JPS59111421A - Oscillator - Google Patents

Abstract

PURPOSE:To obtain an oscillator having resistance to voltage and temperature fluctuation by stopping the oscillating operation temporarily at each TV horizontal oscillating period and controlling the oscillator so that the phase of a pulse generated at a prescribed order number from the starting point of time of the restarted oscillating operation is made always coincident with the TV period. CONSTITUTION:The phase when a pulse 14 changes from level 1 to level 0 as shown in Figure, is fluctuated as shown by a wave line to a phase (a) of a pulse 15 in response to a frequency of an oscillator output 6. In order to control the frequency of an oscillator 5 so that the phase of the pulse 14 changing from level 1 to level 0 is the phase (a) at all times, the feedback control is attained so as to keep the relation of f0=(n-1)/(T1-t), where f0 is the oscillating frequency of the oscillator 5, and T1 and (t) are time shown in Figure. The fluctuation of (t) being a cause to the fluctuation of the oscillating frequency f0 is neglected by making T1>t, and the fluctuation of the frequency due to temperature and voltage fluctuation is excluded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an oscillation device used in a synchronization signal generation circuit of an imaging device using a solid-state imaging device, and in particular to an oscillation device that stabilizes the oscillation frequency. It is.

[Prior art]

A solid-state image sensor photoelectrically converts light incident on the surface of the device using a photoelectric conversion device such as a photodiode arranged two-dimensionally on the surface of the device or a photoelectric conversion film formed on the surface of the device.
It is an element that can read optical information as an electrical signal by sequentially scanning a large number of two-dimensionally arranged signal detection sections in the horizontal and vertical directions. Therefore, in an imaging device using a solid-state imaging device (hereinafter referred to as a solid-state imaging device), the horizontal frequency (hereinafter referred to as fH) of a television signal is generally used to scan signal detection units arranged in the horizontal direction and sequentially read out signals. A clock pulse (hereinafter referred to as a horizontal clock pulse) having a repetition frequency that is an integral multiple of is used. This reason.

I will explain next.

Since the video signal output from the solid-state image sensor is obtained in synchronization with the horizontal clock pulse, the phase of the horizontal clock pulse with respect to the horizontal period of the television signal determines how the image captured by the imaging device is displayed on the screen of the monitor television receiver. Determines the image position on the screen during playback. Hence the horizontal clock.

If the phase of the pulse varies with respect to the horizontal period of the television signal, the position of the reproduced image on the screen will vary, resulting in a very unsightly image. Therefore, the horizontal clock pulse is f
The above-mentioned phase shift is prevented by setting the frequency to an integral multiple of g.

By the way, as the horizontal clock pulse frequency, the above fH
A periodic signal generating circuit having the configuration shown in FIG. 1 has already been proposed as a periodic signal generating circuit that does not cause the above-mentioned phase shift even if a free frequency is set without being limited to an integer multiple of . In Figure 1, an oscillator 1 that oscillates at a frequency that is an integral multiple of fH.
From the output of , a pulse 4 having a repetition frequency fg as shown in FIG. 2 is obtained via a frequency divider 2° decoder 6 known in digital circuit technology. TH in FIG. 2 indicates one horizontal scanning period <1/fH"). This pulse 4 is input to an oscillator 5 for generating horizontal clock pulses. The waveform of the output 6 of the oscillator 5 is shown in FIG. .oscillator 5, pulse 4 is 1
If it is configured so that it oscillates when the level is "0" and the oscillation operation stops when the level is 0, the output 6 will have the waveform shown in FIG. 26. This output 6 is converted into a wave by an inverter circuit, which is a known digital circuit (not shown).

If the shape is shaped, the pulse shown in FIG. 2 is obtained.

If this is used as a horizontal clock pulse, the phase is controlled to be constant for each horizontal period, so it can be used not only when the horizontal clock pulse has a repetition frequency that is an integral multiple of fg, but also when it is not necessarily an integral multiple of fH. The above-mentioned image position fluctuation does not occur.

As a specific example of the oscillator 5, the configuration shown in FIG. 3 can be considered.

In FIG. 3, numeral 8 is a digital circuit called a well-known seamit trigger two-man NAND gate, and resistor 9. When the capacitor 10 is connected as shown in the figure and the pulse 4 is applied to the input terminal 11, the circuit becomes a circuit that oscillates when the input is at the "1" level and stops the oscillation operation when the input is at the "0" level. The output 6 is as shown in FIG. 26.

Generally, in solid-state image sensors, in the horizontal direction.

Photoelectric conversion elements arranged in a row (one element is called one pixel)
are sequentially selected in one horizontal scanning period to read out signals, and at this time, one pixel is selected for each horizontal clock pulse. By the way, in television signals, there is a period during one horizontal scanning period during which the video signal is not required, called the horizontal blanking period, so a solid-state image sensor normally corresponds to the period excluding the horizontal blanking period from the horizontal scanning period. It has a horizontal pixel count of For example, if the frequency of the horizontal clock pulse is fH 45
A deer solid-state image sensor with a magnification of 5 times and a horizontal pixel count of about 680 is known.

Therefore, even if the horizontal clock pulse stops during part of one horizontal period as shown in FIG. 2, there is no problem in reading signals from the solid-state image sensor.

However, the oscillator illustrated in FIG. 3 generally has a characteristic that its oscillation frequency fluctuates significantly as the operating power supply voltage fluctuates or the temperature of the circuit elements fluctuates. When the oscillation frequency of the oscillator 5 changes, the pulse 4 becomes 10 in FIG.
The phase of the output 60 at the point when it changes from "level" to "1 level" remains constant, but the repetition period of the output 6 expands and contracts, and the repetition period of the horizontal clock pulse 7 changes as well. This results in a change in the horizontal size of the reproduced image on the receiver. That is, in the conventional example,
There is an inconvenience in that the horizontal size of the reproduced image expands or contracts with fluctuations in the operating power supply voltage or temperature of the circuit.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an oscillation device that eliminates the above-mentioned disadvantages of the prior art and can maintain a stable oscillation frequency even with fluctuations in operating power supply voltage or temperature fluctuations of circuit elements.

[Summary of the invention]

The features of the present invention are to achieve the above objects.

The oscillator 5 for generating horizontal clock pulses in the configuration shown in FIG. 1 is constituted by a so-called voltage-controlled oscillator whose oscillation frequency is variable by an external control voltage, and its oscillation operation is temporarily stopped as described above. , the oscillator output 6 or the horizontal clock pulse 7 starts from the time when the oscillation operation starts again.
0 a predetermined number of pulse phases and a phase of a pulse generated in the same way as pulse 4 from an oscillator that is an integral multiple of fH and has a repetition frequency of fH and a phase different from the oscillator 50 operation start phase. The oscillation frequency of the voltage-controlled oscillator 5' is controlled so that the oscillator 5' always matches the oscillation frequency of the voltage-controlled oscillator 5'.

[Embodiments of the invention]

The present invention will be explained below with reference to the drawings.

FIG. 4 is a block diagram of an embodiment of the present invention, and FIG. 5 is a waveform diagram of signals of various parts thereof, and parts having the same functions are denoted by the same reference numerals. In FIG. 4, from an oscillator 1 that oscillates at an integral multiple of bl to a branching unit 2. Pulse 4 of repetition frequency fy obtained through decoder 6 is inputted to oscillator 5 for horizontal clock pulse generation through OR circuit 31, which is a well-known digital circuit, and the control of oscillator 5 by pulse 4 is shown in FIG. It will be the same as the conventional example. In FIG. 4, the output 6 of the oscillator 5 is passed through the frequency divider 12° decoder 13 to
A pulse 14 having the pulse phase of the second oscillation output 6 is obtained from the point in time when the oscillator 5 briefly stops and then starts oscillating. In this case, the frequency divider 12 is supplied with the oscillator 5 by the pulse 4.
If the configuration is such that the reset is applied at the same timing as the operation stop control, it is easy to obtain the pulse 14 using known digital circuit technology. OR circuit 3 for pulse 14
If the oscillator 5 is controlled using the second input of 1, the oscillator 5 will start oscillating at the phase where the pulse 4 changes from the "0" level to the "1" level, and after the start of oscillation, the second oscillation output will be output. Since the oscillation is controlled to stop at the pulse phase of 6, the oscillation output 6 has the waveform shown in FIG.

On the other hand, in the same way as pulse 4 is obtained from the output of oscillator 1, it has a phase (α in Fig. 5) different from the oscillation operation start phase of oscillator 5 (d in Fig. 5), and the repetition frequency is fH. 15 pulses are obtained. The pulses 14 and 15 are input to the phase detection circuit 16, and the detection output is sent to the low-pass filter 17.
The smoothed DC voltage is sent to a voltage controlled oscillator 5.
The frequency control voltage 18 is assumed to be 18.

The fact that the oscillation frequency of the oscillator 5 can be stabilized by the above will be explained below. In Fig. 5, pulse 14 is 11.
The phase changing from "level to 10" level varies according to the frequency of the oscillator output 6, as shown by the broken line with respect to the phase a of the pulse 15.

If the frequency of the oscillator 50 is controlled so that the phase of the pulse 14 that changes from the @1' level to the 10'' level is always the phase a, the following relationship is maintained.

fO= (n -1)/(TI -t) ... (1
) However, °fo is the oscillation frequency of oscillator 5, T1 and t
are the times shown in FIG. 5, respectively. here.

Although the stability of the value of T1 depends on the frequency stability of the oscillator 10, by configuring the oscillator 1 with a crystal oscillator or the like, T1 can be kept at a substantially constant value. Therefore (1)
f in Eq. The factor that causes this to vary is the variation in t. If the oscillator 5 has the conventional configuration shown in FIG. 3, it is inevitable that the above-mentioned t will vary due to fluctuations in the operating power supply voltage or fluctuations in the temperature of the circuit elements. However, in equation (1), T
If 1 is made sufficiently large, f due to the fluctuation of t. fluctuations can be reduced. For example, if T1 is set to 50 times t,
Even if t fluctuates between t++ (fluctuation range of 50 factors), the fluctuation range of fo can be suppressed to approximately ±1 factor. When the conventional configuration shown in Fig. 3 is used for the oscillator 5 shown in Fig.
25° C.±35° C.), it is difficult to avoid frequency fluctuations of about 10 to 20 degrees. On the other hand, according to the embodiment of the present invention shown in FIG. 4, frequency fluctuations can be reduced by setting the ratio between t and current according to the desired frequency stability.

FIG. 6 shows an embodiment of the phase detection circuit 16 shown in FIG. 4, and FIG. 7 shows signal waveforms of various parts thereof. OR circuit 19. AND circuit 20. p channel I'vlO8) run raster 21.
N-channel MO8) transistor 22 is connected as shown. MOS) S of transistor.

D and G represent the source, drain, and gate, respectively, and p
The source of the channel MO8) transistor 21 is connected to a power source having a positive polarity with respect to the ground, and the source of the n-channel MO8) transistor 22 is connected to the ground. Input terminal 23
．． The pulses 14 and 15 of FIG. 5 are input to 24, respectively. The phase of the pulse 140 is as shown by the dashed line b with respect to the phase a of the pulse 15.

When this occurs, a “0” level is output to the OR circuit output 25. At this time, the p-channel MO8) transistor 21 becomes conductive, and the output 26 becomes a positive voltage with respect to ground only while the OR circuit output 25 is at the °0'' level.Also, the phase of the pulse 14 is C as shown by the broken line in FIG. When it becomes like this, the AND circuit output 27 becomes the degree 1'' level, and the n-channel MO8) transistor 22 becomes conductive.

The output 26 is at ground potential only while the AND circuit output 27 is at "1" level. Furthermore, the pulse 140 phase is shown in Fig. 7a.
If it matches the pulse 15, the OR circuit output 25 remains at the "1" level, the AND circuit output 27 remains at the 0" level, and the output 26 becomes open.

Therefore, by inputting the output 26 of the phase detection circuit shown in FIG. 6 to a known low-pass filter 17, a voltage obtained by integrating the output 26 can be obtained. That is, when the pulse 14 is in phase C, the DC voltage gradually increases, and when the pulse 14 is in phase C, the DC voltage gradually decreases toward the ground potential. , this can be used as the frequency control voltage 18 in FIG.

FIG. 8 shows an embodiment of the oscillator 5 of FIG. 4.

The oscillator in FIG. 8 is basically the same as that in FIG.

The difference is that instead of the capacitor 10 in FIG. 6, a known variable capacitance diode whose capacitance value can be varied by the applied reverse DC voltage is used. Note that the capacitor 29 is for direct current or for other purposes, and usually has a sufficiently larger capacitance value than the capacitance value of the diode 28. Therefore, the oscillation frequency of the oscillator shown in FIG. 8 can be varied by changing the capacitance value of the diode 28. In other words, with the configuration shown in FIG. 8, a voltage controlled oscillator whose oscillation frequency can be varied by the DC voltage applied to the input terminal 60 can be realized. Furthermore, the capacitance value of the diode 28 decreases as the applied reverse voltage increases, so as the applied DC voltage of the input terminal 30 increases, the oscillation frequency of the oscillator increases, and as the applied DC voltage decreases, the oscillation frequency decreases. Here, if the frequency control voltage 18 obtained as explained in FIGS. 6 and 7 is inputted to the input terminal 30 of the oscillator in FIG. 8, the phase of the pulse 14 in FIG. The frequency and wave frequency of the oscillator 5 are controlled so as to match the .

FIG. 9 shows another embodiment according to the present invention.

In the figure, the same reference numerals are used for the same functions as in FIG. 4. In FIG. 9, instead of the OR circuit 61 in FIG. 4, a T-type flip-flop (hereinafter TFF
) is used (-), and the circuit operation other than the above circuit section is the same as that explained in Fig. 4. Therefore, the TF
Only the operation of F 32 will be described below. Input the pulse 4 in Figure 10 to the clock input terminal T of TFF" 52. Input the pulse 14 (to the reset terminal), and input the pulse 14 to the output terminal Q.
When the phase changes from the @1 level to the 10'' level, the @1# level changes to the 10'' level, and when the phase changes from the 10'' level to the 1 level, the 0'' level changes from the 10'' level to the 1'' level. Obtain 33 monsters that change into .

A TFF that operates as described above can be easily realized using known technology. The operation of the oscillator 5 can be controlled by the oscillator 63 in exactly the same manner as in the embodiment shown in FIG.

Figures 11, 16, and 15 show configuration diagrams of still other embodiments of the present invention. In the drawings below, parts with the same functions as those in the above description are designated by the same reference numerals.

The difference between the embodiments shown in FIGS. 11, 16, and 15 from the embodiments shown in FIGS. 4 and 9 is that the pulse 34 that controls the operation stop phase of the oscillator 5 is the same as the pulse described above.

This is because it was established independently from 14.

In FIG. 11, the pulse 34 is converted from the output 6 of the oscillator 5 to the frequency divider 12 and the decoder 1 in the same way as the pulse [14].
Generate via 3. FIG. 12 shows a waveform diagram of each part signal in FIG. 11. The pulse 14 is a pulse having the second phase of the output pulse 6 after the oscillator 5 starts oscillating, as described above. Here, it is easy to obtain a pulse having an m-th phase, which is a larger number than the above-mentioned number of output pulses 6, as the pulse 34. Pulse 34 and pulse 4 to 9th
The pulse 63 is obtained in the same manner as in the embodiment shown, and therefore the phase of the oscillator output 6 becomes the same at every fixed period TH. Furthermore, the frequency of the oscillator 50 can be stabilized using pulses 14 and 15 in the same manner as described in FIG.

Next, in the embodiment of FIG. 13, similarly to the pulse 14, the oscillator output 6 is converted to the frequency divider 12. A pulse 65 generated via the decoder 16 is phase-delayed by a phase delay circuit 56 to obtain a pulse 64 that controls the stop phase of the oscillator operation. FIG. 14 shows signal waveforms at various parts. pulse 14
The pulse 35 having the first phase of the pulse 6 obtained in the same manner as above is input to the phase delay circuit 36. If a monostable multivibrator, which is a known digital circuit, is used as the phase delay circuit, its output will have a phase delayed by an arbitrary time td from the phase of the pulse 35, and an arbitrary pulse width t.
A pulse 34 of W is easily obtained.

While the pulse width tW of pulse 34 is iW, the phase d of pulse 4 is
If the width is set so that the pulse 34 and the pulse 4 are not included using the TFF 32 explained in FIG.
A pulse 33 is obtained from . The operation control of the oscillator 5 using the pulse 33 and the frequency control of the oscillator 50 using the pulses 14 and 15 are the same as in the conventional example described above.

Further, as explained above, the delay time td of the pulse 64
can be set arbitrarily, so the phase of the pulse 65 can be set arbitrarily. In other words, the value of l is arbitrary as long as it is within the desired number of pulses 6 during the island period, and pulses 35 and 14 may be shared in FIG. 13.

Furthermore, in the present invention, if the phase of FIG. Even if it is set arbitrarily according to the required number of pulses, the frequency stabilization function of the oscillator 5, which is the object of the present invention, will not be impaired in any way. Therefore, the phase of FIG. 14e or the Melf 340 phase need not be added to pulse 6.

Therefore, in the embodiment shown in FIG. A pulse 37 with a repetition period TH is generated in the same way as pulse 4 or pulse 15 through the decoder 3, and this pulse 37 is input to a phase delay circuit 36 similar to the embodiment shown in FIG. get. If the delay time and pulse width of the pulse 34 are appropriately set in the phase delay circuit 36 in the same way as the explanation in the embodiment shown in Fig. 16, the embodiment shown in Fig. Inventions can be realized.

Although TFF 32 is used to obtain the pulse 33 in FIGS. 9.11 and 13.15, it is well known in digital circuit technology that similar functions can be achieved using circuits other than TFF.

〔Effect of the invention〕

As explained above, according to the present invention, the oscillator for generating horizontal clock pulses temporarily stops for each horizontal cycle of the television signal, and from the time when excavation starts again, the pulse phase of the predetermined number of the oscillator outputs is always maintained. Since the oscillation frequency is controlled to be the repetition period of the horizontal period of the television signal, the oscillation frequency of the oscillator can be stabilized against fluctuations in the operating power supply voltage or temperature.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional example, FIG. 2 is a pulse waveform diagram of each part thereof, FIG. 3 is a configuration diagram of the oscillator 5 shown in FIG. 1, FIG. 4 is a configuration diagram of an embodiment of the present invention, and FIG. The figure is a pulse waveform diagram of each part, FIG. 6 is an example configuration diagram of the phase detection circuit of FIG. 4, and FIG.
The figure is a pulse waveform diagram of each part, and Figure 8 is the oscillator 5 of Figure 4.
Figures 9.11 and 15.15 are configuration diagrams of different embodiments of the present invention, and Figures 10.12.14 and 10.12.14 are pulse waveforms of various parts in the configuration diagrams of Figures 9, 11, and 15, respectively. It is a diagram. 1.5 ... Oscillator 2.12 ... Frequency divider 6.16 ... Decoder 16 ... Phase detection circuit 17 ... Low-pass filter Fig. 1 Fig. 2 No. 3 Rule No. 4 WIJ 151-; Kudai Otsu Figure δ Figure /I Figure 72 Figure 3, 0' Figure 75

Claims (1)

[Claims] A first oscillation means and an output of the first oscillation means. By dividing the force, the repetition frequency is the same for the first, third and second
pulses, each with a different phase. means for generating, and an oscillation operation starts at the first phase;
and voltage-controlled second oscillation means whose oscillation frequency is controlled by a control voltage, and which second oscillation means divides its oscillation output from the time when it starts its oscillation operation in the first phase. means for generating a pulse having a third phase corresponding to the predetermined number of output pulse phases;
phase detection means for phase detecting the pulse phase of the pulse phase and the third pulse phase, and the detected output is passed through a low-pass filter circuit to become the frequency control voltage of the second oscillation means; oscillation stop means for stopping the oscillation operation of the second oscillation means at a fourth phase that is simultaneous with the phase or later and before the first pulse phase; An oscillation device characterized in that its output is a device output.