JP3454369B2 - Imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus, and more specifically, to a drive pulse for driving an image pickup element constituting an image pickup device to extract a signal output,
The present invention relates to an image pickup apparatus including a pulse generation circuit that generates at least a sampling pulse for sampling and holding the extracted signal output .

Generally, there is reset noise at the time of signal detection as one of the main random noise sources generated when a solid-state image pickup device is driven by a drive pulse to extract a signal output. Correlation is a method for reducing such noise. The double sampling method is known. For the purpose of implementing this correlated double sampling method, it is necessary to generate the clamp pulse prior to the sampling pulse for sampling and holding the signal output.

The present invention specifically relates to such driving pulse and sampling pulse generated from a pulse generating circuit.
The present invention relates to such a phase adjustment for enabling an optimum phase adjustment between the two images and achieving a high quality display image.

[0004]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a conventional circuit for showing how the drive pulse, clamp pulse and sampling pulse described above are generated from a pulse generation circuit and function. In the figure, 1 is an image pickup element, 2 is a pulse generation circuit for generating pulses at various timings, and 3 is a sample hold circuit (hereinafter abbreviated as S / H circuit).
Is. In the S / H circuit 3, 31 is a DC blocking capacitor, 32 is a clamp switch, 33 is a voltage source that gives a clamp potential, 34 is a sampling switch, 3
Reference numeral 5 is a holding capacitor.

FIG. 3 is a timing chart showing the timing relationship of the pulses of each part in FIG. In FIG. 3, XC is a basic clock, H1 and H2 are pulses for horizontal transfer of charges of each pixel in the image sensor 1, and RG is a pulse used when converting the charges into a voltage.
The H1 and H2 pulses and the RG pulse are collectively referred to as a drive pulse.

In addition, in FIG. 3, Vo is the output of the image pickup device 1, CP is a pulse for clamping the output Vo, and SH.
Is a pulse for sampling the output Vo, but the respective pulses of RG, CP and SH in FIG. 3 are shown as having an optimum timing positional relationship with each other.

Returning to FIG. 2, the pulse generation circuit 2 is supplied with the basic clock XC, and by this, drive pulses (H1 and H2 pulses, RG pulse, etc.) of the image pickup device 1 and sample / hold processing in the S / H circuit 3 are performed. Necessary pulses (clamp pulse CP, sampling pulse SH) are created and generated. That is, in the pulse generation circuit 2, these pulses were generated from an oscillator (not shown) at the required timing.

The circuit operation will be described below with reference to FIGS. The image sensor 1 converts the charge transferred by the vertical drive pulse and the horizontal drive pulses H1 and H2 from the charge to the voltage by the pulse RG, and outputs the output Vo. However, the output Vo contains noise (random noise such as the reset noise described above) that is substantially uniform for each pixel.

Therefore, in order to remove noise, S / H
The circuit 3 clamps the output Vo in the voltage stable period within the floating period Tf by switching the clamp switch 32 by the clamp pulse CP, and further, in the signal output period Ts, the sampling pulse SH.
Therefore, by switching the sampling switch 34 to perform sampling, only necessary video components are extracted and noise is removed.

The correlated double sampling circuit is described in "Television Image Information Engineering Handbook" edited by the Television Society, November 30, 1990, page 180, published by Ohmsha Co., Ltd., and other related conventional techniques. Japanese Patent Application Laid-Open No. 4-51787 can be cited as a document showing the above.

[0011]

In the above prior art, in order to optimize the phase of each pulse (driving pulse, CP pulse, SH pulse), analog signals such as resistors and capacitors (not shown) are provided in the pulse generation circuit 2. This has been dealt with by using a delay element. The timing of the pulse that can be generated in the pulse generation circuit 2 can be adjusted by the oscillation cycle of the oscillator or its (1/2) cycle. An example of the adjustment will be described with reference to FIG.

In FIG. 3, when the period of the oscillator is T, its output pulse becomes a digital pulse (basic clock) indicated by XC. Therefore, the pulse (basic clock) cannot be changed in a time shorter than T / 2. Therefore, if a pulse that becomes H (high level) for (T / 2) period is generated at the same period as the pulse H1. If so, only four types of P1 to P4 can be generated.

Therefore, none of the pulses RG, CP and SH having the timings shown in FIG. 3 belong to the above-mentioned four types, and therefore cannot be generated directly.
Therefore, the pulse RG is generated by delaying the pulse P4 by the delay element for the time t1, similarly, the pulse CP is generated by delaying the pulse P1 by the delay element for the time t2, and is generated by the pulse SH. , Pulse P
3 is generated by delaying 3 by the delay element for the time t3.

However, in the case where the delay time varies depending on the delay elements used for such delay, if the delay elements having such variations are used, each pulse (RG, C
There is a problem that it is difficult to realize relative optimum phase adjustment between P and SH). In addition, considering the miniaturization and reduction of the number of parts by rationalizing the circuit,
I want to reduce the number of external parts
The delay element is not externally attached to the IC, and a circuit equivalent to it is desired to be built in the IC.

However, in this case, since the process performances are almost the same in the same IC, it is considered that there is no variation in the delay time per delay element stage. Since there is a variation in time and a delay element that varies is used, it becomes difficult to adjust the relative phase between the pulses (RG, CP, and SH).

Therefore, an object of the present invention is to digitize an analog delay element for phase adjustment of drive pulses and the like, which has been externally attached to an IC in the past, to incorporate the digitized IC into the IC and further adjust the drive pulse to an optimum phase. It is an object of the present invention to provide an image pickup apparatus capable of improving the image quality of a display image by providing a phase adjusting unit capable of performing the above.

[0017]

In order to achieve the above object, according to the present invention, a drive pulse for driving an image pickup device constituting an image pickup device to take out a signal output, and a drive pulse taken out.
A sampling pulse for sampling and holding the signal output, and an imaging device having a pulse generating circuit for generating at least, in addition to the pulse generating circuit,
A variable delay circuit, a phase detection circuit, and a control circuit are provided.

[0018]

When the pulse generating circuit is supplied with the basic clock, the pulse generating circuit generates a drive pulse and a sampling pulse , the phases of which are adjusted in units of 1 or (1/2) period of the clock, at predetermined phases. The variable delay circuit, the driving
Of the motion pulse and the sampling pulse , when the drive pulse is the reference pulse, other pulses except the reference pulse are input, and when the unit gate delay time is d, the value n
(However, n is an integer) is stored, and the time d times that n times is stored.
-The input pulse is delayed by n before being output.

The phase detection circuit takes in the reference pulse and the delay pulse which is the output pulse of the variable delay circuit,
Phase data indicating the phase relationship of the delayed pulse with respect to the reference pulse is detected. Control circuit, given the detected the phase data from the phase detection circuit, the time d · n Toka et in the variable delay circuit with the phase data, the unit
The average delay time d of the gate is calculated, and the average delay time d
The value of n necessary for delaying the delay pulse from the delay time d until the delay pulse becomes a known optimum phase with respect to the reference pulse is newly calculated as phase information by calculation, and the variable delay is obtained. The value of n stored in the circuit is rewritten with the phase information.

Therefore, the image pickup apparatus according to the present invention has the conventional I
Delete the delay analog element that was externally attached to C,
Even if a delay element to replace it is built into the IC, the delay time can be controlled regardless of the variation in the process performance of each IC, and as a result, the image sensor can be driven and the sample and hold processing of its output can be performed at the optimum timing. Higher image quality can be achieved.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part (phase adjusting means for adjusting a relative phase between a drive pulse, a clamp pulse, and a sampling pulse) in an image pickup apparatus as an embodiment of the present invention. In the figure, 1 is an image sensor, 2 is a pulse generation circuit, 3 is an S / H (sample hold) circuit, 4 is a variable delay circuit, 5 is a phase detection circuit, and 6 is a control circuit.

In FIG. 1, the image pickup device 1 converts light (optical image) input from the outside into electric charges, and transfers the electric charges to an output portion by driving pulses (vertical and horizontal driving pulses H1 and H2), At the timing of the reset gate pulse RG, the transferred charges are converted into a voltage and then output as an output Vo.

The S / H circuit 3 outputs the output signal V of the image pickup device 1.
When o is input, the clamp pulse CP and the sampling pulse SH are used to remove noise by the correlated double sampling method described above, and only the necessary output signal is output. The pulse generation circuit 2 is provided with the timing data C1 for determining the rise and fall of the generated pulse from the control circuit 6 and is provided with a first storage means for storing this, and is supplied with the basic clock XC of the cycle T. Then, the pulses T1 to T3 are generated based on the timing data C1.

The variable delay circuit 4 comprises a second storage means for storing the delay data C2 given from the control circuit 6,
When the pulse T2 is supplied from the pulse generation circuit 2, the pulse T4 generated by delaying the pulse T2 based on the delay data C2 is output. The phase detection circuit 5 outputs the reference pulse T3 from the pulse generation circuit 2 to the variable delay circuit 4
When the pulse T4 is supplied from the device, the phase data C3 indicating the phase relationship of the pulse T4 with respect to the reference pulse T3 is detected and output.

The control circuit 6 uses appropriate timing data C
1 is supplied to the first storage means in the pulse generating circuit 2, and the pulse generating circuit 2 receives the timing data C1.
From the basic clock XC of the period T based on
T3 is generated and output at a predetermined timing. When the phase data C3 is supplied from the phase detection circuit 5, the control circuit 6 also receives the pulse T relative to the reference pulse T3.
4 is obtained, the delay data C2 for obtaining the optimum phase relation is calculated by an arithmetic means (not shown), and the delay data C2 is stored in the second storage means in the variable delay circuit 4. Then, the variable delay circuit 4 delays the input pulse T2 based on the delay data C2.

Pulse T1 is a pulse that does not require phase adjustment (that is, a pulse that can be regarded as a reference pulse), pulse T2 is a pulse that requires phase adjustment (clamp pulse or sampling pulse), and pulse T3 is when performing phase adjustment. The reference pulse of the phase of, and the pulse T4 is a pulse obtained by delaying the pulse T2, and the pulses T1 to T4 are not always one kind of pulse, for example, the pulse T1 is Image sensor 1
It corresponds to the horizontal drive pulses H1 and H2 and the vertical drive pulse for driving, and the drive pulse for performing signal processing.

Further, the pulse T2 is a pulse before the delay gate pulse RG of the image pickup device 1, the clamp pulse CP in the S / H circuit 3 and the sampling pulse SH are all delayed, and the pulse T4 is The pulse including the whole thereof is a pulse after being delayed, and the pulse T3 is a pulse corresponding to the horizontal drive pulse H1.

Therefore, when there are a plurality of pulses T2 that require delay and these pulses require different delays, the variable delay circuit 4 or the phase detection circuit 5 also
In the case of FIG. 1, for example, three (RG, CP, S
H) is required for each, but it is omitted and only one set is described. The same applies to the following description and the drawings used for the description.

Next, a more detailed operation of each circuit in FIG. 1 will be described. FIG. 4 is a timing chart for explaining the phase adjustment in the variable delay circuit 4. Now, it is assumed that the pulse T4 delayed by the time t (0 <t <(T / 2)) from the falling timing of the reference pulse T3 is required.

In the pulse generating circuit 2 (FIG. 1), when the period of the oscillator included in the generating circuit 2 is T, the timing data C1 given from the control circuit 6 can set the timing only at intervals of T / 2. Therefore, it is not possible to generate a pulse having a timing such as T4 (FIG. 4). Therefore, the pulse T4 is generated by delaying the pulse T2 (FIG. 1) in the variable delay circuit 4 whose delay time can be set more finely than T / 2.

It is assumed that the variable delay circuit 4 can delay the input signal by the time d and output the delayed signal C2 provided from the control circuit 6. FIG. 5 is a block diagram showing a specific circuit example of the variable delay circuit 4 and the phase detection circuit 5 in FIG. In FIG. 5, 401-
40n are delay circuits, 411-41n are switches, and 42 is the second storage means.

In the delay circuits 401 to 40n, delay elements constituted by gates having a delay time d are 1, 2,
3, to n connected in series, each having a delay time of approximately d, 2 · d, to nd. Each of the switches 411 to 41n includes a delay circuit 40.
The non-passage (terminal a side) and the passage (terminal b side) of 1 to 40n are selected. These selections are made in the second storage means 4 respectively.
It is determined by the delay data C21 to C2n supplied from 2 (connected to the terminal a side when the logic is 0, and to the terminal b side when the logic is 1).

The second storage means 42 stores the n-bit delay data C2 consisting of C21 to C2n supplied from the control circuit 6, and supplies it to the switches 411 to 41n as a switching control signal. When the delay time in the variable delay circuit 4 is D (C2), the delay time D (C2) is expressed by the following equation 1. D (C2) = C2 · d + D ′ (Equation 1) Here, D ′ is the total of the error in the delay time due to each element variation and the time required to pass through the switch.

The phase detection circuit 5 is composed of a flip-flop (hereinafter referred to as FF) 51. When the pulse T4 is used as data and the reference pulse T3 is supplied as a clock, the pulse T4 is latched at the rising edge of the reference pulse T3. Then, the output (phase data) C3 is supplied to the control circuit 6.

The control circuit 6 is provided with a calculating means (not shown), and the calculating means calculates the average delay time d per delay element from the phase data C3 supplied from the phase detecting circuit 5, and further, The delay data C2 supplied to the variable delay circuit 4 is obtained from the delay time d.

FIG. 6 shows the delay data C in the control circuit 6.
6 is a flowchart showing an example of an operation for obtaining 2. The delay data C2 will be described below mainly using FIGS. 3, 4 and 6.
A method of performing the phase adjustment by obtaining is described.

(Step S1) Timing data C1
(See FIG. 1) is set to be the pulse P1 in FIG. Also, the delay data C2 is initialized to 0.
At this time, as shown in FIG. 4, it is assumed that there is an initial phase difference of time t ′ between the pulse H1 (that is, the pulse T3) and the pulse T4. (Step S2) The FF 51 latches the pulse T4 at the rising edge of the reference pulse T3, and supplies the latched phase data C3 to the control circuit 6.

After that, the control circuit 6 performs the following processes (step S3) to (step S7). (Step S3) Add 1 to the delay data C2 and supply the added delay data C2 to the variable delay circuit 4. Thus, after changing the delay time, step S2 is executed again.

(Step S4) Steps S2 and S3 are repeated, and the value M of the delay data C2 is stored immediately after the midway phase data C3 becomes H (high level). (Step S5) Immediately after the phase data C3 becomes L (low level) again, the value N (N> M) of the delay data C2 is stored, and steps S2 and S3 are stopped. (Step S6) The H (high level) section of the pulse T4 is T / 2, and that section is the delay element (NM).
The following Equation 2 is obtained because of the number of steps. (NM) d = T / 2 (Formula 2)

Then, the average delay time d per one stage of the delay element shown in the following expression 3 is obtained from the expression 2. d = T / {2 (N−M)} (Equation 3) Further, the following Equation 4 indicating the initial phase difference t ′ is obtained. t ′ = (T / 2) −M · d (Equation 4)

Therefore, in order to set the phase difference between the pulse T4 and the pulse T3 to t, the pulse T4 may be delayed by the delay element by a value obtained by subtracting the initial phase difference t'from the time t, that is, t-t '. From the equations 3 and 4, this delay time t−
The following Equation 5 indicating the number of stages of delay elements required to obtain t ′, that is, the value of the delay data C2 is obtained. C2 = (t−t ′) / d (Equation 5)

(Step S7) The optimum delay data C2 calculated from the equations 3 to 5 is supplied to the variable delay circuit 4,
The variable delay circuit 4 changes the delay time based on the delay data C2. However, the calculation processing in the above phase adjustment method is an example, and if it is realized by software,
The processing method can be changed.

As described above, according to the present embodiment, in the image pickup apparatus, the delay analog element is not used, and a delay circuit corresponding to this is incorporated in the IC, whereby the circuit can be rationalized, and the image pickup element Since it is possible to adjust the pulse necessary for the driving and the sample hold processing so as to have an optimum timing, it is possible to improve the image quality.

Next, another embodiment of the present invention will be described. FIG. 7 is a block diagram showing a main part (phase adjusting means) in an image pickup apparatus as another embodiment of the present invention. 7 is different from FIG. 1 in that the variable delay circuit 4 is changed to the variable delay circuit 7 and the basic clock XC is input. 8 is a block diagram showing a specific example of the variable delay circuit 7 in FIG. 7, and FIG. 9 is a timing chart for explaining the phase adjusting method.

The phase adjustment method in this embodiment will be described below with reference to FIGS. In FIG. 8, reference numeral 4 denotes the variable delay circuit 4 in the above embodiment, 71 and 7
Reference numerals 2 are flip-flops, respectively. Variable delay circuit 4
Is the timing data C based on the input basic clock XC.
The delayed clock XC 'is generated by delaying based on 2 and output, and the FF 71 latches the pulse T2 at the rising edge of the delayed clock XC', outputs the pulse 74A, and outputs the pulse FF 72.
Latches pulse 74A at the falling edge of delayed clock XC ', outputs pulse 74B, and AND74 outputs pulse 74A.
A and pulse 74B are input and pulse T4 is output.

That is, the variable delay circuit 7 delays the pulse T2 based on the control signal (delay data) C2 and outputs the pulse T4, as in the variable delay circuit 4 in the previous embodiment. Therefore, by operating the other circuits in the same manner as in the previous embodiment, it is possible to obtain the timing data C2 for making the unit delay time d and the pulse T4 the optimum phase.

Now, as shown in FIG. 9, when the pulse T4 generated by delaying the pulse T2 by the time t with respect to the reference pulse T3 is required, the reference pulse T
By delaying the basic clock XC synchronized with 3 by a time t, a delayed clock XC 'is generated, the pulse T2 is latched at the rising edge of the delayed clock XC', and the output pulse 74A after latching is further delayed by the delayed clock XC '. The optimum phase pulse T4 is obtained by latching at the falling edge and ANDing the output pulse 74B after latching and the pulse 74A.
Can be generated.

As described above, also in this embodiment, the effect of improving the image quality can be obtained as in the case of the above embodiment. Further, another embodiment of the present invention will be described. FIG. 10 is a main part (phase adjusting means) in an image pickup apparatus as still another embodiment of the present invention.
It is a block diagram showing. 10 is different from FIG. 1 in that a circuit for generating a pulse T2 requiring a delay is separated from the pulse generating circuit 2 and a pulse generating circuit 8 for generating only a pulse T4 delayed from the pulse T2. Is provided.

The phase adjusting method in this embodiment will be described below with reference to FIG. 10, when the basic clock XC is supplied, the pulse generation circuit 2 generates a pulse T1 and a reference pulse T3 that do not require delay. When the basic clock XC is supplied, the variable delay circuit 4
Delays the basic clock XC based on the delay data C2 and outputs it as a delayed clock XC '. Then, when the delay clock XC ′ is supplied, the pulse generation circuit 8
Generate pulse T4. The pulse T4 is the delayed clock X
Since the signal is delayed corresponding to C ′, the pulse T4 having the optimum phase can be obtained by delaying the basic clock XC by the same processing as in the above embodiment. As described above, also in this embodiment, the effect of improving the image quality can be obtained as in the case of the above embodiment.

Further, another embodiment of the present invention will be described.
FIG. 11 is a block diagram showing a main part (phase adjusting means) in an image pickup apparatus as still another embodiment of the present invention.
11 is different from FIG. 1 in that a temperature sensor 9 is provided.

The phase adjusting method in this embodiment will be described below with reference to FIG. In FIG. 11, the temperature sensor 9 detects the temperature inside the image pickup apparatus and outputs temperature data C4. When the temperature data C4 is supplied, the control circuit 6
Rewrites the second phase information in the second storage means based on the temperature characteristic.

When the temperature data C4 is supplied from the temperature sensor 9 to the control circuit 6 in addition to the calculating means for obtaining the delay data C2 as in the above-described embodiment, the temperature characteristics for correcting the delay data C2 based on the temperature characteristics. Compensation means is provided, and the delay data C2 in the second storage means is rewritten according to the result of the compensation.

The temperature characteristic correction means includes, for example, a calculation means and a method of correcting the delay data C2 based on the temperature characteristics by calculation, or a conversion table in which the delay data C2 corresponding to the temperature data C4 is stored. There is a method of correcting the delay data C2 based on the conversion table.

As described above, in the present embodiment, the same effect of improving the image quality as that of the above embodiment can be obtained without being affected by the temperature when the image pickup apparatus is used. For example, if the temperature is adjusted automatically in advance so that the optimum phase will be achieved during production in the factory, and if the temperature during actual use is significantly different from the temperature during adjustment in the factory, the phase may not be optimum. If the temperature correction means is provided, there is an effect that readjustment can be performed according to the temperature at that time.

[0055]

According to the present invention, in the image pickup apparatus, the phase adjustment of the drive pulse is performed not by the analog element external to the IC but by the delay element built in the IC, and is influenced by the process variation of the IC. Since the optimum phase adjustment of the drive pulse can always be performed without the need for higher image quality.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a main part (a phase adjusting unit that adjusts a relative phase between a drive pulse, a clamp pulse, and a sampling pulse) in an image pickup apparatus as an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional circuit for showing how a drive pulse, a clamp pulse, and a sampling pulse are generated from a pulse generation circuit and function.

FIG. 3 is a timing chart showing a timing relationship of pulses at respective parts in FIG.

FIG. 4 is a timing chart for explaining phase adjustment in the variable delay circuit 4 of FIG.

5 is a variable delay circuit 4 and a phase detection circuit 5 in FIG.
3 is a block diagram showing a specific circuit example of FIG.

FIG. 6 is a flowchart showing an example of an operation of obtaining delay data C2 in the control circuit 6 of FIG.

FIG. 7 is a block diagram showing a main part (phase adjusting means) in an image pickup apparatus as another embodiment of the present invention.

8 is a block diagram showing a specific example of the variable delay circuit 7 in FIG.

FIG. 9 is a timing chart for explaining a phase adjustment method.

FIG. 10 is a block diagram showing a main part (phase adjusting means) in an image pickup apparatus as still another embodiment of the present invention.

FIG. 11 is a block diagram showing a main part (phase adjusting means) in an image pickup apparatus as still another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Imaging element, 2 ... Pulse generation circuit, 3 ... S / H (sample hold) circuit, 4 ... Variable delay circuit, 5 ... Phase detection circuit, 6 ... Control circuit, 7 ... Variable delay circuit, 8 ... Pulse generation circuit , 9 ... Temperature sensor, XC ... Basic clock, XC '
... delay clock, T1 to T4 ... pulse, C1 timing data, C2 ... delay data, C3 ... phase data, C4 ...
Temperature data, Vo ... Image sensor output

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroyasu Otsubo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Hitachi, Ltd. Visual Media Research Laboratories (56) Reference JP-A-5-37865 (JP, A) JP-A-2-255908 (JP, A) JP-A-53-38242 (JP, A) JP-A-6-318851 (JP, A) JP-A-6-77819 (JP, A) JP-A-5-268017 (JP, A) International publication 93/14602 (WO, A1) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/30-5/335

Claims (8)

(57) [Claims] 1. A drive pulse for driving an electric charge obtained by photoelectric conversion.
And transfer the transferred charge as an electric signal.
Adjust the phase in units of 1 or (1/2) cycle of the basic clock with the image sensor
The generated driving pulse and sampling pulse
Pulse delay circuit and a plurality of delay elements, one delay element having an average delay time
When the distance is d, the delay time is nd (n is an integer)
The pulse generator circuit can be set between
Delayed sampling pulse with delay time nd,
Variable delay circuit that outputs delayed sampling pulse
And an electric signal output from the image sensor,
Sampled by the sampling pulse output from the circuit
Output from the sampling hold circuit for holding and the variable delay circuit for the drive pulse.
Phase detection circuit that detects the phase relationship of the sampling pulse
Path and the phase relationship detected by the phase detection circuit
The uniform delay time d is calculated, and the n is calculated from the average delay time d.
Control the delay time of the variable delay circuit.
An image pickup apparatus, comprising: 2. The basic clock is supplied to the variable delay circuit.
And delay the basic clock with the variable delay circuit.
The delayed sampling pulse by
The imaging device according to claim 1, wherein the imaging device is generated. 3. The pulse generation circuit comprises a reset gate
Generates a pulse, and the variable delay circuit is supplied from the pulse generation circuit.
Delay the reset gate pulse with a delay time nd
Then, the delayed reset gate pulse is output, and the image sensor converts the transferred charges into a voltage.
Sometimes, the reset gate output from the variable delay circuit
Using the Toparusu, the phase detection circuit, the variable with respect to the drive pulse
The position of the reset gate pulse output from the delay circuit
The phase relationship is detected, and the control circuit detects the phase detected by the phase detection circuit.
When the average delay time d is calculated from the phase relationship,
The variable delay circuit is obtained by obtaining n from the interval d.
3. The delay time of is controlled.
The imaging device according to. 4. The basic clock is supplied to the variable delay circuit.
And delay the basic clock with the variable delay circuit.
To generate the reset gate pulse
The image pickup apparatus according to claim 3, wherein the image pickup apparatus is provided. 5. Obtained by photoelectric conversion by a driving pulse
Transferred electric charge and outputs the transferred electric charge as an electric signal.
Image sensor The electrical signal output from the image sensor is sampled by a sampling pulse.
Sampling hold times to sample and hold by
Road, Phase adjustment in units of 1 or (1/2) cycle of the basic clock
First pulse generation time capable of generating the generated drive pulse
Road, When a plurality of delay elements are provided and one delay element has an average delay time
If the interval is d, the delay time of the delay time nd (n is an integer)
The basic clock can be set to the delay time
A variable delay circuit that delays by nd and outputs a delayed clock.
Road, Based on the delay clock output from the variable delay circuit
A second pulse to generate the sampling pulse
Raw circuit, From the second pulse generation circuit for the drive pulse
Detects the phase relationship of the output sampling pulse
Phase detection circuit, From the phase relationship detected by the phase detection circuit,
The uniform delay time d is calculated, and the n is calculated from the average delay time d.
Therefore, a control circuit for controlling the delay time of the variable delay circuit
An image pickup apparatus comprising: 6. The image pickup device collects the transferred charges.
Use reset gate pulse when converting to voltage, The second pulse generation circuit outputs from the variable delay circuit.
Based on the delayed clock applied, the reset gate
Rauses, The phase detection circuit includes the second pulse for the drive pulse.
Of the reset gate output from the pulse generator circuit of
Detect the phase relationship of the lus, The control circuit detects the position detected by the phase detection circuit.
When the average delay time d is calculated from the phase relationship,
The value n is obtained from the interval d, and the delay of the variable delay circuit is calculated. Extra time
The imaging device according to claim 5, which is controlled. 7. Imaging according to any one of claims 1 to 6.
In the device, The variable delay circuit, A delay element formed by connecting a plurality of gates in series, Each of the plurality of series-connected gates forming the delay element
Switch the signal path to pass or bypass the signal
Changeover switch for each gate The gate is switched to the signal passing side according to the value n.
The amount of delay can be changed by determining the number of changeover switches.
And an image pickup device. 8. Imaging according to any one of claims 1 to 7.
The device detects the temperature inside the imaging device and uses it as temperature information.
Temperature sensor that outputs the
Temperature characteristics of the delay element in the variable delay circuit
As the phase information, temperature compensation is performed depending on
and a control circuit for modifying the value of n.
Image pickup device.