JPH07327172A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To allow the solid-state image pickup device to smoothly conduct automatic exposure control and automatic gain control. CONSTITUTION:A digital signal processing section 26 implementing various processing to digital data D1 corresponding to a video signal extracts luminance information and an integration circuit 28 integrates the information in the unit of a pattern to obtain an integration value I0. A comparator circuit 29 discriminates whether or not the integral value I0 is in a proper range and provides an output of comparison result C0. An exposure gain control circuit 30 controls the extension/contraction of a charge storage period of a solid-state image pickup element 21 depending on the comparison result C0 and controls the increase/decrease in the gain of a voltage controlled amplifier 24. In this case, either of exposure control and gain control is fixed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device which controls exposure of a solid-state image pickup device and gain control of a video signal.

[0002]

2. Description of the Related Art In a solid-state image pickup device using a CCD solid-state image pickup device, an exposure control function of the solid-state image pickup device is provided so as to cope with a change in luminance of a subject. This exposure control function is disclosed in JP-A-3-22768 and JP-A-3-48.
As disclosed in Japanese Patent No. 586 or the like, after the information charge accumulated in the light receiving pixel is temporarily discharged during the charge accumulation period of the solid-state image sensor, the newly accumulated information charge is read out to generate a video signal. Configured to get. Further, an automatic gain control circuit is provided for the video signal obtained from the solid-state image sensor, and the level of the video signal is averaged.

FIG. 7 is a block diagram showing the structure of a conventional solid-state image pickup device. The CCD solid-state imaging device 1 has a plurality of light receiving pixels arranged in rows and columns, and stores information charges generated in response to the light L emitted from the subject in each light receiving pixel. The CCD driving circuit 2 supplies a multi-phase transfer clock φ _n to the solid-state image sensor 1, temporarily discharges the charges accumulated in the light receiving pixels in the middle of the vertical scanning period, and then, from the discharging timing to the vertical scanning period. Information charges accumulated in the period until the end are transferred and output to obtain a video signal Y1. The sample hold circuit 3 samples and holds the video signal Y1 output from the solid-state image sensor 1 in synchronization with the driving timing of the solid-state image sensor 1, and outputs a video signal Y2. The integrating circuit 4 outputs the video signal Y1 output from the solid-state image sensor 1.
Is integrated in one screen unit, that is, in one vertical scanning period unit, and an integrated value I1 is generated for each vertical scanning period. The comparison circuit 5 is
The integrated value I1 is compared with a reference value corresponding to the proper range, and a comparison result C1 indicating whether or not the integrated value I1 is within the proper range is output. The exposure control circuit 6 generates a timing signal T that determines the charge discharge timing of the solid-state image sensor 1 based on the comparison result C1 and supplies the timing signal T to the drive circuit 2.
As a result, the timing of discharging the electric charge of the solid-state imaging device 1 is determined, and the charge accumulation period set between the discharging of the electric charge and the reading is expanded / contracted according to the illuminance of the light L. For example, when the light L is strong and the level of the video signal Y1 rises and the integrated value I1 exceeds the proper range, the comparison circuit 5
From this, an instruction is given to the exposure control circuit 6 to reduce the exposure, and the exposure control circuit 6 delays the discharge timing of the charges, whereby the charge accumulation period is shortened. On the contrary, when the light L is weak and the level of the video signal Y1 is lowered and the integrated value I1 becomes smaller than the appropriate range, the comparison circuit 5 gives an instruction to the exposure control circuit 6 to open the exposure, and the exposure control circuit 6 The charge accumulation period is extended by advancing the charge discharge timing. Therefore, the charge accumulation period of the solid-state image sensor 1 is expanded / contracted according to the illuminance of the light L, and the video signal Y1
Level is maintained within the proper range.

The voltage-controlled amplifier 7 has its gain variably set according to the applied control voltage V _C , amplifies the video signal Y2 according to a predetermined gain, and outputs a video signal Y3.
The analog signal processing unit 8 subjects the video signal Y3 to gamma correction, clamping of a reference level, etc., and outputs a video signal Y4 in accordance with a predetermined format. Integrating circuit 9
In the same manner as the integration circuit 4, integrates the video signal Y3 output from the amplifier 7 in units of one vertical scanning period to generate an integrated value I2 in each vertical scanning period. The comparison circuit 10 calculates the integrated value I
2 is compared with a reference value corresponding to the proper range, and a comparison result C2 indicating whether the integrated value I2 is within the proper range is output. Gain control circuit 11 increases or decreases the control voltage V _C receives the comparison result C2, variably set corresponding to the gain of the amplifier 7 to the level of the video signal Y2 by supplying the control voltage V _C to the amplifier 7 . For example, when the level of the video signal Y3 rises and the integrated value I2 exceeds the reference range, the comparison circuit 10 gives an instruction to the gain control circuit 11 to lower the gain, and the gain control circuit 11 outputs the control voltage V _C. By lowering the gain, the gain of the amplifier 7 is lowered. On the contrary, when the level of the video signal Y3 becomes low and the integrated value I2 becomes smaller than the proper range, the comparison circuit 10 gives an instruction to the gain control circuit 11 to increase the gain, and the gain control circuit 11 causes the control voltage V _{C to rise.} To increase the gain of the amplifier 7. Therefore, automatic gain control is realized so as to maintain the level of the video signal Y3 within the proper range.

[0005]

In a solid-state image pickup device having an automatic exposure control function and an automatic gain control function, two feedback loops are provided as shown in FIG. Exposure control and gain control are performed independently. However, since the response characteristics of the respective feedback loops are different, the finally extracted video signal is given by the quadratic transfer function. Therefore, when the brightness of the subject changes, the exposure of the solid-state image sensor and the gain of the video signal cannot be quickly responded to,
Smooth control is difficult.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a solid-state image pickup device which enables smooth control without losing the functions of exposure control and gain control.

[0007]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of light-receiving pixels arranged in a matrix have information charges corresponding to a subject image. From the first timing to the second timing after discharging the information charges accumulated in each light receiving pixel of the solid-state imaging element at the first timing and transferring and outputting the information charges at the second timing. Driving means for obtaining a video signal corresponding to the information charge accumulated in the charge accumulation period between the two, an amplifying means for giving an arbitrary gain to the video signal to control the average level of the screen unit, and the level-controlled Control means for determining the charge storage period based on the luminance information extracted from the video signal and for determining the gain of the amplifying means, wherein the control means determines the charge storage period. The gain of the amplifying means to a fixed value, after reaching is to a variable value the gain of said level control means to secure the charge accumulation period until reaching the period.

[0008]

According to the present invention, when the exposure of the solid-state image pickup device and the gain of the video signal are controlled based on the luminance information of the video signal, the gain is fixed by fixing the exposure when the exposure control reaches the limit state. On the contrary, when the gain control reaches the limit state, the gain is fixed and the exposure control is performed, so that the feedback loop can be one system. Therefore, even if the brightness of the subject changes significantly, it is possible to follow the subject without any trouble.

[0009]

1 is a block diagram showing the configuration of a solid-state image pickup device according to the present invention. The CCD solid-state image sensor 21 has a plurality of light-receiving pixels arranged in a matrix to receive light L from a subject and generates information charges. The CCD drive circuit 22 supplies a multi-phase transfer clock φ _n to the solid-state image sensor 21. Then, the video signal Y1 is output by pulse driving. The solid-state imaging device 21 and the drive circuit 22 have the same configuration as that of FIG. 7.

The sample and hold circuit 23 is configured to perform correlated double sampling which takes in the difference between the reference level of the video signal Y1 and the video information level in synchronism with the drive timing of the solid-state image pickup device 1, and only the video information. Output a video signal Y2. The voltage control type amplifier 24 gives the video signal Y2 a gain that is variably set according to the applied control voltage V _C , and outputs the video signal Y3 amplified to a predetermined level. The sample-hold circuit 23 and the amplifier 24 can both have MOS transistor configurations, and can be easily integrated on the same semiconductor substrate as the control circuit 30 described later. A / D converter 2
5 is the digital signal D1 for each pixel of the video signal Y3.
And is supplied to the digital signal processing unit 26. The digital signal processing unit 26 performs gamma correction on the data D1, clamps the reference level, adjusts the white balance in the case of color imaging, and suppresses the high-luminance pseudo signal.
2 is output. Then, the D / A converter 27 outputs the data D
2 is converted into an analog value and output as a video signal Y4.

The integrating circuit 28 includes a digital signal processing section 26.
The luminance information extracted from the screen is cumulatively added in a unit of one screen, that is, in a unit of one vertical scanning period, and the integrated value I0 is supplied to the comparison circuit 29 for each vertical scanning period. The comparison circuit 29 compares the integrated value I0 with a reference value corresponding to the appropriate range of the video signal level, and outputs a comparison result C0 indicating whether the integrated value I0 is within the appropriate range. Exposure gain control circuit 30
Generates a timing signal T for setting the charge accumulation period of the solid-state imaging device 21 based on the comparison result C0 and supplies the timing signal T to the drive circuit 22, and at the same time generates a control voltage V _C for controlling the gain of the amplifier 24. It is supplied to the amplifier 24. In this control circuit 30, the timing signal T or the control voltage V _C
Is configured to be changed in response to the comparison result C0, and the other is fixed during that period. For example, until the charge accumulation period of the solid-state image sensor 21 becomes the shortest, the charge accumulation period is expanded / contracted while the gain of the amplifier 24 is fixed at the maximum value, and after the shortest, the timing signal T is fixed and controlled. The voltage V _C is increased or decreased in response to the comparison result C0. As a result, the charge accumulation period of the solid-state image sensor 21 is expanded / contracted according to the illuminance of the light L, whereby automatic exposure control is realized, and the gain given to the video signal Y3 is increased / decreased according to the level of the video signal Y3. By doing so, automatic gain control is individually realized.

FIG. 2 is a block diagram showing the structure of the exposure gain control circuit 30, and FIG. 3 is a timing chart for explaining the operation thereof. Up-down counter 31 for exposure control
Performs a counting operation in accordance with the comparison result C0 of the comparison circuit 29, and stores information corresponding to the timing at which the drive circuit 22 discharges the information charge of the solid-state imaging device 21. When the count value overflows, the up / down counter 31 temporarily stops the counting operation and generates an overflow signal. Up / down counter 32 for gain control
Is activated upon receiving an overflow signal output from the up / down counter 31, counts according to the comparison result C0, and stores information corresponding to the control voltage V _C supplied to the amplifier 24. When the count value of the up / down counter 32 overflows, the counting operation is stopped and an overflow signal is generated. Then, this overflow signal is given to the up / down counter 31 to restart the up / down counter 31. The down counter 33 fetches the count output of the up / down counter 31 as preset data at the beginning of the vertical scanning period, counts the horizontal scanning signal HD, and raises the pulse of the timing signal T when the count value becomes “0”. . As a result, the period from the beginning of the vertical scanning period to the timing of discharging the information charges of the solid-state imaging device 21 is measured by the number of horizontal scanning periods. Then, by setting the timing of reading the information charges of the solid-state imaging device 21 at the end of the horizontal scanning period, the charge accumulation period set between the discharge timing of the information charges and the read timing is counted by the up / down counter 31. Expansion / contraction is controlled according to the output. The D / A converter 34 includes the up / down counter 3
The count output of 2 is converted into an analog value and the control voltage V _C
Output as. As a result, the gain of the amplifier 24 is controlled to increase or decrease according to the count output of the up / down counter 32.

Assuming that the exposure control is operating and the gain control is stopped, when the integrated value I0 exceeds the proper range, the comparison result C0 is first the up / down counter 31.
Is increased to increase the preset data of the down counter 33, delay the discharge timing of the information charges, and shorten the charge accumulation period. Then, the up-down counter 31 stops the counting operation and supplies an overflow signal to the up-down counter 32 when the count output reaches the maximum value with the shortest charge accumulation period (one horizontal scanning period). Further, if the integrated value I0 exceeds the proper range, the comparison result C0 causes the up / down counter 32 to count down, and the control voltage V _C is reduced to reduce the amplifier 2
Lower the gain of 4. On the contrary, assuming that the exposure control is stopped and the gain control is operating, when the integrated value becomes smaller than the appropriate range, the up / down counter 32 is counted up and the control voltage V _C is increased to increase the amplifier 24. Increase the gain. Then, the up / down counter 32
When the count output reaches the maximum value, stops the counting operation and supplies an overflow signal to the up / down counter 31. Further, if the integrated value I0 is smaller than the proper range, the comparison result C0 counts down the up / down counter 31 to reduce the preset data of the down counter 33, to accelerate the discharge timing of information charges and extend the charge accumulation period. As described above, only one of the two up / down counters 31 and 32 is operating and the other is stopped.

FIG. 4 is a circuit diagram of the sample and hold circuit 23 having a MOS transistor structure, and FIG. 5 is a timing chart for explaining its operation. Video signal Y which is an input signal
1 is connected to one end of the capacitor 42 via the buffer 41, and the other end of the capacitor 42 is connected to the buffer 43. Further, to the input side of the buffer 43, a constant voltage V _R is supplied via the switch 44 which operates in response to a first sampling pulse P1. The output of the buffer 43 is connected to the capacitor 46 whose other end is grounded via the switch 45 which operates in response to the second sampling pulse P2. Then, the fluctuation of the voltage of the capacitor 46 is taken out as the video signal Y2.

Video signal Y1 input to the buffer 41
As shown in FIG. 5, the reference level and the video information level are repeated at a constant clock cycle. This is a CCD
This is because the output section of the solid-state imaging device 21 repeatedly discharges and accumulates the information charges transferred and output, and the potential of the output section after the information charges are discharged becomes the reference level, and the amount of the accumulated information charges is increased. Indicates the video information level. Therefore, when the switch 44 is turned on in response to the first sampling pulse P1 whose timing coincides with the period of the reference level of the video signal Y1, the reference level of the video signal Y1 is fixed to the voltage V _R. For this reason,
Even if the reference level of the video signal Y1 fluctuates due to noise or the like, the buffer 43 captures the video signal Y1 having a stable reference level. Then, when the switch 45 is turned on in response to the second sampling pulse P2 whose timing coincides with the period of the image information level of the image signal Y1, the voltage corresponding to the difference between the reference level and the signal level is taken into the capacitor 46. . Therefore, the reference level on which is fixed to the voltage V _R, only the signal level portion of the video signal Y1 is output as a video signal Y2.

FIG. 6 is a circuit diagram of the voltage-controlled amplifier 24. The video signal Y2 passes through the buffer 51 and the resistor 52.
The drain of the N-channel MOS transistor 53 is connected to the resistor 52. A control voltage V _C for gain control is applied to the gate of the MOS transistor 53, and the source is grounded. Further, the voltage V _{D obtained} by resistance-dividing the power supply voltage is connected to the resistor 55 via the buffer 54, and the drain of the N-channel MOS transistor 56 is connected to the resistor 55.
A control voltage V _C common to the MOS transistor 53 is applied to the gate of the MOS transistor 56, and the source is similarly grounded. The drains of the two MOS transistors 53 and 56 thus arranged in parallel are connected to the inputs of the differential amplifier 60 having a MOS transistor configuration. A level shift circuit is provided between the drains of the MOS transistors 53 and 56 and the differential amplifier 60, if necessary. In the differential amplifier 60, the power sources are connected to the sources of two P-channel type MOS transistors 61 and 62 whose gates are connected to each other, the gates are connected to the drain side of the MOS transistor 61, and the sources are grounded. Two N-channel type MOS
Transistors 63 and 64 are MOS transistors 61 and 6
2 are connected in series to form a current mirror circuit.
Then, the gates of the MOS transistors 63 and 64 are used as two inputs, the potentials on the drain sides of the MOS transistors 53 and 56 are received, and the video signal Y3 is output from the drain side of the MOS transistor 62.

Here, when the control voltage V _C applied to the gates of the MOS transistors 53 and 56 becomes high, the MOS
The transistors 53 and 56 tend to turn on, the on-resistance decreases, and the potential on the drain side decreases. When the potentials on the drain side of the MOS transistors 53 and 56, which are inputs to the differential amplifier 60, decrease, the MO of the differential amplifier 60 is reduced.
The S transistors 63 and 64 tend to turn off, and the gain of the differential amplifier 60 decreases. Conversely, when the control voltage V _C decreases, the MOS transistors 53 and 56 tend to turn off, the on-resistance increases, the potential on the drain side increases, and the gain of the differential amplifier 60 increases.

As described above, the sample hold circuit 2 that handles the video signals Y1, Y2 and Y3 which are analog signals.
If the MOS transistor circuit 3 and the amplifier 24 are configured by MOS transistor circuits, they can be easily formed on the same semiconductor substrate as the control circuit 30 and the digital signal processing unit 26, which are usually digital circuits.

[0019]

According to the present invention, since the exposure of the solid-state image pickup device and the gain for the video signal can be controlled by a single feedback loop, it is easy to follow the change in the brightness of the subject and smooth control can be performed. It will be possible. Moreover, since the integrating circuit and the comparing circuit can be integrated into one, the circuit scale can be reduced and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a solid-state imaging device of the present invention.

FIG. 2 is a block diagram of an exposure gain control circuit.

FIG. 3 is a timing diagram showing the operation of the exposure gain control circuit.

FIG. 4 is a circuit diagram of a sample hold circuit.

FIG. 5 is a timing chart showing the operation of the sample hold circuit.

FIG. 6 is a circuit diagram of a voltage control type amplifier.

FIG. 7 is a block diagram showing a configuration of a conventional solid-state imaging device.

[Explanation of symbols]

 1, 21 CCD image sensor 2, 22 drive circuit 3, 23 sample hold circuit 4, 9, 28 integration circuit 5, 10, 29 comparison circuit 6 exposure control circuit 7, 24 voltage control type amplifier 8 analog signal processing unit 11 gain control Circuit 25 A / D converter 26 Digital signal processing unit 27 D / A converter 30 Exposure gain control circuit

Claims (2)

[Claims] 1. A solid-state image sensor for accumulating information charges corresponding to a subject image in a plurality of light-receiving pixels arranged in a matrix, and information charges accumulated in each light-receiving pixel of the solid-state image sensor are discharged at a first timing. After that, the driving means for transferring and outputting at the second timing to obtain a video signal corresponding to the information charge accumulated in the charge accumulation period from the first timing to the second timing, and an arbitrary video signal for the video signal. Amplifying means for giving a gain to control the average level of each screen unit, and control for determining the charge accumulating period on the basis of luminance information extracted from the level-controlled video signal and determining the gain of the level controlling means. The control means sets the gain of the amplifying means to a fixed value until the charge accumulation period reaches a predetermined period, and after the gain reaches the charge accumulation period. Is fixed and the gain of the amplification means is set to a variable value. 2. A solid-state imaging device for accumulating information charges corresponding to a subject image in a plurality of light-receiving pixels arranged in a matrix, and information charges accumulated in each light-receiving pixel of the solid-state imaging device are discharged at a first timing. After that, the driving means for transferring and outputting at the second timing to obtain a video signal corresponding to the information charge accumulated in the charge accumulation period from the first timing to the second timing, and an arbitrary video signal for the video signal. Amplifying means for giving a gain to control the average level of each screen unit, and the charge storage period is expanded or contracted in response to an increase or decrease of an integrated value of one screen unit of the video signal output from the amplifying means.
Control means for increasing or decreasing the gain given to the video signal by the amplifying means, wherein the control means starts reduction of the gain given by the level control circuit when the charge storage period becomes shortest, A solid-state imaging device, wherein extension of the charge storage period is started when the gain given by the level control circuit reaches a maximum.