JPH0153543B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive pulse generation circuit necessary for driving a scanning circuit of a solid-state imaging device for television.

In the past, so-called image pickup tubes such as vidicon and image orthicon were mainly used as imaging devices for television, but in recent years, with advances in semiconductor technology, electron beams are no longer used to read out video signals. enables readout by wire,
So-called solid-state imaging devices have been put into practical use, and their performance has been improved at a rapid pace.

An example of this solid-state imaging device is shown in FIGS. 1A and 1B.

FIG. 1A shows an example of the basic configuration of a two-dimensional array solid-state imaging device, and FIG. 1B shows an example of a timing chart of horizontal and vertical scanning pulses.

In the figure, 1 and 2 are horizontal and vertical scanning circuits, 3 is a plurality of photoelectric conversion elements arranged two-dimensionally, 4 is a video signal output terminal, 5 and 6 are switching elements, and 7 is a vertical readout line. , 8 is a horizontal readout line, 9 is a video bias voltage source, and 10 is a load resistor.

For example, two-phase clock pulses C _px and C _py are supplied to the scanning circuits 1 _{and 2} , and the respective outputs OX ₁ , OX _{2 .} . . OX _o and
OY ₁ , OY ₂ ...Input pulse V _sx and OY _o respectively
V _sy is a pulse train whose phase is shifted sequentially at the timing of clocks C _px and C _py , V _px1 , V _px2 ……V _pxo ,
V _py2 ...Outputs V _pyo . The relationship between these pulse trains is shown in FIG. 1B.

So, these pulse examples V _px1 ..., V _py1 ...
The switching elements 5 and 6 are sequentially opened and closed by
Each photoelectric conversion element 3 arranged two-dimensionally
The signal is read out from the readout line 7 to the readout line 8 and taken out to the output terminal 4. Since the signal from the photoelectric conversion element 3 corresponds to the optical image projected onto its surface, the video signal can be taken out to the output terminal 4 by the above operation.

By the way, in this type of solid-state imaging device, in order to obtain the necessary resolution, for example, about 500 x 500 photoelectric conversion elements 3, switching elements 5 and 6 paired with them, and a unit circuit for scanning are required. Therefore, most devices are based on MOS-LSI technology, which is relatively easy to integrate and can be configured by integrating photoelectric conversion elements and switching elements. An example of this is shown in Figure 2. show.

This figure 2 shows the configuration of the photoelectric conversion element 3 and switching elements 5 and 6 of an IC for a solid-state imaging device made by MOS-LSI technology, where 11 is -
Conductive type semiconductor substrates, 12, 13, and 14 are substrate 1
1 is a diffusion layer of a conductivity type opposite to that of 1, 15 is an insulating oxide film, and 16 and 17 are gate electrodes made of conductor films. Note that 8 is a conductive film for reading to the diffusion layer 14 and constitutes a horizontal readout line.

Then, the diffusion layer 12 forms a photodiode between it and the substrate 11 to become the photoelectric conversion element 3, and the gate electrode 16 uses the diffusion layer 12 as a source and the diffusion layer 13 as a source.
The switching element 5 is formed by forming a MOS transistor in which the gate electrode 17 has the diffusion layer 13 as the source and the diffusion layer 14 as the drain.

Although not shown, the scanning circuits 1 and 2 are also MOS
It is made using a shift register made of transistors.

Therefore, from scanning circuits 1 and 2, pulses V _pxo and V _pyo
appears on the output lines O _xo and O _yo , switching elements 6 and 5 become conductive at the same time, and a charging current flows from the video bias voltage source 9 to the photoelectric conversion element 3 at that position. The size corresponds to the amount of charge that was discharged in proportion to the amount of light that was incident on the photoelectric conversion element 3, so the load resistor 10 eventually A corresponding voltage will appear and be taken out from the output terminal 4 as a video signal.

Next, FIG. 3A shows horizontal and vertical scanning circuits 1 and 2.
In one example, 18 is an inverter, 19 is a MOS transistor, and 20 is an input pulse terminal. This circuit is a well-known shift register consisting of an inverter and a transfer gate, and two-phase clock pulses CP1 and CP2 as shown in FIG. 3B are applied to the terminal 2.
When the input pulse V _s is supplied to 0, the pulse train V _p1 ,
V _p2 ...V _po is obtained by sequential phase shifting in the clock cycle, so if C _px is the clock pulse and V _sx is the input pulse, the output is a pulse train V _px1 ...
It can be used as a horizontal scanning circuit 1 by generating , and by applying C _py to the clock pulse and V _sy to the input pulse, a pulse train V _py1 . . . is obtained as an output, so it can be operated as a vertical scanning circuit 2.

In addition, in Fig. 3A, the two-phase clock pulse CP
Although we have shown an example of a shift register using 1 and CP2, the clock pulses are not limited to 2 phases but can also be 3 phases,
Alternatively, it can be operated with a four-phase shift register, and such shift registers are well known, and it is possible to configure a scanning circuit using either of them.

Now, as is clear from the above description, in order to operate a solid-state imaging device, various pulses (clock pulses and input pulses) having a certain relationship in frequency and phase are required.

That is, as understood from FIGS. 1 to 3,
Clock pulses C _px , C _py and input pulses V _sx , V _sy are required, and among these, the clock pulse C _px is a high frequency signal of, for example, 6 to 7 MHz, depending on the number of photoelectric conversion elements 3 provided in the horizontal direction. The input pulse V _sx and the clock pulse C _py are at the horizontal frequency of the television signal, and the input pulse V _sy is at the vertical frequency of the television signal.

Therefore, in conventional color solid-state imaging devices that comply with the NTSC standard, for example, a high-frequency signal source is provided as a reference, and then the reference frequency signal of, for example, 14.318 MHz is processed by a frequency dividing circuit, a counter circuit, a decoder circuit, etc. , and was configured to obtain the various pulses mentioned above.

At this time, the clock pulse for the horizontal scanning circuit
As mentioned above, the C _px generation circuit generates this pulse C _px in the video signal band of the television signal (4 MHz or less).
Therefore, even if noise is mixed into the video signal from this circuit, the noise component can be easily removed by installing an appropriate low-pass filter in the video signal circuit. However, since the operating frequencies of other circuits that generate clock pulses and input pulses are located within the video signal band, if noise from these circuits mixes into the video signal, It becomes extremely difficult to eliminate this, and as a result, the above-mentioned conventional solid-state imaging device has the disadvantage that it is unable to provide a sufficient S/N ratio to the video signal.

An object of the present invention is to provide a drive pulse generation circuit for a solid-state imaging device that eliminates the drawbacks of the prior art described above and prevents the S/N of a video signal from deteriorating due to noise from the pulse generation circuit for driving a scanning circuit. It is on offer.

To achieve this object, the present invention is characterized in that the frequency divider circuit and counter circuit for obtaining drive pulses from the reference high frequency signal are configured to operate only during the blanking period of the television signal.

An embodiment of the drive pulse generation circuit according to the present invention will be described below with reference to FIGS. 4 and 5 of the drawings.

FIG. 4 is a block diagram showing an embodiment of the present invention, in which 21 is a reference frequency oscillator, 22 is a crystal oscillator, 23 is a synchronizing signal circuit, 24 is a signal processing circuit,
25 is a clock pulse generation circuit for the horizontal scanning circuit;
26 is a frequency dividing circuit, 27 is a phase/pulse width setting circuit, 28 is a horizontal frequency drive pulse generation circuit, 29
30 is a frequency dividing circuit, 30 is a counter circuit, 31 is a decoder circuit, 32 is a solid-state imaging device, 33 is an operation control circuit, 34 is a vertical frequency drive pulse generation circuit, 35
36 is a counter circuit, 37 is a decoder circuit, and 38 is an operation control circuit.

Note that the other details are the same as in the case of FIG.

Next, the operation will be explained.

The reference frequency oscillator 21 generates a reference high frequency signal a and supplies it to the synchronization signal circuit 23 and the horizontal frequency drive pulse generation circuit 25. At this time, as already explained, the frequency of the reference high frequency signal a is
For NTSC imaging devices, 14.318MHz is selected.

The synchronization signal circuit 23 generates various synchronization signals (horizontal and vertical synchronization signals, clamp pulses, horizontal and vertical synchronization signals, horizontal and vertical synchronization signals, clamp pulses, horizontal and
(vertical blanking pulse, etc.) is generated and supplied to the signal processing circuit 24 to synthesize a television signal. Such various synchronization signals b
Various types of LSI are known as the synchronization signal circuit 23 that generates .

Further, the reference high frequency signal a supplied to the horizontal scanning circuit clock pulse generation circuit 25 is frequency-divided by 1/2 by the frequency dividing circuit 26 to become a 7.16 MHz signal.
The phase/pulse width setting circuit 27 generates a clock pulse C _px having a predetermined phase relationship and a predetermined pulse width.
The signal is shaped into a horizontal scanning circuit 1 and supplied to the horizontal scanning circuit 1.

Up to this point, there is no particular difference from the conventional device, and the incorporation of noise can be adequately countered by using a filter or the like.

Next, the horizontal frequency drive pulse generation circuit 28 and the vertical frequency drive pulse generation circuit 34, which are the main points of the present invention, will be explained.

The frequency dividing circuit 29 of the horizontal frequency drive pulse generation circuit 28 further divides the output signal of the frequency dividing circuit 26,
An output signal c is obtained that provides the input pulse V _sx and the required phase and pulse width of the clock pulse C _py . For example, create a 3.58MHz signal by dividing 7.16MHz by 2. This output signal c is passed through a counter circuit 30 and a decoder circuit 31 to an input pulse V _sx of the horizontal scanning circuit 1 and a clock pulse of the vertical scanning circuit 2.
C _py is generated within the horizontal blanking period T (H.BLK) and input to the solid-state image sensor 32 .

In Fig. 5A, the horizontal frequency drive pulse generation circuit 28 is shown.
The input/output pulse chart is shown below. As explained above, from the output signal c of the frequency divider circuit 29, a two-phase clock pulse _Cpy and a reset pulse d are generated in the illustrated example via the counter circuit 30 and the decoder circuit 31. Such counter circuit 30 and decoder circuit 31 are well known. Further, in the decoder circuit 31, it is possible to logically AND the reset pulse d and the output signal c to obtain the horizontal scanning circuit input pulse V _sx as in the illustrated example, which can be easily realized using known digital circuit technology. In the illustrated example, the clock pulse _{C_py} has two phases, but a clock pulse with more phases can be easily realized. The pulse width and phase are also not limited to the illustrated example.

Next, the reset pulse d is input to the operation control circuit 33 shown in FIG. Also, from the synchronous circuit 23 to 1
A horizontal drive pulse HD of a horizontal frequency output at the beginning of the horizontal period is input to the operation control circuit 33.
Incidentally, a horizontal drive pulse HD as shown in FIG. 5A can be easily obtained from a commercially available synchronous circuit LSI. Note that although the horizontal drive pulse HD is used in the illustrated example, it is not limited to this as long as it is a similar signal. Horizontal drive pulse with known technology
Since a signal similar to HD can be easily generated, it may be used.

The operation control circuit 33 in FIG. 4 is a circuit that generates the operation control pulse e from the horizontal drive pulse HD and reset pulse d in FIG. 5A. The operation control circuit 33 can be easily realized by using a flip-flop circuit known in digital circuit technology. For example, a T-type flip-flop whose output polarity is reversed at the falling edge of the reset pulse d (the part where it changes from 1 level to 0 level in Figure 5 d) is used, and this flip-flop is connected to an external circuit. It is a so-called T-type flip-flop with a reset function that can be reset to the initial state by a control pulse, and the drive pulse HD shown in Fig. 5 is used as the external control pulse at this time.
All you have to do is use .

If the operation control circuit 33 configured in this way is used, the output pulse e is the drive pulse
A pulse is obtained that becomes 1 level when HD is 0 level, and becomes 0 level in synchronization with the falling edge of pulse d.

By the way, as mentioned above, the synchronization signal circuit 23
generates a horizontal drive pulse HD or a horizontal blanking pulse, but in known LSIs for synchronization signal circuits, the generation timing of the horizontal blanking pulse (represented by period T in FIG. 5A) is generally The generation phase of the horizontal drive pulse HD (0 level generation phase) is not as shown in FIG. 5A. In other words, in general-purpose LSIs like this, the start timing of the drive pulse HD is usually set to match the start timing of the horizontal blanking period, or very close to it. , their generation end timing is earlier than the end timing of the horizontal blanking period.

Therefore, when using such an LSI, the frequency divider circuit 29 and the counter circuit 30 operate when the operation control pulse e is at the 1 level, and are reset to the initial state when the pulse is at the 0 level. It can be configured with a frequency dividing circuit or a counter circuit. Note that frequency divider circuits and counter circuits capable of such operations are also known as digital circuits.

With this configuration, before the horizontal drive pulse HD generation start timing, the frequency divider circuit 29 and the counter circuit 30, which have been reset to the initial state, perform the frequency division operation at the generation start timing of this pulse HD. start, then output signal c
When a predetermined number of pulses are counted, pulses Cpy, pulses d, etc. can be obtained from the decoder 31.

The pulse generation period of the output signal c is the same as that of the crystal oscillator 2.
Since it is stabilized by the accuracy of the highly stable reference frequency oscillator 21 using the oscillator 21, it is technically difficult to keep the generation phase of the reset pulse d within the period T shown in FIG. 5A. For this reason, the pulse e that goes to 0 level in synchronization with the falling edge of the pulse d causes the pulse _Vsx , which is generated last among the drive pulses Cpy and _Vsx generated in one horizontal blanking period, to be generated. , immediately divider circuit 2
9 and the counter circuit 30 can be stopped.

In this embodiment, the output pulse HD of the synchronization circuit 23 is used to control the frequency division operation described above, but in the present invention, as shown in FIG. The only information necessary for operation control is the timing at which the pulse changes from to 0 level, and the width of the pulse (the period during which it is at 0 level) is irrelevant to operation control. Therefore,
According to the present invention, the driving pulse is generated with a free phase that does not depend on the pulse width of the pulse HD and only takes into consideration the operating characteristics of the solid-state image sensor 32.
Generates Cpy and _Vsx , thereby making it possible to always set optimal operating conditions.

The pulse _Vsx is input to the horizontal scanning circuit 1, and the clock pulse Cpx is also input to the horizontal scanning circuit 1. As mentioned above, this clock pulse Cpx is obtained by shaping the output pulse of the frequency dividing circuit 26. , and the pulse c in FIG.
Since the clock pulse Cpx and the pulse c are obtained by dividing the frequency of the output pulse by the frequency dividing circuit 29, the generation phases of the clock pulse Cpx and the pulse c have a constant relationship, although this is omitted in the timing chart of FIG. Therefore, for example, if the frequency divider circuit 29 is constituted by a frequency divider by 2 circuit, the clock pulse Cpx will be generated at a repetition period twice that of the pulse c.

On the other hand, as mentioned above, the pulse V _sx has a generation phase extracted from a predetermined half period of the pulse c, so this pulse V _sx is added to the signal Vs of FIG. 3B, and the clock pulses Cp1, Cp2 If the clock _pulses Cpx are replaced with
These can be generated in phases that are individually enclosed. In addition, in FIG. 3B, the pulse Vs is shown as having a phase that surrounds one pulse Cp2 and does not surround the pulse Cp1, but in the shift register shown in FIG. If two consecutive pulses of the conducting pulse Cp2 are not surrounded, even if the pulse Cp1 is surrounded, the signals V _p1 , V _p2 . . . will be generated as shown in FIG. 3B.

As described above, a signal having a predetermined phase relationship with the generation start phase of the horizontal drive pulse HD synchronized with the horizontal scanning period of the television signal is used as a reference.
V _sx is generated, and the scanning operation of the horizontal scanning circuit 1 of the solid-state image sensor 32 is started in synchronization with this signal V _sx , so that the horizontal scanning of the photoelectric conversion element 3 of the solid-state image sensor 32 is performed in synchronization with the signal V sx of the television signal. It is reliably executed in synchronization with the horizontal scanning period.

In the embodiment shown in FIG. 5, the signal V _sx is generated before the end of the horizontal blanking period T. In this case, the photoelectric conversion element 3 of the solid-state image sensor 32 By increasing the number of horizontal elements corresponding to this number, it is possible to prevent the lack of image signals during the horizontal video period (horizontal period excluding the horizontal blanking period). Here, the signal output from the output terminal 4 of the solid-state image sensor 32 during the horizontal blanking period is erased by the signal processing circuit 24 using a blanking pulse from the synchronization circuit 23.

As is clear from the above description, the frequency divider circuit 29 and counter circuit 30 of the horizontal frequency drive pulse generation circuit 28 operate during the horizontal blanking period T (H.
BLK) and stops during other periods.

Next, the vertical frequency drive pulse generation circuit 34 will be explained. The frequency dividing circuit 35 further divides the frequency of the output signal of the frequency dividing circuit 26 to obtain an output signal f that provides the phase and pulse width required for the input pulse V _sy . The input pulse V _sy of the vertical scanning circuit 2 is generated from this output signal f via the counter circuit 36 and the decoder circuit 37 within the vertical blanking period T (V.BLK), and is input to the solid-state image sensor 32 .

FIG. 5B shows the vertical frequency drive pulse generation circuit 34.
The input/output pulse chart is shown below. As described above, the vertical scanning circuit input pulse V _sy is generated from the output signal f of the frequency dividing circuit 35 via the counter circuit 36 and the decoder circuit 37. This input pulse V _sy is input to the operation control circuit 38 . Also, the synchronous circuit 23
A vertical drive pulse VD of a vertical frequency output at the beginning of one vertical period is input to the operation control circuit 38. The vertical drive pulse VD can be obtained from a commercially available synchronous circuit LSI like the horizontal drive pulse HD explained earlier, but the vertical drive pulse
As in the case of the horizontal drive pulse HD, other pulses similar to VD may be used.

In this way, as in the case of the horizontal frequency drive pulse generation circuit 28 described above, the operation control circuit 38 consisting of a T-type flip-flop with a reset function generates
A pulse g which becomes 1 level when the signal VD is 0 level and becomes 0 level in synchronization with the falling edge of pulse V _sy is output.

As in the case of the pulse generation circuit 28, the frequency dividing circuit 35 and the counter circuit 36 are also constructed of circuits capable of frequency dividing operation using this pulse g, and as a result, the pulse HD and pulse d shown in FIG. 5A can be operated. Operates as control timing. Similar to the operation control circuit 33, frequency divider circuit 29, counter circuit 30, and decoder 31 in the pulse generation circuit 28, this pulse generation circuit 34 also generates the pulse VD of FIG. 5B.
The operation control circuit 38, the frequency dividing circuit 35, the counter circuit 36, and the decoder 37 function using the pulse V _sy as the operation control timing.

As a result, a pulse V _sy having a predetermined phase relationship with the vertical drive pulse VD generated at the start of the vertical blanking period in synchronization with the vertical scanning period of the television signal is set as a reference. It can occur during the vertical blanking period.

At this time, the frequency division number of the frequency dividing circuit 35 is set so that the repetition period of the pulse f is the same as the horizontal scanning period of the television signal, and the counter circuit 36 and the decoder 37 are used to generate a predetermined number of pulses f. The configuration is such that a pulse V _sy synchronized with one cycle period of is generated.

As already explained with reference to FIG. 5A, since one vertical circuit clock pulse _Cpy is generated for each repetition period of the horizontal scanning period of the television signal, the circuit is configured as shown in FIG. 3A. C _py 2 is input as pulse Cp2 to the vertical scanning circuit 2
The pulse V _sy can be generated so as to surround one of the .

Therefore, when the pulses Cp1 and Cp2 shown in FIG. 3B are replaced with the pulse _Cpy of FIG. 5A, and the pulse Vs is replaced with the pulse _Vsy of FIG. 5B, it is clear that the vertical scanning circuit 2 output pulses V _py1 , V _py2
...is the pulse C _py surrounded by the above-mentioned pulse V _sy
After the generation timing of pulse C py 2, the pulse C py is sequentially output every time the pulse C _py 2 is repeated.

As described above, in this embodiment, a pulse V _sy having a predetermined phase relationship with the vertical drive pulse VD synchronized with the vertical scanning period of the television signal is generated based on the generation start phase of the vertical drive pulse VD, and this pulse V _sy
Since the vertical scanning operation of the solid-state image sensor 32 is started in synchronization with the vertical scanning period of the television signal, the vertical scanning of the solid-state image sensor 32 with respect to the photoelectric conversion element 3 is synchronized with the vertical scanning period of the television signal.
It can be done reliably.

In the example shown in FIG. 5B, the pulse V _sy
is generated before the end of the vertical blanking period T. In addition, correspondingly, the horizontal rows of the photoelectric conversion elements 3 are set to the number of effective scanning lines (the vertical number excluding the vertical blanking period T). It is also possible to provide some extra columns (number of scanning lines in a period), and thereby it is possible to prevent image signal loss in the vertical direction. Furthermore, the output signal of the solid-state image sensor during the vertical blanking period is removed by the signal processing circuit 24 using a blanking pulse.

As is clear from the above explanation, the frequency dividing circuit 35
The counter circuit 36 operates only during the vertical blanking period T (V.BLK) and stops during other periods.

Therefore, according to the embodiment of FIG. 4, both the horizontal frequency drive pulse generation circuit 28 and the vertical frequency drive pulse generation circuit 34, which operate at a frequency within the band of the television signal, operate only during the blanking period. Therefore, even if noise enters the television signal system from these circuits, it will simply be blanked out and will not have any effect on the S/N of the television signal.

As explained above, according to the present invention, it is possible to generate various pulses necessary for the operation of a solid-state imaging device without affecting the S/N of a television signal, thereby overcoming the drawbacks of the prior art. Except for all of the above, it is possible to provide a pulse generation circuit for a solid-state imaging device that can obtain a television signal with a sufficient S/N ratio.

[Brief explanation of drawings]

Figures 1A and B are a conceptual diagram and drive pulse waveform diagram showing the basic configuration of a solid-state imaging device, Figure 2 is a sectional view showing the configuration of its photoelectric conversion element and switching element, and Figure 3A and B. 4 is a block diagram showing an example of a scanning circuit and a waveform diagram for explaining its operation. FIG. 4 is a block diagram showing an embodiment of the pulse generating circuit according to the present invention. FIGS. 5A and 5B are waveform diagrams for explaining its operation. It is. 1...Horizontal scanning circuit, 2...Vertical scanning circuit, 2
DESCRIPTION OF SYMBOLS 1... Reference frequency oscillator, 25... Clock pulse generation circuit for horizontal scanning circuit, 28... Horizontal frequency drive pulse generation circuit, 29... Frequency dividing circuit, 30...
...Counter circuit, 31...Decoder circuit, 32...
...Solid-state image sensor, 33...Operation control circuit, 34...
... Vertical frequency drive pulse generation circuit, 35 ... Frequency dividing circuit, 36 ... Counter circuit, 37 ... Decoder circuit, 38 ... Operation control circuit.

Claims (1)

[Claims] 1. Frequency dividing means that receives a reference high frequency signal pulse as input and generates an output signal pulse with a repetition frequency within the video signal band, and operation limiting means that limits the frequency dividing operation of the frequency dividing means to within the blanking period of the television signal. In the pulse generating circuit, the pulse generating circuit is configured to generate a scanning circuit drive pulse for a solid-state image sensor from the output pulse of the frequency dividing means, in which the frequency dividing means an operation start means for starting a frequency dividing operation of the frequency dividing means; and a reset means for counting the output signal pulses and generating a reset pulse synchronized with the generation timing of a predetermined number of output signal pulses after the frequency dividing operation of the frequency dividing means has started. pulse generating means;
A pulse generating circuit characterized in that an operation stop control means is provided for stopping the frequency dividing operation of the frequency dividing means in synchronization with the reset pulse, and the operation limiting means is constituted by these three types of means.