JPS63263878A - Clock signal generating circuit for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution and to decrease the radiation of a noise by arranging a synchronizing circuit substrate at the position away from a CCD driving substrate and replacing a conventional 1/100 frequency-divider on the synchronizing circuit substrate to two 1/50 frequency-dividers. CONSTITUTION:An 1/2 frequency-divider 2 on a CCD driving substrate 12 two-frequency-dividers a master clock MCK, and generates complementary pulses CK1 and the inverse of CK1 in which the frequency is 37.125 MHz and the duty is 50%. The above-mentioned complementary pulse is outputted from the substrate 12 to an external part, inputted to an 1/11 frequency- divider 4 on a synchronizing circuit substrate 13, and a frequency-divider 4 generates complementary pulses CK2 and the inverse of CK2 in which the frequency is 3.375 MHz and the duty is 50%. For the CK2 and the inverse of the CK2, a pulse CK3 of the double frequency of a horizontal scanning frequency fH is generated by 1/50 horizontal frequency-dividers 5 and 6. Here, the horizontal frequency-dividers 5 and 6 are synchronized. An 1/2 frequency- divider 7 two-frequency-divides the CK3 and generates a pulse CK4 of a horizontal scanning frequency fH. By such a constitution, since it is not necessary to clear the frequency-divider 2 at every constant period, the circuit constitution is facilitated. Since the pulse transmitted from the frequency-divider 2 to the frequency-divider 4 is the complementary pulse of a frequency lower than the MCK, even when a transmission line is lengthened, the attenuation of a pulse is minimized and the radiation of the noise to a circumference is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a clock signal generation circuit for a solid-state imaging device.
The present invention particularly relates to a clock signal generation circuit suitable for high-speed operation.

(Prior Art) In recent years, solid-state imaging devices using charge-coupled devices (hereinafter referred to as COD) and the like have tended to have more pixels due to advances in integrated circuit technology. Along with this, the clock signal generation circuit of the solid-state imaging device must also be made faster. FIG. 5 is a block diagram showing an example of a solid-state imaging device with a large number of pixels. A two-dimensional CCp solid-state imaging device is shown that is compatible with a high-definition television system (hi-vision) with a field frequency of 60 Hz, an aspect ratio of 16:9, and a 2:1 interlace. In the figure, 101 is an imaging unit that photoelectrically converts incident light from a subject. In this imaging unit 101, a light receiving element such as a photodiode (not shown here) is arranged horizontally at 192.
0 pixel and 1035 pixels are arranged in the vertical direction. The horizontal COD registers 102 and 103 alternately receive and remove signal charges from a vertical COD register (not shown here) in the imaging section 101 and transfer them in the horizontal direction. Note that the structure using two horizontal COD registers 102 and 103 is generally called a dual channel readout structure, and the horizontal COD
This is useful for relaxing the horizontal electrode pitch of the register and reducing the clock frequency per horizontal COD register.

In other words, the clock frequency when only one horizontal COD register is used is 74, which is the product of the number of scanning lines, 1125, the frame frequency, 30 Hz, and the number of horizontal samples, 2200.
The clock frequency is as fast as 25 MHz, but with a dual channel readout structure the clock frequency is 37.125 MHz.
will be halved to Next, reference numerals 104 and 105 are charge detection units, which convert the signal charges transferred to the horizontal COD registers 102 and 103, respectively, into voltage signals. The two signals output from charge detection units 104 and 105 are combined as a time-series signal by an external signal processing circuit (not shown).

FIG. 6 shows a conventional clock signal generation circuit corresponding to the two-dimensional CCD solid-state imaging device shown in FIG.
106 is a master clock generation source such as a crystal oscillator or voltage controlled crystal oscillator, 107 is a 1/2 frequency divider, and 108 is a CC
D clock decoder, 109 is a 1/11 frequency divider, 110
is a 1/100 horizontal frequency divider, 111 is a 172 frequency divider, 11
2 is a horizontal synchronous decoder, 113 is a 1/1125 vertical frequency divider, 114 is a vertical synchronous decoder, and 115 is a composite decoder. In a clock signal generator with such a configuration, 1
Beat disturbance may occur between the 72 frequency divider 107 and the 1711 frequency divider 109. The most effective means to minimize this beat disturbance is the 172 frequency divider 107 and 171
1 frequency divider 109. In FIG. 6, the master clock generation source 106 and the frequency divider 10
7 and the COD clock decoder 108 are arranged on the CCD drive board 116, and other components are arranged on the synchronous circuit board 117 located apart from the CCD drive board 116, thereby preventing beat disturbance.

FIG. 7 is a time chart of the clock signal generation circuit of FIG. 6. The operation will be explained below using this time chart. First, in the master clock generation source 106, 74.2
It oscillates a 5MHz master frequency MCK.

This master clock MCK is applied to a 172 frequency divider 107, which generates a 172 frequency divided pulse CK11 of 37.125 MHz. COD clock decoder 108
Here, the COD horizontal transfer pulse -8, reset pulse 4 large, clamp pulse -3, sampling pulse φS, etc. are generated based on the 172 frequency divided pulse CKII. On the other hand, the master clock signal MCK is outputted from the CCD drive board 116 to the outside, and is input to the 1/11 frequency divider 109 arranged on the synchronous circuit board 117, where the 6.75M1
A pulse CK12 of 1z divided by 1711 is generated. The reason for generating the 1711 frequency divided pulse CK12 here is that the 0 and 15p pulses required by the horizontal synchronization decoder 112 in the next stage are
This is to obtain the minimum timing for every (= 1/6.75MHz). The 1/11 frequency divided pulse CK12 is applied to the 1/100 horizontal frequency divider 110, and the horizontal scanning frequency fMcy) is doubled to 67, 5kHz (2fw
) is generated. 17 more
The frequency divider 111 divides the pulse CK13 by two to generate a pulse CK14 having a horizontal scanning frequency f□. The horizontal synchronization decoder 112 generates a horizontal synchronization signal H8Y, a horizontal drive pulse HD, etc. based on the pulses from the 1/100 horizontal frequency divider 110 and the 1/2 frequency divider 111. On the other hand, the pulse CK13 can also be applied to the 1/1125 vertical frequency divider 113, where the field frequency is 60Hz.
Each field timing pulse is generated. The vertical synchronization decoder 114 generates a vertical drive pulse VD, a field index pulse FI, etc. based on this field timing pulse. Further, the composite decoder 115 synthesizes the pulses from the horizontal synchronization decoder 112 and the vertical synchronization decoder 114 to generate a composite synchronization signal C.
It generates 8Y, CCD vertical transfer pulse 4V, etc.

By the way, the rising (falling) timing of the 172 frequency divided pulse CKII and the rising (falling) timing of the 1/11 frequency divided pulse CK12 shown in Fig. 947 only match every 22 clock cycles of the master clock MCK. Therefore, the 172 frequency divided pulse CKI
In order to synchronize I and various pulses generated after the 1/11 frequency divider 109, horizontal synchronization decoder 112 to 1
The 1/2 frequency divider 107 must be cleared using the clear pulse CP that is output once per horizontal scanning period. This will be explained in more detail using the circuit shown in FIG. In the same case, 99 is a 174 frequency divider consisting of D type flip-flops 117 and 118,
Its function is equivalent to the horizontal frequency divider 110 except for the difference in frequency division ratio. Further, 119 is an AND gate whose function is equivalent to that of the horizontal synchronization decoder 112. In the same figure, the clock terminals of flip-flops 117 and 118 have 1
A 711 frequency division pulse CK12 is applied. Therefore, from the flip-flop 117, from time t1 to t in FIG.
A frequency-divided pulse CK15 which is at a high level during the period , is output. Further, from the inverting output terminal of the flip-flop 118, a frequency division pulse CK16 is outputted corresponding to the frequency division pulse CK15, which is at a low level for a period from time t to t. Therefore, the AND gate 119 outputs time t□ to t.

A pulse CK17 that becomes high level during the period is output. On the other hand, the signal from the flip-flop 117 is the time t.

Frequency division pulse CK15 whose level is high in the t4th period from
゛ may also be output. At this time, the frequency-divided pulse CK15' is output from the inverting output terminal of the flip-flop 118.
Correspondingly, a frequency-divided pulse CK16' that becomes low level during a period from time t to t6 is output. Therefore, the AND gate 119 outputs a pulse CK17' which is at a high level only during periods of time and t. Here pulse C
K17 and pulse CK17° are 1/2 frequency divided pulse CK1
Note that the phase relationships with respect to 1 are not the same.

In other words, the rising edge of pulse CK17 coincides with the rising edge of pulse CKII divided by 172 (time t,), but the rising edge of pulse CK17' is out of phase by 180° and does not coincide with the rising edge of CKII (time t,).
, this, and the COD clock decoder 108 in FIG.
output pulses from and other dehooders 112, 114,
The timing of the output pulse from 115 is set to 1 of master clock MCK by the initial state of 172 frequency divider 107.
This suggests that there is a possibility of clock deviation (13.5 nS), which poses a problem for stable operation of the circuit. Therefore, in the clock signal generation circuit shown in FIG.
By clearing the 2 frequency divider 107 every horizontal scanning period using the clear pulse CP, the above-mentioned timing deviation is prevented.

(Problem to be Solved by the Invention) However, in the conventional clock signal generation circuit described above, the 172 frequency divider 107 is cleared every horizontal scanning period, so the video signal processing circuit cannot be placed nearby. Noise easily enters the area. Furthermore, adjusting the phase relationship of the clear pulse CP is also troublesome. Furthermore, the master clock MCK with the highest frequency in the system is the CCDFX moving board 1.
16 to the synchronous circuit board 117, the pulses are easily attenuated and noise is easily radiated to the surroundings.

The present invention eliminates the above-mentioned conventional drawbacks, and its purpose is to provide a clock signal generation circuit for a solid-state imaging device that has an easy circuit configuration and emits less noise.

(Means for Solving the Problems) According to the present invention, a clock from a master clock generation source is frequency-divided to generate drive pulses of a solid-state imaging device, part of a group of output signal processing pulses, and a group of output signal processing pulses. a first frequency divider that generates a necessary timing pulse and two complementary pulses with a duty of 50% synchronized with the timing pulse;
a first clock decoder that generates a part of the drive pulse group of the solid-state imaging device and an output signal processing pulse group based on the timing pulse output from the 0 frequency divider; and an output from the first frequency divider. a second frequency divider that divides the two complementary pulses to be outputted by an odd number to generate two complementary pulses with a duty of 50%; third and fourth frequency dividers that divide the frequencies at the same ratio and are synchronized with each other; and driving the solid-state imaging device based on the pulses output from the third and fourth frequency dividers. A clock signal generation circuit for a solid-state imaging device is obtained, which includes a second clock defuter that generates the remainder of a pulse group and a phase signal group.

(Function) Since it is not necessary to clear the first frequency divider at regular intervals, the circuit configuration becomes easy. Also, from the first frequency divider to the second
Since the pulses transmitted to the frequency divider are complementary pulses with a lower frequency than the master clocker, even if the transmission path is lengthened, the attenuation of the pulses is small and the radiation of noise to the surroundings is also small.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a clock signal generation circuit according to the present invention, which is compatible with the two-dimensional CCD solid-state imaging device shown in FIG. This clock signal generation circuit is a master clock generator R1,1.
72 frequency divider 2, CCD clock decoder 3.1/11 frequency divider 4.1150 horizontal divider 5, 6.172 frequency divider 7,
The horizontal synchronization decoder 8.1/1125 is composed of a vertical frequency divider 9, a vertical synchronization decoder 10, and a composite decoder 11. In addition, in the same figure, in order to prevent beat interference between the 172 frequency divider 2 and the 1711 frequency divider 4, the master clock generation [1 and 172 frequency divider 2' and CCD
A clock decoder 3 is placed on a CCD drive board 12, and other components are placed on a synchronous circuit board 13 located apart from the CCD drive board 12. FIG. 2 is a time chart of the clock signal generation circuit according to the present invention. The operation will be explained below using this time chart. First, master clock generation source 1 has 74 clocks as before.
．． It oscillates a 25MHz master clock MCK. The 172 frequency divider 2 divides the frequency of this master clock MCK by 2, and the frequency is 37.125 MHz and the duty is 50.
% complementary pulses CKI and CKI are generated. The CCD clock decoder 3 uses the complementary pulses CKI and CKI as a reference, and the horizontal transfer pulse of the CCD is −8, and the reset pulse is ≠8.
．． Clamp pulse φ. , sampling pulse φ3, etc. are generated. On the other hand, complementary pulses CKI and CKI are CCD
The signal is output from the drive board 12 to the outside and input to the 1711 frequency divider 4 arranged on the synchronous circuit board 13. 1/1
1 frequency divider 4 divides the complementary pulses CKI and CKI by 1 each.
By dividing the frequency by 1, complementary pulses CK2 and σX1 with a frequency of 3.375M)Iz and a duty of 50% are generated.

Here, a specific circuit example of the 1/11 frequency divider 4 is shown in Figure 3 (a
), this 1/11 frequency divider 4 is composed of synchronous hexadecimal counters 14 and 15, inverters 16 and 17, and a flip-flop 18. The operation will be explained using the time chart shown in FIG. 3(b). First, at time 1, the ripple carry CR of the counter 14 becomes high level, so the flip-flop 18 is preset and its output CK2 becomes high level. At the same time, the counter 15 starts counting at time 1. Time 1.5.5 clocks have passed since 1. So counter 15 ripple carry C
Since R becomes high level, the flip-flop 18 is cleared and its output CK2 becomes low level. At time t, when 5.5 clocks have elapsed from 0 and time t, when the counter 14 starts counting at the same time, the counter 14 starts counting.
・Ripple carry CR becomes high level again.

Thereafter, by repeating the same operation, the flip-flop 18 outputs complementary pulses CKI and complementary pulses CK2 and CK2, which are obtained by dividing CKI by 11 and have a duty of 50%.

These complementary pulses CK2 and CK2 are passed through the 1150 horizontal frequency divider 5
, 6, and a pulse CK3 having a frequency of 67, 5 kHz (2L+'), which is twice the horizontal scanning frequency fu, is generated. Here 1750 horizontal splitter 5.6
are out of sync. The 172 frequency divider 7 divides the frequency of the pulse CK3 by two to generate a pulse CK4 having a horizontal scanning frequency f)l. The horizontal synchronization decoder 8 generates a horizontal synchronization signal H3Y, a horizontal dry pulse HD, etc. based on the pulses from the 1150 horizontal frequency dividers 5 and 6 and the 172 frequency divider 7. On the other hand, pulse CK3 is applied to 1/1125 vertical frequency divider 9.
At this point, field timing pulses with a field frequency of 60 Hz are generated. The vertical synchronization decoder 10 generates a vertical drive pulse VD, a field index pulse FI, etc. based on this field timing pulse. Further, the composite decoder 11 synthesizes the pulses from the horizontal synchronization decoder 8 and the vertical synchronization decoder 10 to generate a composite synchronization signal C8Y, a vertical transfer pulse 4v of the CCD, and the like.

Next, the operations of the 1150 frequency dividers 5 and 6 and the horizontal synchronous decoder 8 will be explained in detail using the circuit shown in FIG. 4, which shows these in a simplified manner. The function of the D type flip-flop 19.20 in the same figure is 115, excluding the difference in frequency division ratio.
This is equivalent to 0 frequency dividers 5 and 6. Further, 21 is an AND gate whose function is equivalent to that of the horizontal synchronization decoder 8. In the figure, a pulse CK2 is applied to the clock terminal of the flip-flop 19. Therefore, the flip-flop 19 outputs a frequency-divided pulse CK5 which is at a high level during the period from time t1 to time t in FIG. Furthermore, the inverted pulse of CK5 is fully applied to the data input terminal of the flip-flop 20 for synchronization with the flip-flop 19, and furthermore, the pulse CK2 is fully applied to the clock terminal thereof. Therefore, from the flip-flop 20, the time t! The pulse CK6 is at a low level during the period from t4 to
is output. Therefore, from the AND gate 21, time 1.
From t! A pulse CK7 which is at a high level during the period is output. Here, the pulse CK7 is the same as the pulse CK17 of the conventional example shown in FIG. 7, and its rising timing coincides with the rising timing of the pulse CK1 (time t
-1) There is a problem. According to the above-described operation, there is a possibility that the AND gate 21 outputs the pulse CK7' which is at a high level during the period from time t to t4. However, even in this case, the rising timing of CK7' and the rising timing of pulse CKI match (time t,
), so the overall phase relationship will not shift.
Therefore, it is not necessary to clear the 1-by-2 frequency divider 2 at regular intervals as in the conventional case, and the circuit configuration becomes easy.

In addition, in the clock signal generation circuit shown in FIG. 1, only complementary pulses CKI and CKI having a frequency of 37.125 MHz, which is half of the master clock MCK, can be transmitted between the CCD drive board 12 and the synchronization circuit board 130. Even if the path is lengthened, the attenuation of the complementary pulses CKl and CKI is small, and the rate at which these pulses are radiated to the surroundings as noise is also reduced.

(Effects of the Invention) As described above, according to the present invention, it is possible to obtain a clock signal generation circuit for a solid-state imaging device that has an easy circuit configuration and emits less noise. In the embodiments of the present invention, the clock signal generation circuit of a two-dimensional CCD solid-state image pickup device compatible with the high-definition television system was explained as an example, but the application of the present invention is not limited to this. Imaging device, MO
It is widely applicable to clock signal generation circuits such as 8-inch solid-state imaging devices and -dimensional solid-state imaging devices. Furthermore, although the detailed description of the present invention has been made on the assumption that the clock signal generation circuit is composed of discrete components, the present invention can also be applied to a case where these components are integrated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a clock signal generation circuit of a solid-state imaging device which is an embodiment of the present invention, FIG. 2 is a time chart explaining its operation, and FIGS. A specific circuit example of the 1711 frequency divider 4 shown in the figure and a time chart explaining its operation, FIG. A simplified circuit diagram; FIG. 5 is a plan view illustrating a two-dimensional COD solid-state imaging device; 6150 is a configuration diagram illustrating a conventional clock signal generation circuit; FIG. 7 is a time chart illustrating its operation; Figure 8 shows the sixth figure for ease of explanation.
1/100 frequency divider 110 and horizontal synchronous decoder 112 in the figure
FIG. 2 is a simplified circuit diagram. In the figure, 1,106 is the master black ivy generation source, 2
, 107 is a 172 frequency divider, 3, 108 is a COD clock decoder, 4, 109 is a 1711 frequency divider, 5, 6
is a 1150 horizontal frequency divider, 110 is a 1/100 horizontal frequency divider, 7°111 is a 1/2 frequency divider, 8 and 112 are horizontal synchronous decoders, 9 and 113 are 1/1125 vertical frequency dividers, 1
0, 114 are vertical synchronization decoders, 11, 115 are composite decoders, 12, 116 are CCD drive boards, 13, 1
17 is a synchronous circuit board.

Claims (1)

[Claims] A timing pulse necessary to divide the clock from the master clock generation source to generate a part of the drive pulse group of the solid-state imaging device and an output signal processing pulse group, and a 50% duty pulse synchronized with the timing pulse. a first frequency divider that generates complementary pulses; and a part of a drive pulse group of the solid-state imaging device and an output signal processing pulse group are generated based on the timing pulse output from the first frequency divider. a first clock decoder that divides the two complementary pulses output from the first frequency divider by an odd number to generate two complementary pulses with a duty of 50%; third and fourth frequency dividers that divide each of the two complementary pulses output from the second frequency divider at the same ratio and are synchronized with each other; A clock signal generation circuit for a solid-state imaging device, comprising a second clock decoder that generates the remainder of a group of driving pulses for the solid-state imaging device and a group of synchronization signals based on pulses output from the device.