JPS6252510B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a television camera using a solid-state image sensor, and more particularly to a drive circuit for a television camera using a solid-state image sensor.

[Background of the invention]

A MOS solid-state image sensor is designed to read out signals from photodiodes arranged in a matrix in a light receiving section as time-series signals by switching vertical and horizontal readout switches in an orderly manner. The vertical and horizontal readout switches are opened and closed by the output pulses of the vertical and horizontal shift registers built into the solid-state image sensor, but in order to operate the vertical and horizontal shift registers, two-phase vertical clock pulses, vertical input pulses, two Phase horizontal clock pulses, horizontal input pulses, etc. are required. Furthermore, in order to convert the output signal of the solid-state image sensor into a television signal, blanking signals, horizontal and vertical synchronization signals, etc. are also required.

Conventionally, these pulses are composed of an oscillator 1, a horizontal clock generating section 2, a horizontal counter section 3, a horizontal logic section 4, a vertical counter section 5, a vertical logic section 6, and a complex logic section 7, as shown in FIG. Drive circuit 8
It was made of.

That is, the horizontal clock generator 2 sequentially generates pulses for driving the horizontal shift register 9 and the horizontal counter 3 from the output signal of the oscillator 1 having a high oscillation frequency. The output pulses of the horizontal counter section 3 are combined in a horizontal logic section 4 to form a vertical clock pulse 4.
a, a horizontal input pulse 4b, a horizontal blanking pulse 4c, and a horizontal synchronizing pulse 4d. These pulses are applied to the vertical shift register 10, the horizontal shift register 9, and the composite logic section 7, respectively, and are also supplied to the vertical counter section 5. The output pulses of the vertical counter section 5 are combined in a vertical logic section 6 to become a vertical input pulse, a vertical blanking pulse 6a, and a vertical synchronization pulse 6b, which are supplied to a vertical shift register 10 and a composite logic section 7.
The composite logic section generates composite blanking signals and composite synchronization signals from horizontal and vertical blanking signals and synchronization signals.

The conventional drive circuit 8 shown in FIG. 1 not only has a drawback of having a complicated circuit configuration, but also becomes a source of periodic noise, which is a major drawback of solid-state cameras. In other words, since the counter section of the drive circuit 8 is composed of a binary counter, noise generated especially in the frequency dividing circuit of the horizontal counter can enter the signal line through the power supply line, ground line, electrostatic coupling, etc. and cause vertical stripes on the screen. It was producing a similar noise.

[Purpose of the invention]

The present invention provides a method of configuring a drive circuit without providing a counter section required in conventional circuits, and aims to completely eliminate periodic noise mixed in video signals.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail based on Examples. FIG. 2 shows one embodiment of the drive circuit of the present invention. This circuit differs from conventional drive circuits that use a frequency divider circuit to create a low frequency from a high frequency.This circuit uses the lowest frequency handled by the drive circuit (vertical synchronization frequency).
The main feature is that it is equipped with a horizontal synchronous oscillator that oscillates in synchronization with that frequency, and a horizontal clock pulse oscillator that oscillates in synchronization with the horizontal synchronous signal, and that it gradually generates high frequencies from low frequencies. . FIG. 3, FIG. 4, and FIG. 5 show waveforms at each part of the above circuit.

The pulse width of the output 12 of the vertical synchronization frequency oscillator 11 is changed by a pulse width control circuit 13 to generate a vertical synchronization pulse 14 and a vertical blanking pulse 33. Vertical blanking pulse 33 is also applied to horizontal sync frequency oscillator 15 to produce horizontal sync pulse 16 synchronized to the vertical blanking pulse. This horizontal synchronizing pulse is transmitted to the pulse delay circuit 17 and the logic circuit 1.
8 to create a horizontal synchronization signal (H.SYNC pulse) 20.

The H.SYNC pulse is applied to logic circuit 22 and combined with other pulses to form a composite synchronization signal.
The H.SYNC pulse is also used as one phase of two-phase vertical clock pulses for driving the vertical shift register of the solid-state image sensor.

The horizontal synchronization pulse 16 is also supplied to a pulse width control circuit 19, which generates a horizontal blanking pulse 21.

The horizontal blanking pulse is used as another phase of vertical clock pulse, but is also used to synchronously oscillate the horizontal clock pulse generator 23 and generate a clock pulse 24 for driving the horizontal shift register.

Two-phase clock pulses are required to drive the horizontal shift register; 24 clock pulses are used for one phase, and 24 clock pulses are used for the other phase using a pulse delay circuit 25 and a pulse width control circuit 26.
Make pulse 27 from 4. Note that the frequency of the horizontal clock pulse is determined by the number of pixels arranged in the horizontal direction of the solid-state image sensor. For example, in the case of 320 pixels, it is approximately
It becomes 6MHz.

Horizontal clock pulse 24 is also provided to logic circuit 28 and is combined with horizontal blanking pulse 21 to form horizontal input pulse 29.

The composite blanking signal is generated by the logic circuit 22 from the horizontal blanking signal 21 and the blanking signal 33, and the composite synchronization signal is generated by the logic circuit 22 from H.SYNC.
are produced by the respective combinations of pulse 20 and vertical sync pulse 14.

In the drive circuit of the present invention, the horizontal clock pulse is synchronized with the vertical synchronization pulse, and the horizontal synchronization pulse is synchronized with the vertical synchronization pulse. Therefore, the drive circuit of the present invention does not require a counter circuit or a complicated logic circuit, and is different from the conventional drive circuit shown in FIG. Although it has exactly the same function as the drive circuit, the circuit can be simplified, and as described above, it is possible to completely eliminate the noise generated in the counter circuit.

Also, HD (horizontal drive pulse) 3 can be input from the outside.
1 or VD (vertical drive pulse) 32, it is easy to perform external synchronization by switching the switch, and it also has the advantage of being able to add an external synchronization function without adding any special circuit.

FIG. 6 shows another embodiment that satisfies the gist of the present invention. The feature of this embodiment is that a horizontal synchronizing frequency is oscillated, a horizontal clock pulse is oscillated in synchronization with the horizontal synchronizing signal, and a vertical synchronizing frequency is generated using a frequency dividing circuit.

That is, the oscillator 34 oscillates a horizontal synchronizing frequency to obtain a horizontal synchronizing pulse (FIG. 4, 16). The horizontal synchronizing pulse 16 is first used to synchronize the horizontal clock pulse generator 35. The output 25 of the horizontal clock pulse generator is used as it is as one phase pulse of the two-phase horizontal clock pulse,
The other phase pulse 27 is generated by a pulse delay circuit 36 and a pulse width control circuit 37.

The horizontal synchronizing pulse 16 is also applied to a pulse width control circuit 38 and a horizontal blanking pulse generation circuit 39. The output pulse of pulse width control circuit 38 is combined with a horizontal sync pulse in logic circuit 40 to generate H.
Make SYNC pulse 20. The H.SYNC pulse 20 is also used as one phase of the vertical shift register drive pulse.

The output pulse 21 of the horizontal blanking pulse generation circuit 39 is used as a pulse for one phase of the vertical clock pulse, and is also used as a pulse for one phase of the vertical clock pulse.
and is combined with horizontal clock pulse 25 to produce horizontal input pulse 29.

The horizontal blanking pulse 21 is the counter circuit 4
It is also used as the second drive pulse. The counter circuit 42 is a circuit that generates a vertical synchronization frequency from the horizontal synchronization frequency, and its output is supplied to a pulse logic circuit 43 to generate a vertical input pulse 30 and a vertical blanking signal 33. A composite blanking signal is generated by combining the horizontal blanking signal 21 and the vertical blanking signal 33 in a logic circuit 44. In addition, the composite synchronization signal is generated by the logic circuit 45 with H.SYNC pulse 20,
It is synthesized from the vertical synchronization pulse 14 generated by the vertical synchronization signal generation circuit 46.

Also in this embodiment, synchronization with an external synchronization pulse can be easily achieved without adding any special circuit. In other words, horizontal synchronization can be done by simply receiving the HD pulse 31 from the outside and switching it with a switch.
Vertical synchronization is externally applied VD pulse 32
It is sufficient to reset the counter circuit 42 with .

The output pulses of the horizontal synchronous frequency oscillators shown at 15 in Fig. 2 and 34 in Fig. 6 have pulse duties of 18% or less and 8%, respectively, as shown in Fig. 7.
Must be as follows. This is to prevent spike noises generated at the rise and fall of pulses from appearing on the screen, and to cause these spike noises to occur during the blanking period of the video signal.

〔Effect of the invention〕

Hereinafter, the synchronization signal generation circuit of the present invention can realize a synchronization signal generation circuit that does not generate periodic noise that harms the video signal and is capable of external synchronization with a simple circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit configuration diagram of a conventional device, Fig. 2 is a drive circuit configuration diagram showing a first embodiment of the present invention, and Figs.
FIG. 5 is a signal waveform diagram in the above embodiment circuit, FIG. 6 is a configuration diagram of a drive circuit showing a second embodiment of the present invention, and FIG. 7 is a signal waveform diagram of output pulses. In the figure, 9 is a horizontal shift register, 10 is a vertical shift register, 11 is a vertical synchronous frequency oscillator, and 34 is a horizontal synchronous frequency oscillator.

Claims (1)

[Claims] 1. In a drive circuit that generates clock pulses for driving a solid-state image sensor, a horizontal synchronous frequency oscillator that oscillates in synchronization with a vertical synchronous frequency, which is the lowest frequency handled by the driving circuit, as a reference; What is claimed is: 1. A driving circuit for a solid-state image sensor, comprising a horizontal clock pulse generator that oscillates in synchronization with a signal from a synchronous frequency oscillator, and generating clock pulses from the low frequency to the high frequency in stages.