JPS5962270A - Pulse generating circuit for solid-state television camera - Google Patents

Abstract

PURPOSE:To decrease the number of stages of a shift register of a solid-state TV pulse generating circuit, by applying a different clock frequency between an m-bit section and an n-bit section among (m+n)-bit shift registers. CONSTITUTION:The horizontal frequency is produced at a ring counter circuit using the shift registers and pulses with shifted phase from each state of the shift registers are combined, allowing to form all required pulses for the camera. A high frequency pulse is formed at an oscillating circuit 31 and frequency- divided into two at a frequency division circuit 90. A pulse generated at an input pulse generating section 41 is inputted to a shift register 33a of 189 stages determining the video image period and a shift register of 77 stages determining the horizontal blanking period. Taking the clock of the former shift register as 3.58MHz and the latter as 7.2MHz, the period of pulse required for one circulation is one horizontal scanning period, and the number of stages is decreased less than a circuit driving all shift registers in the same frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an S pulse generation circuit for a television camera, and more particularly to a synchronization signal generation circuit for a television camera using a solid-state image sensor.

[Prior art]

If a method is adopted in which the original oscillation frequency is counted down to a predetermined low frequency using a counter circuit, the pulse noise generated at each stage of the counter circuit will enter the output signal line via the power supply line, ground line, or due to electrostatic coupling. This causes synchronous noise that appears as a vertical striped pattern on the monitor screen and degrades the image quality.

Therefore, the inventors of the present invention have already filed an application for a pulse generation circuit for a solid-state camera with a novel configuration that does not generate synchronous noise by using a shift register as a horizontal counter (Application No. 56-117777).

This pulse generation circuit generates pulses at all horizontal scanning frequencies using a circuit called a ring counter, which connects the input end and output end of a shift register, and a decoder circuit. Let the frequency noculus be l/n and 1/(n-
l-1) (n is a positive integer).
Moreover, by delaying the l/n frequency division mode pulse by 1/2 (horizontal scanning time), a frame number that can be interlaced is obtained.The basic content of this earlier patent is as follows. explain.

FIG. 1 is a block diagram showing the main parts of the pulse generation circuit of the earlier patent (application number 56-117777).

The circuit 31 is an oscillation circuit that generates high-frequency pulses,
The circuit 32 generates a horizontal clock signal Cpx from its high frequency signal.
This is a circuit that generates

As described above, the pulse generation circuit of the present invention does not use a horizontal ring, but instead uses a ring counter circuit to generate the horizontal scanning frequency.

The ring counter circuit connects the input terminal and output terminal of the shift register shown in FIG. , the clock pulses are used to shift the clock pulses one stage at a time.

Ring counter beam [As long as one pulse is supplied, the above-mentioned manual pulse continues to be transferred, so if the above-mentioned transfer pulse is taken out from one output terminal, a counter of 1/the number of stages of the shift register can be formed. The clock frequency can be directly divided into 1/n (n is the number of stages of the shift register).

Also, from this shift register 33, output pulses whose phase is shifted by one clock can be obtained from each stage, so by combining the pulses with the necessary phases, all the pulses necessary for the camera can be created. I can do it.

For example, when using a clock pulse of 14.31818 MIIZ, a 910-stage shift register (clock foot register) is required in the NTS C system, and 910 pulses with different phases at a frequency of 15.755...KH2 are required. can be made.

Therefore, necessary pulses are extracted from the shift register that generates pulses with a phase within the blanking period of the video signal, and the line decoder circuit 34 generates various pulses l(D
, Vsx, Upyl, Cry2, 248.

Make 24Ii' and 24B.

The circuit 35 is an equalization pulse decoder circuit, which generates equalization pulses 27E and 27Vt within the vertical blanking period.

Note that the equalization pulse decoder circuit uses the vertical blanking pulse 2713! ll operation is limited (rl), and is designed to operate within the vertical blanking period.

In this pulse generation circuit, the pulse that determines 1/2 water W water use/scanning exists only during the vertical planking period, so
It is not easy to create a shogi synchronization pulse that is compatible with interlaced scanning.

In the circuit of the present invention, the horizontal scanning frequency is set to 1/C.
Divide the frequency in two modes: n/(n-1-1), 1/
! The purpose is achieved by delaying the frequency division mode by 1/2 horizontal scanning time.

The circuit 61 is a counter circuit for dividing the frequency of the horizontal plan Young pulse 24I3 generated by the line decoder. This counter circuit 61 is the first. has a second branch mode,
The input pulses are counted in one of the modes specified by the control signal 628 output from the control circuit 62, and each time the manual pulse reaches a predetermined value, the output pulse 61 shown in FIG.
S f: Occurs.

In the first frequency division mode, an output pulse 618 is generated every 262 input pulses, and in the 20th frequency division mode, an output pulse is generated every 263 input pulses.

The control circuit 62, for example, outputs pulses from a counter for 1s.
It is a flip-flop circuit that inverts the state upon receiving t.

Therefore, the pulse 61 from the control circuit 62 and the S counter 61 is
Each time 8 is output, the state is inverted, and upon receiving this control signal, the counter 61 alternately repeats the 1st and 2nd frequency division modes.

This is a noft register with 83 parallel output circuits.

In this embodiment, the output pulses 618 (shown in FIG. 2) of the counter 61 are input to the shift register 83, and the output pulses are combined to form a desired pulse.

80, 81, and 82 are circuits that generate clock pulses to be supplied to the shift register 83, and the horizontal blanking pulse shown in FIG.
The output 808 is delayed by 1/2 horizontal scanning time by a delay circuit 81 to obtain an output 818.

82 corresponds to the control signal 628 to control the above two systems 7 (Rus 8).
A circuit that alternately selects 0S and 818, and its output 82S
When applied to the ffi shift register 83, the output pulse of 83 is delayed by 1/2 horizontal scanning time for each field. Further, 62S is also used as a field discrimination pulse.

Note that the counter circuit 80 is reset every 262 and 263 horizontal scanning periods by the synchronization pulse 618 of the counter circuit 61, so that the timings of the output pulses of both counters match.

Since the output terminal of each stage of the shift register receives a pulse train -h<+- as shown in FIG. 2 838, the frame decoder circuit 3
By combining these pulse trains in step 7, vertical drive pulse VD pulse, vertical blanking pulse 27B
The composite decoder circuit 36 that generates the 1 vertical synchronization pulse 278 generates composite synchronization pulses 5YNC, 47-combined blanking pulse BL, from the output pulses of the line decoder 34, equalization pulse decoder 35, and frame decoder 37.
A burst flag BF and a vertical human power pulse Vsy are generated.

The basic configuration of the six-pulse generation circuit in the earlier patent (Application No. 56-117777) has been explained above, but in this method, pulse transfer is performed to all ring counters 33 using the same clock, so the number of stages of the shift register increases. This has the disadvantage that the circuit becomes complicated. Particularly when converting the circuit of the above system into an IC, it is necessary to take measures to reduce the number of stages, simplify the circuit, and reduce power consumption.

[Purpose of the invention]

An object of the present invention is to provide a method for reducing the number of stages of 77 transistors in a synchronization signal generation circuit that uses a ring counter to obtain a synchronization signal.

[General explanation of the invention]

The present invention has a total number of stages ((m+n) stages (m
, n is a positive integer), m stages corresponding to the horizontal blanking period and 0 stages corresponding to the video period are transferred using clock pulses of different frequencies.

In the prior patent, for example, when using a clock pulse of 14.31818 MH2, the NTSC system required a 910-stage shift register, but with the present invention, the video period can be reduced to 7.2 MHz and the horizontal blanking period to 14.
．． Since pulses can be transferred using clocks of two different frequencies, such as 31818MH2, the total number of stages is 532.The number of shift register stages is 378 fewer than the one that transfers pulses only using 14.3MH2 clock pulses. I can do it.

The band of the video signal is approximately 3 MHz for an NTSC home video camera. Therefore, if the transfer lock frequency of the shift register that operates during the video period is set to be higher than the frequency of the video signal (for example, 3.58M) (Z), the above-mentioned synchronous noise can be removed with a low-pass filter, thereby improving the image quality. cannot be influenced. On the other hand, the parts that operate during the horizontal pushing period do not affect the video signal, so when configuring a ring counter, the number of stages of the shift register is determined by the time it takes for one pulse to go around in one horizontal scanning period. Any combination with the clock frequency may be selected.

Reducing the number of stages of the shift register by this method is very useful when implementing the pulse generation circuit of the present invention into an IC. It also has the advantage of leading to savings in power consumption.

〔Example〕

The present invention will be described below with reference to embodiments in the NTSC system.

FIG. 3 shows an embodiment of a shift register section that satisfies the gist of the present invention.

31 is an oscillation circuit that generates high-frequency pulses, and in this embodiment, the oscillation frequency is set to 7.2M11Z. 90
is a frequency dividing circuit that divides 7.2MH2 into 1. 41 is an input pulse generator, and 42 is an OR gate.

Of the 266 stages of shift registers, 189 stages of the 7-shift register 33a are set to 3.58. It is transferred using a pulse of MH2 (subcarrier frequency), and is transferred to a 77-stage shift register 33b17.
When transferring with 2 MIIZ pulses, it takes one horizontal scanning period for one pulse to go around the ring counter made up of 41 in this 266-stage shift register. 189 here
The shift register 33a of the stage determines the video period 7'7
The stage /ft register 33b defines the horizontal blanking period. Since the signal band of a home video camera is about 3MIIZ, the shift register that determines the video period is 3.
Driven by 58 MIIZ clock pulse, 'C is also practical,
Synchronous noise is not a problem. The reason why the horizontal blanking period is driven at 7.2 MHz and the number of stages of the shift register is 77 is because pulses with different phases are required to form the drive pulse and synchronization signal pulse of a solid-state camera. This is because it is necessary. In addition, pulse 331)-8 is output from the section corresponding to 41'' in the plan young period -C
The reason for the input to the frequency dividing circuit 90 is that the phase of the 3.58 MHz pulse is inverted every horizontal scanning period, so the pulse 33b-8 resets the signal so that no phase inversion occurs every horizontal scanning period. This is because I did so. Therefore,
In some cases, it may not be necessary to increase the frequency of the clock used to drive the shift register.

By means of increasing the horizontal scanning frequency shown in Figure 3, the vertical scanning frequency and the pulses necessary to drive the solid-state camera are generated.'' - The circuit is not shown in Figure 1 and is the same as the embodiment of the earlier patent. Therefore, the explanation will be omitted.

FIG. 4 shows another embodiment. The 227-stage shift register 33 ai"t: 3.58 MII Z is driven by a clock pulse, and only one stage 33 b is driven by a 7.2 M) i z clock pulse. When one pulse is input, it takes one horizontal period for the pulse to go around the ring counter once.Furthermore, the front 189 stages of shift register 33)1 determine the video period, and the rear 38 stages and shift register 33b determine the video period. A horizontal blanking period is determined.The explanation of the music part is the same as that of the embodiment shown in FIG. 3, so the explanation will be omitted.

The above explanation took the NTSC force formula as an example, but lJ
Even in the AL system, the gist of the present invention can be applied to the synchronization signal generation circuit.

〔Effect of the invention〕

The gist of the present invention has been described in detail above, but if the means for obtaining the horizontal scanning frequency of the present invention is used, the S/
It would be possible to generate the necessary pulses with the solid-state ten vision camera 1 without adversely affecting N, and furthermore, the number of stages of the shift register could be reduced.

[Brief explanation of drawings]

Claims (1)

[Claims] 1. In a pulse generation circuit that generates a horizontal scanning pulse from a shift register and obtains a vertical scanning frequency from the frequency of the horizontal scanning pulse, the total number of pits (
m-1-n) out of pits (m. n is a positive integer)! With an interval of n bits! A pulse generation circuit for a solid-state television camera that transfers pulses at a clock frequency different from the interval of 1 bit at /1 m. 2. In the pulse generation circuit for a solid-state television camera according to claim 1, the IT1 bit section among the total number of bits (m-1-n) pits (m and n are positive integers) of the shift register. A pulse generation circuit for a solid-state television camera, characterized in that it is driven at a subcarrier frequency.