JP2551997B2 - Synchronization signal generation circuit for solid-state imaging device - Google Patents
Synchronization signal generation circuit for solid-state imaging deviceInfo
- Publication number
- JP2551997B2 JP2551997B2 JP1132399A JP13239989A JP2551997B2 JP 2551997 B2 JP2551997 B2 JP 2551997B2 JP 1132399 A JP1132399 A JP 1132399A JP 13239989 A JP13239989 A JP 13239989A JP 2551997 B2 JP2551997 B2 JP 2551997B2
- Authority
- JP
- Japan
- Prior art keywords
- horizontal
- counter
- decoder
- solid
- vertical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 title claims description 8
- 238000003384 imaging method Methods 0.000 title claims description 6
- 125000004122 cyclic group Chemical group 0.000 claims description 3
- 239000002131 composite material Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- 230000002194 synthesizing effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
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- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は固体撮像装置の固体撮像素子を駆動する駆動
回路と同期信号発生回路とを単一の半導体チップに形成
した集積回路に関し、特に同期信号発生回路からの回り
込みノイズにより有効映像期間に発生する縦線ノイズを
低減した固体撮像装置の同期信号発生回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit in which a drive circuit for driving a solid-state image pickup device of a solid-state image pickup device and a synchronizing signal generating circuit are formed on a single semiconductor chip, and more particularly to a synchronous circuit. The present invention relates to a synchronous signal generation circuit for a solid-state imaging device in which vertical line noise generated in an effective video period due to sneak noise from the signal generation circuit is reduced.
従来、この種の固体撮像装置の固体撮像素子を駆動す
る駆動回路と同期信号発生回路とを単一の半導体チップ
に形成した集積回路は、同期信号の規格上第４図に示す
ように複合同期信号CSYNが水平同期周波数fHの２倍（2f
H）の成分を含むため、第２図に示すような構成をとる
のが通常である。すなわち、発振器101の出力は固体撮
像素子駆動回路102を介して固体撮像素子109を駆動する
固体撮像素子駆動信号を発生し、また、発振器101の出
力は、水平カウンタ103に入力され水平デコーダ106から
水平ドライブ信号HDを作るとともにコンポジットデコー
ダ108にも入力信号を与える。この水平カウンタ103から
の水平同期周波数fHの２倍（2fH）の成分を持つ信号は
垂直カウンター104に加えられ、垂直デコーダ107の出力
と、水平同期周波数の２倍（2fH）の成分を持つ水平デ
コーダ106の出力とをコンポジットデコーダ108で合成す
ることにより、水平同期周波数の２倍（2fH）の成分を
含む複合同期信号CSYNを発生させていた。Conventionally, an integrated circuit in which a drive circuit for driving a solid-state image pickup element of this type of solid-state image pickup device and a synchronization signal generation circuit are formed on a single semiconductor chip has a composite synchronization as shown in FIG. Signal CSYN is twice the horizontal sync frequency fH (2f
Since it contains the component (H), it is usually configured as shown in FIG. That is, the output of the oscillator 101 generates a solid-state image sensor drive signal for driving the solid-state image sensor 109 via the solid-state image sensor drive circuit 102, and the output of the oscillator 101 is input to the horizontal counter 103 and output from the horizontal decoder 106. The horizontal drive signal HD is generated and the input signal is also given to the composite decoder 108. A signal having a component (2fH) twice the horizontal synchronizing frequency fH from the horizontal counter 103 is added to the vertical counter 104, and an output of the vertical decoder 107 and a horizontal component having a component twice the horizontal synchronizing frequency (2fH). By synthesizing the output of the decoder 106 with the composite decoder 108, the composite synchronizing signal CSYN including the component of twice the horizontal synchronizing frequency (2fH) is generated.
上述した従来の固体撮像装置の固体撮像素子を駆動す
る駆動回路と同期信号発生回路とを単一の半導体チップ
に形成した集積回路では、同期信号発生回路は、水平カ
ウンタ103で発振器101の出力を水平同期周波数fHの２倍
（2fH）に分周し、水平デコーダ106によって水平同期周
波数fHの２倍（2fH）成分を含む信号を取り出している
ため、第３図に示すように、水平デコーダ106のスイッ
チングノイズが固体撮像素子駆動回路102に回り込み、
有効映像期間に縦線状ノイズとして現われるという欠点
がある。In the integrated circuit in which the drive circuit for driving the solid-state imaging device of the conventional solid-state imaging device and the synchronization signal generation circuit described above are formed on a single semiconductor chip, the synchronization signal generation circuit outputs the output of the oscillator 101 by the horizontal counter 103. The horizontal decoder 106 divides the frequency by two times the horizontal synchronizing frequency fH (2fH), and the horizontal decoder 106 extracts a signal including twice the horizontal synchronizing frequency fH (2fH). Therefore, as shown in FIG. Switching noise of the sneak into the solid-state image sensor drive circuit 102,
There is a drawback that it appears as vertical line noise during the effective video period.
本発明によれば、水平同期周波数（fH）でフィードバ
ックされ巡回する巡回型シフトレジスタによって構成さ
れる水平カウンタから水平同期周波数の２倍（2fH）の
信号のデコード出力を制御できる水平デコーダと、水平
同期周波数の２倍（2fH）で動作する垂直カウンタと、
水平同期周波数（fH）で動作する垂直カウンタと、垂直
ブランキング期間以外の期間前記水平デコーダと水平同
期周波数fHの２倍（2fH）で動作する垂直カウンタを停
止する制御回路とを有する固体撮像装置用同期信号発生
回路を得る。According to the present invention, a horizontal decoder capable of controlling the decoding output of a signal of twice the horizontal synchronization frequency (2fH) from a horizontal counter configured by a cyclic shift register that is fed back at the horizontal synchronization frequency (fH) and cyclically, A vertical counter that operates at twice the synchronization frequency (2fH),
A solid-state imaging device having a vertical counter that operates at a horizontal synchronizing frequency (fH), and a control circuit that stops the horizontal decoder and a vertical counter that operates at twice the horizontal synchronizing frequency fH (2fH) during periods other than the vertical blanking period. To obtain a synchronizing signal generating circuit for use.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の構成図である。発振器10
1の出力は、固体撮像素子駆動回路102に入力されて固体
撮像素子駆動信号を発生し、固体撮像素子109を駆動す
る。また発振器101の出力は、水平同期周波数（fH）で
フィードバックされ巡回する巡回型シフトレジツタによ
って構成される水平カウンタ201に入力される。そして
水平カウンタ201は発振器101の出力信号を水平同期周波
数（fH）に分周し垂直カウンタ202に出力するととも
に、2FHデコーダ203に水平同期周波数の２倍（2fH）の
信号を発生させるための信号を出力する。制御回路205
は垂直カウンタ202の出力により垂直ブランキング期間
かどうかの情報を得て水平カウンタ201からの信号によ
り水平同期周波数の２倍（2fH）の周波数を生成する2FH
デコーダ203と、この2FHデコーダ203の出力を入力クロ
ックとして動作する垂直カウンタ206と、水平周波数の
２倍（2fH）の同期信号成分をコンポジットデコーダ108
に出力している水平デコーダ204の2fHデコーダ部とを垂
直ブランキング期間以外の期間停止させる。例えばNTSC
方式では第１フィールドは第21ラインの初めから第263
ラインの途中まで、第２フィールドは第283ラインの途
中から第525ラインの終りまでの期間止める。一方、垂
直ブランキング期間では2FHデコーダ203が水平カウンタ
201からの信号をデコードして2fH分周信号を生成し、垂
直カウンタ206を動作させる。そして、垂直デコーダ207
は垂直カウンタ202の水平同期周波数（fH）の成分と、
垂直カウンタ206の水平同期周波数の２倍（2fH）の成分
とを合成することにより、水平同期周波数の２倍（2f
H）の成分を出力に持つことができる。水平デコーダ204
の水平同期周波数の２倍（2fH）の成分を持つ出力と垂
直デコーダ207の出力をコンポジットデコーダ108で合成
することにより水平同期周波数の２倍（2fH）の成分を
含む複合同期信号CSYNを発生することができる。このよ
うな垂直ブランキング期間以外の期間における水平同期
周波数の２倍（2fH）のクロック成分の発生の停止と水
平同期周波数の２倍（2fH）で動作する垂直カウンタ206
の停止と、水平同期周波数の２倍（2fH）のデータを出
力している水平デコーダ204の2fHデコード部の停止は、
有効走査期間の同期信号には水平同期周波数の２倍（2f
H）の成分の同期信号は存在しないため信号発生上全く
支障はない。FIG. 1 is a configuration diagram of one embodiment of the present invention. Oscillator 10
The output of 1 is input to the solid-state image sensor drive circuit 102 to generate a solid-state image sensor drive signal and drive the solid-state image sensor 109. The output of the oscillator 101 is fed back to the horizontal counter 201 which is composed of a cyclic shift register which is fed back at the horizontal synchronizing frequency (fH) and cyclically moves. Then, the horizontal counter 201 divides the output signal of the oscillator 101 into a horizontal synchronizing frequency (fH) and outputs it to the vertical counter 202, and at the same time, causes the 2FH decoder 203 to generate a signal twice the horizontal synchronizing frequency (2fH). Is output. Control circuit 205
2FH, which obtains the information on whether the vertical blanking period or not by the output of the vertical counter 202 and generates a frequency twice the horizontal synchronizing frequency (2fH) by the signal from the horizontal counter 201.
The decoder 203, the vertical counter 206 that operates using the output of the 2FH decoder 203 as an input clock, and the composite decoder 108 that outputs a synchronization signal component that is twice the horizontal frequency (2fH).
And the 2fH decoder section of the horizontal decoder 204, which is outputting to, is stopped during a period other than the vertical blanking period. For example NTSC
In the method, the first field is 263 from the beginning of the 21st line.
Halfway through the line, stop in the second field from the middle of line 283 to the end of line 525. On the other hand, in the vertical blanking period, the 2FH decoder 203 operates as a horizontal counter.
The signal from 201 is decoded to generate a 2fH divided signal, and the vertical counter 206 is operated. And the vertical decoder 207
Is the horizontal sync frequency (fH) component of the vertical counter 202,
By synthesizing with the component of the horizontal synchronizing frequency of the vertical counter 206 (2fH), the horizontal synchronizing frequency is doubled (2fH).
H) component can be output. Horizontal decoder 204
By synthesizing the output having the component of twice the horizontal synchronizing frequency (2fH) and the output of the vertical decoder 207 by the composite decoder 108, the composite synchronizing signal CSYN including the component of the twice the horizontal synchronizing frequency (2fH) is generated. be able to. In the period other than the vertical blanking period, the generation of the clock component at twice the horizontal synchronizing frequency (2fH) is stopped and the vertical counter 206 operates at twice the horizontal synchronizing frequency (2fH).
And the stop of the 2fH decoding section of the horizontal decoder 204 which outputs data of twice the horizontal synchronizing frequency (2fH),
Double the horizontal sync frequency (2f
Since there is no synchronizing signal of component H), there is no problem in signal generation.
以上説明したように、本発明は有効映像期間には縦線
の原因となる水平同期周波数の２倍（2fH）の成分及び
この水平同期周波数の２倍（2fH）で動作するカウンタ
を停止することにより、従来の同期信号発生回路では避
けることのできなかった水平同期周波数の２倍（2fH）
成分による画面に生じる縦線状固定パターンノイズを無
くすことができる効果がある。As described above, according to the present invention, the component operating at twice the horizontal synchronizing frequency (2fH) causing vertical lines and the counter operating at twice the horizontal synchronizing frequency (2fH) are stopped during the effective video period. Therefore, double the horizontal sync frequency (2fH) that could not be avoided by the conventional sync signal generator.
There is an effect that vertical line fixed pattern noise generated on the screen due to the component can be eliminated.
第１図は本発明の一実施例の構成を示すブロック図、第
２図は従来技術の構成を示すブロック図、第３図は有効
映像期間の中央付近に発生する縦線状ノイズを説明する
ための図、第４図は水平同期周波数の２倍（2fH）の成
分を持つ複合同期信号を説明するための図である。 101……発振器、102……固体撮像素子駆動回路、103…
…水平カウンタ、104……垂直カウンタ、105……２分周
回路、106……水平デコーダ、107……垂直デコーダ、10
8……コンポジットデコーダ、109……固体撮像素子、20
1……水平カウンタ、202……垂直カウンタ、203……2FH
デコーダ、204……水平デコーダ、206……垂直カウン
タ、207……垂直デコーダ。FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a conventional technique, and FIG. 3 is a diagram for explaining vertical line noise generated near the center of an effective video period. FIG. 4 is a diagram for explaining a composite sync signal having a component of twice the horizontal sync frequency (2fH). 101 ... Oscillator, 102 ... Solid-state image sensor drive circuit, 103 ...
… Horizontal counter, 104 …… Vertical counter, 105 …… Division circuit, 106 …… Horizontal decoder, 107 …… Vertical decoder, 10
8: Composite decoder, 109: Solid-state image sensor, 20
1 …… horizontal counter, 202 …… vertical counter, 203 …… 2FH
Decoder, 204 ... Horizontal decoder, 206 ... Vertical counter, 207 ... Vertical decoder.
Claims (1)
れ巡回する巡回型シフトレジスタによって構成される水
平カウンタと、前記水平カウンタから水平同期周波数の
２倍（2fH）の信号のデコード出力を制御できる水平デ
コーダと、水平同期周波数の２倍（2fH）で動作する垂
直カウンタと、水平同期周波数（fH）で動作する垂直カ
ウンタと、垂直ブランキング期間以外の期間前記水平デ
コーダと前記水平同期周波数の２倍（2fH）で動作する
垂直カウンタを停止する制御回路とを有することを特徴
とする固体撮像装置用同期信号発生回路。1. A horizontal counter composed of a cyclic shift register which is fed back at a horizontal synchronizing frequency (fH) and cyclically, and a horizontal counter capable of controlling decoding output of a signal of twice the horizontal synchronizing frequency (2fH) from the horizontal counter. A decoder, a vertical counter that operates at twice the horizontal synchronization frequency (2fH), a vertical counter that operates at the horizontal synchronization frequency (fH), a period other than the vertical blanking period, and the horizontal decoder and twice the horizontal synchronization frequency A synchronization signal generation circuit for a solid-state imaging device, comprising: a control circuit that stops a vertical counter that operates at (2fH).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1132399A JP2551997B2 (en) | 1989-05-24 | 1989-05-24 | Synchronization signal generation circuit for solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1132399A JP2551997B2 (en) | 1989-05-24 | 1989-05-24 | Synchronization signal generation circuit for solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02309772A JPH02309772A (en) | 1990-12-25 |
| JP2551997B2 true JP2551997B2 (en) | 1996-11-06 |
Family
ID=15080485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1132399A Expired - Fee Related JP2551997B2 (en) | 1989-05-24 | 1989-05-24 | Synchronization signal generation circuit for solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2551997B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2765684B2 (en) * | 1991-11-29 | 1998-06-18 | シャープ株式会社 | CCD drive integrated circuit |
-
1989
- 1989-05-24 JP JP1132399A patent/JP2551997B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02309772A (en) | 1990-12-25 |
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