JP2758615B2 - Synchronous signal generation circuit for solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit in which a driving circuit for driving a solid-state imaging device of a solid-state imaging device and a synchronizing signal generating circuit are a single integrated circuit, and in particular, synchronizing signal generation. The present invention relates to a synchronous signal generation circuit of a solid-state imaging device that reduces vertical line noise generated near the center of an effective video period due to sneak noise from a circuit.

[Conventional technology]

Conventionally, an integrated circuit in which a drive circuit for driving a solid-state image sensor of this type of solid-state imaging device and a synchronization signal generation circuit are a single circuit has a complex synchronization signal as shown in FIG. Since a component having twice the horizontal synchronization frequency (2H) is included, a configuration as shown in FIG. 5 is usually employed. That is, the output of the oscillator 101 generates a solid-state imaging device drive signal, and the output of the oscillator 101 is input to the horizontal counter 103 and the output of the vertical decoder 107 having a component of twice the horizontal synchronization frequency (2H) and the horizontal decoder. By combining the outputs of 106 with the composite decoder 108, a composite synchronizing signal including a component twice (2H) of the horizontal synchronizing frequency is generated.

[Problems to be solved by the invention]

The synchronizing signal generation circuit of the integrated circuit in which the driving circuit for driving the solid-state imaging device of the conventional solid-state imaging device and the synchronizing signal generating circuit are a single integrated circuit, the output of the oscillator is output by the horizontal counter to the horizontal synchronizing frequency of 2 Since the vertical counter 104 is operated at twice (2H) the horizontal synchronization frequency by the 2H clock signal, the third frequency is obtained.
As shown in the figure, there is a drawback that the switching noise of the vertical counter 104 goes to the solid-state imaging device driving circuit 102 and appears as a vertical line noise near the center of the effective video period.

[Means for solving the problem]

A synchronous signal generation circuit for a solid-state imaging device according to the present invention includes a horizontal counter that divides an output of an oscillator to a horizontal synchronization frequency (fH), and a first counter that receives the output of the horizontal counter and operates at the horizontal synchronization frequency (fH). A vertical counter, a second vertical counter operating at twice the frequency (2fH) of the horizontal synchronization frequency, and the second counter receiving the output of the first vertical counter.
And a vertical decoder for generating a solid-state imaging device synchronization signal from the output signals of the first and second vertical counters.

Further, in the synchronization signal generation circuit for a solid-state imaging device according to the present invention, the horizontal counter is constituted by a cyclic shift register, and the horizontal synchronization frequency is supplied to the second vertical counter via a decoder for decoding an output of the shift register. 2
A clock having a double frequency (2fH) may be provided.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of one embodiment of the present invention. Oscillator 10
The output of 1 is input to the solid-state imaging device driving circuit 102 to generate a solid-state imaging device driving signal and drive the solid-state imaging device. The output of the oscillator 101 is input to the horizontal counter 205 to generate a frequency twice (2H) of the horizontal synchronizing frequency and to divide the frequency into the horizontal synchronizing frequency (H).
To work. FIG. 2 is a configuration diagram of the horizontal counter 205.
It is composed of a single-column cyclic shift register. One flip-flop always has a state of logic "1", and the other flip-flops have a state of logic "0". Therefore, since only one logic "1" of the cyclic shift register is always shifted in the entire circuit, there is no fluctuation in power consumption and no generation of synchronizing noise. The control circuit 202 obtains information on whether a vertical blanking period is present from the output of the vertical counter 201, and controls the vertical counter 203 operating at a frequency twice (2H) of the horizontal synchronization frequency and twice (2H) of the horizontal synchronization frequency to be vertical. Suspended for periods other than blanking period.
For example, in the NTSC system, the first field is stopped from the beginning of the 21st line to the middle of the 263rd line, and the second field is stopped from the middle of the 283rd line to the end of the 525th line.
The vertical decoder 204 synthesizes a horizontal synchronization frequency (H) component of the vertical counter 201 and a double (2H) component of the horizontal synchronization frequency of the vertical counter 203 to generate a component of twice the horizontal synchronization frequency (2H). The composite decoder 108 can generate a composite synchronization signal including a component twice as high as the horizontal synchronization frequency (2H) by combining the output of the vertical decoder 204 and the output of the horizontal counter 205 with the composite decoder 108. . Twice (2) times the horizontal synchronization frequency in periods other than such a vertical blanking period
H) Stop of generation of clock component and horizontal synchronization frequency 2
The stop of the vertical counter 203 operating at twice (2H) means that the synchronization signal during the effective scanning period is twice (2H) the horizontal synchronization frequency.
Since there is no synchronization signal of the component H), there is no problem in signal generation.

FIG. 6 is a block diagram showing another embodiment of the present invention. FIG. 6 is a block diagram of a cyclic shift register according to another configuration method of the vertical counter using the cyclic shift register shown in the embodiment of FIG.

The vertical counter according to the present embodiment includes a plurality of cyclic shift registers of different stages each having no common divisor, and a coincidence circuit. Reference numerals 301, 302, and 303 denote five-stage, six-stage, and seven-stage shift registers, respectively, and the output of each shift register is connected to the coincidence circuit 304. The output from the oscillator is input to each shift register as a clock. In the cyclic shift register having this configuration, the respective outputs of the cyclic shift registers 301, 302, and 303 match, and the cyclic shift register has the number of clocks at which each shift register is reset by the output of the matching circuit 304.

The cyclic shift register having this configuration is characterized in that it can be configured with a shift register having a very small number of stages as compared with a single-column cyclic shift register. In the same manner as described above, since the power consumption does not fluctuate, frequency division noise other than the H period of the horizontal synchronization frequency is not generated. The horizontal synchronizing frequency H and the doubled 2H decoding output obtained from the shift register shown in FIG. 6 are applied to two vertical counters, respectively, and operate in the same manner as in the first embodiment. , A synchronous signal generating circuit capable of preventing the generation of vertical linear noise can be configured.

〔The invention's effect〕

As described above, according to the present invention, during the effective video period, the generation of a component twice the horizontal synchronization frequency (2H) that causes a vertical line and the counter operating at twice the horizontal synchronization frequency (2H) are provided. By stopping, there is an effect that vertical line fixed pattern noise generated at the center of the screen due to a double (2H) component of the horizontal synchronization frequency, which cannot be avoided in the conventional synchronization signal generation circuit, can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention,
FIG. 2 is a block diagram showing the configuration of the horizontal counter 205, FIG. 3 is a diagram for explaining vertical linear noise generated near the center of the effective video period, and FIG.
FIG. 5 is a block diagram showing a configuration of the prior art, and FIG. 6 is a block diagram of a cyclic shift register used in another embodiment of the present invention. 101 ... Oscillator, 102 ... Solid-state image sensor drive circuit, 103 ...
… Horizontal counter, 104… conventional vertical counter, 105
... Divide-by-2 circuit 106 horizontal decoder 107 conventional vertical decoder 108 composite decoder 109
... solid-state imaging device, 201 ... vertical counter of the present invention, 202
... Control circuit, 203, vertical counter, 204, vertical decoder of the present invention, 205, horizontal counter of the present invention, 206
2H decoder, 301... Five-stage shift register, 302.
... Six-stage shift register, 303... Seven-stage shift register, 304.

Continuation of the front page (56) References Japanese Utility Model Sho 62-86775 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/30-5/335 H04N 5/04-5 / 12

Claims (2)

(57) [Claims] 1. A horizontal counter for dividing the output of an oscillator to a horizontal synchronization frequency (fH), a first vertical counter receiving the output of the horizontal counter and operating at a horizontal synchronization frequency (fH), A second vertical counter operating at twice the frequency (2fH) of the first vertical counter, a control circuit for receiving the output of the first vertical counter, and stopping the second vertical counter for a period other than a vertical blanking period; First and second
And a vertical decoder for generating a synchronization signal for the solid-state imaging device from an output signal of the vertical counter. 2. The horizontal counter is constituted by a cyclic shift register, and a clock having a frequency twice as high as a horizontal synchronization frequency (2fH) is supplied to the second vertical counter via a decoder for decoding an output of the shift register. 2. The synchronization signal generation circuit for a solid-state imaging device according to claim 1, wherein the synchronization signal is provided.