JPH02113679A - Synchronizing signal generating circuit for solid state image pickup device - Google Patents
Synchronizing signal generating circuit for solid state image pickup deviceInfo
- Publication number
- JPH02113679A JPH02113679A JP63266540A JP26654088A JPH02113679A JP H02113679 A JPH02113679 A JP H02113679A JP 63266540 A JP63266540 A JP 63266540A JP 26654088 A JP26654088 A JP 26654088A JP H02113679 A JPH02113679 A JP H02113679A
- Authority
- JP
- Japan
- Prior art keywords
- horizontal
- vertical
- counter
- period
- frequencies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000007787 solid Substances 0.000 title 1
- 230000001360 synchronised effect Effects 0.000 claims abstract description 10
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 11
- 238000003384 imaging method Methods 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 125000004122 cyclic group Chemical group 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 239000002131 composite material Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Transforming Light Signals Into Electric Signals (AREA)
- Color Television Image Signal Generators (AREA)
- Synchronizing For Television (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は固体撮像装置の固体撮像素子を駆動する駆動回
路と同期信号発生回路とを単一集積回路とした集積回路
に関し、特に同期信号発生回路からの回り込みノイズに
より有効映像期間の中央付近に発生ずる縦線ノイズを低
減した固体撮像装置の同期信号発生回路に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an integrated circuit in which a driving circuit for driving a solid-state image sensor of a solid-state imaging device and a synchronization signal generation circuit are integrated into a single integrated circuit, and in particular, The present invention relates to a synchronization signal generation circuit for a solid-state imaging device that reduces vertical line noise generated near the center of an effective video period due to wrap-around noise from the circuit.
従来、この種の固体撮像装置の固体撮像素子を駆動する
駆動回路と同期信号発生回路とを単一回路とした集積回
路は、同期信号の規格上、第４図に示すように複合同期
信号は水平同期周波数の２倍（２ｆＨ）の成分を含むた
め、第５図に示すような構成をとるのが常である。すな
わち、発振器１０１の出力は固体撮像素子駆動信号を発
生し、また、発振器１０１の出力は水平カウンタ１０３
に入力され水平同期周波数の２倍（２ｆＨ）の成分を持
つ垂直デコーダ１０７の出力と水平デコーダ１０６の出
力をコンポジットデ′コーダ１０８で合成することによ
り、水平同期周波数の２倍（２，ｆＨ）の成分を含む複
合同期信号を発生させていた。Conventionally, integrated circuits in which the drive circuit for driving the solid-state image sensor of this type of solid-state imaging device and the synchronization signal generation circuit are integrated into a single circuit have a composite synchronization signal as shown in FIG. 4 due to the synchronization signal standard. Since it includes a component twice the horizontal synchronization frequency (2fH), a configuration as shown in FIG. 5 is usually adopted. That is, the output of the oscillator 101 generates a solid-state image sensor driving signal, and the output of the oscillator 101 generates a horizontal counter 103.
The composite decoder 108 combines the output of the vertical decoder 107 and the output of the horizontal decoder 106, which have a component twice the horizontal synchronizing frequency (2fH), which is input to the horizontal synchronizing frequency twice (2, fH). A composite synchronization signal containing the following components was generated.
上述した従来の固体撮像装置の固体撮像素子を駆動する
駆動回路と同期信号発生回路とを単一集積回路とした集
積回路の同期信号発生回路は、水平カウンタで発振器の
出力を水平同期周波数の２倍（２ｆ Ｈ）に分周し、こ
の２．ｆＨクロック（１によって垂直カウンタ１０４を
水平同期周波数の２倍（２ｆＨ）で動作させているため
第３図に示すように前記垂直カウンタ１０４のスイッチ
ングノイズが固体撮像装置駆動回路１０２に回り込み有
効映像期間の中火付近に縦線状ノイズとして現われると
いう欠点がある。The synchronization signal generation circuit of an integrated circuit in which the drive circuit for driving the solid-state image sensor of the conventional solid-state imaging device described above and the synchronization signal generation circuit are integrated into a single integrated circuit uses a horizontal counter to convert the output of the oscillator into two parts of the horizontal synchronization frequency. Divide the frequency by a factor of 2 (2f H). Since the vertical counter 104 is operated at twice the horizontal synchronization frequency (2fH) by the fH clock (1), as shown in FIG. The drawback is that it appears as vertical line noise near medium heat.
本発明の固体撮像装置の固体撮像素子を駆動する駆動回
路と同期信号発生回路とを単一集積回路とした集積回路
の同期信号発生回路は巡回型フォＩ・レジストで構成さ
れ少くとも水平同期周波数の２倍（２ｆＨ）のデコード
用出力を含み発振器の出力を水平同期周波数（ｆＨ）に
分周する水平カウンタと、水平同期周波数（ｆＨ）で動
作する垂直カウンタと前記水平カウンタの水平同期周波
数の２倍（２ｆＩ（）デコード用出力及び前記水平同期
の２倍（２，ｆＨ）で動作する垂直カウンタを垂直ブラ
ンキング期間以外の期間停止させる制御回路と、前記水
平同期周波数（ｆＨ）で動作する垂直カウンタと前記水
平同期周波数の２倍（２ｆＨ）で動作する垂直カウンタ
との出力信号から固体撮像装置用同期信号を発生ずる垂
直デコーダとを有している。The synchronization signal generation circuit of the integrated circuit in which the drive circuit for driving the solid-state image sensor and the synchronization signal generation circuit of the solid-state imaging device of the present invention are integrated into a single integrated circuit is constructed of a cyclic photo resist and has at least a horizontal synchronization frequency. A horizontal counter that includes a decoding output twice (2fH) and divides the output of the oscillator to a horizontal synchronous frequency (fH), a vertical counter that operates at the horizontal synchronous frequency (fH), and a horizontal synchronous frequency of the horizontal counter. a control circuit that stops a vertical counter that operates at double (2fI()) decoding output and twice the horizontal synchronization frequency (2, fH) for a period other than the vertical blanking period; and a control circuit that operates at the horizontal synchronization frequency (fH). It has a vertical counter and a vertical decoder that generates a synchronization signal for the solid-state imaging device from the output signal of the vertical counter that operates at twice the horizontal synchronization frequency (2fH).
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の構成図である。発振器］０
１の出力は、固体撮像素子駆動回路１０２に入力され固
体撮像素子駆動信号を発生し、固体撮像素子を駆動する
。また発振器１０１の出力は水平カウンタ２０５に入力
され水平同期周波数の２倍（２ｆＨ）の周波数を発生す
るとともに水平同期周波数（ＪＨ）に分周され、垂直カ
ウンタ２０１を動作させる。第２図は水平カウンタ２０
５の構成図で、−判型巡回型シフトレジスタで構成され
ており、必ず一つのフリップフロップに論理″１′″の
状態があり、他のフリップフロップは論理゛′０″′の
状態になっている。そのため回路全体では常に巡回型シ
フ１〜レジスタの一つの論理パ１′″がシフｌ−してい
るだげであるので、消費電力変動がなく同期性雑音の発
生がない。制御回路２０２は垂直カウンタ２０１の出力
により垂直ブランキング期間かどうかの情報を得て水平
同期周波数の２倍（２ｆＨ）の周波数と水平同期周波数
の２倍（２ｆＨ）で動作する垂直カウンタ２０３を垂直
ブランキング期間以外の期間停止させる。例えばＮＴＳ
Ｃ方式では第１フイールドは第２１ラインの初めから第
２６３ラインの途中まで、第２フイールドは第２８３ラ
インの途中から第５２５ラインの終りまでの期間止める
。垂直デコーダ２０４は垂直カウンタ２０１の水平同期
周波数（ｆＨ）の成分と垂直カウンタ２０３の水平同期
周波数の２倍（２ＪｌＪ）の成分とを合成することによ
り、水平同期周波数の２倍（２ｆＨ）の成分を出力に持
つことができるので垂直デコーダ２０４の出力と水平カ
ウンタ２０５の出力をコンポジットデコーダ１０８で合
成することにより水平同期周波数の２倍（２ｆＨ）の成
分を含む複合同期信号を発生することができる。このよ
うな垂直ブランキング期間以外の期間における水平同期
周波数の２倍（２ｆＨ）のクロック成分の発生の停止と
水平同期周波数の２倍（２ｆＨ）で動作する垂直カウン
タ２０３の停止は、有効走査期間の同期信号には水平同
期周波数の２倍（２ｆＨ）の成分の同期信号は存在しな
いため信号発生上全く支障は無い。FIG. 1 is a block diagram of an embodiment of the present invention. Oscillator] 0
The output of 1 is input to the solid-state image sensor driving circuit 102 to generate a solid-state image sensor drive signal and drive the solid-state image sensor. The output of the oscillator 101 is input to the horizontal counter 205 to generate a frequency twice the horizontal synchronization frequency (2fH), and is divided into the horizontal synchronization frequency (JH) to operate the vertical counter 201. Figure 2 shows the horizontal counter 20
5, it is composed of a - format cyclic shift register, and one flip-flop always has a logic ``1'' state, and the other flip-flops have a logic ``0'' state. Therefore, in the entire circuit, only the cyclic shift 1 to one logic register 1''' is shifted at all times, so there is no fluctuation in power consumption and no synchronous noise is generated. The control circuit 202 obtains information on whether it is a vertical blanking period from the output of the vertical counter 201, and controls the vertical counter 203, which operates at a frequency twice the horizontal synchronization frequency (2fH) and twice the horizontal synchronization frequency (2fH), to control the vertical blanking period. Stop for a period other than the blanking period. For example, NTS
In method C, the first field is stopped from the beginning of the 21st line to the middle of the 263rd line, and the second field is stopped from the middle of the 283rd line to the end of the 525th line. The vertical decoder 204 combines the horizontal synchronization frequency (fH) component of the vertical counter 201 and the component twice the horizontal synchronization frequency (2JlJ) of the vertical counter 203, thereby generating a component twice the horizontal synchronization frequency (2fH). By combining the output of the vertical decoder 204 and the output of the horizontal counter 205 with the composite decoder 108, it is possible to generate a composite synchronization signal containing a component twice the horizontal synchronization frequency (2fH). . Stopping the generation of the clock component at twice the horizontal synchronization frequency (2fH) and stopping the vertical counter 203 operating at twice the horizontal synchronization frequency (2fH) during periods other than the vertical blanking period are performed during the effective scanning period. Since there is no synchronization signal with a component twice the horizontal synchronization frequency (2fH), there is no problem in signal generation.
第６図は本発明の他の実施例を示すブロック図である。FIG. 6 is a block diagram showing another embodiment of the present invention.
第６図は第１図の実施例で示した巡回型シフトレジスタ
による垂直カウンタの他の構成方法による巡回型シフト
レジスタのブロック図である。FIG. 6 is a block diagram of a cyclic shift register using another method of configuring a vertical counter using the cyclic shift register shown in the embodiment of FIG.
本実施例しこおける垂直カウンタは、それぞれ互に公約
数をもたない異なる段数の復数の巡回型シフト１／ジス
タと、一致回路とから構成されている。The vertical counter in this embodiment is composed of a plurality of cyclic shift 1/registers each having a different number of stages, each having no common divisor, and a matching circuit.
３０１，３０２，３０３はそれぞれ５段、６段。301, 302, and 303 have 5 and 6 stages, respectively.
７段のシフトレジスタであり、各シフトレジスタの出力
は一致回路３０４に接続されている。発振器からの出力
は各シフトレジスタにクロックトシて入力されている。It is a seven-stage shift register, and the output of each shift register is connected to a matching circuit 304. The output from the oscillator is clocked and input to each shift register.
この構成の巡回型シフトレジスタは各巡回型シフトレジ
スタ３０１，３０２゜３０３のそれぞれの出力が一致し
、一致回路３０４の出力によって各シフトレジスタがリ
セットされるクロック数の巡回型シフ）・レジスタを構
成することになる。The cyclic shift register with this configuration constitutes a cyclic shift register with a clock count in which the outputs of the cyclic shift registers 301, 302 and 303 match, and each shift register is reset by the output of the matching circuit 304. I will do it.
この構成の巡回型シフトレジスタは、−判型の巡回型シ
フトレジスタに対して非常に少ない段数のシフトレジス
タで構成出来るのが特徴で、基本的にはリセットタイミ
ングでの消費電力変動以外は一列巡回型と同様に消費電
力変動が無いために、水平同期周波数ｆＨ周期以外の分
周雑音が発生しない特徴を合せもつ。この第６図に示す
シフトレジスタから得られる水平同期周波数ｆＨ及び２
倍の２．ｆＨデコード用出力はそれぞれ２つの垂直カウ
ンタに印加され、第一の実施例と同様な動作１７、有効
映像期間の中央付近の縦線状ノイズの発生を防止出来る
同期信号発生回路が構成出来る。A cyclic shift register with this configuration has a feature that it can be configured with a much smaller number of stages than a - format cyclic shift register, and basically it cycles in one row except for power consumption fluctuations at reset timing. Similar to the type, there is no power consumption fluctuation, so it also has the characteristic that frequency division noise other than the horizontal synchronization frequency fH cycle does not occur. The horizontal synchronization frequency fH and 2 obtained from the shift register shown in FIG.
Double 2. The fH decoding outputs are applied to two vertical counters, respectively, and a synchronization signal generation circuit can be constructed that operates similarly to the first embodiment and can prevent the occurrence of vertical line noise near the center of the effective video period.
以上説明したように、本発明は、有効映像期間には縦線
の原因となる水平同期周波数の２倍（２、ｆＨ）の成分
の発生及びこの水平同期周波数の２倍（２ｆＨ）で動作
するカウンタを停止することにより、従来の同期信号発
生回路では避けることのてきなかった水平同期周波数の
２倍（２ｆＨ）成分による画面中央部に生じる縦線状固
定パターンノイズを無くすことができる効果がある。As explained above, the present invention generates a component twice the horizontal synchronization frequency (2, fH) that causes vertical lines during the effective video period, and operates at twice the horizontal synchronization frequency (2fH). By stopping the counter, it is possible to eliminate the vertical line-shaped fixed pattern noise that occurs in the center of the screen due to the twice the horizontal synchronization frequency (2fH) component, which could not be avoided with conventional synchronization signal generation circuits. .
第１図は、本発明の一実施例の構成を示すブロック図、
第２図は水平カウンタ２０５の構成を示すブロック図、
第３図は有効映像期間の中央付近に発生する縦線状ノイ
ズの説明する図、第４図は水平同期周波数の２倍（２，
ｆＨ）の成分を持つ複合同期信号の説明する図、第５図
は従来技術の構成を示すブロック図、第６図は本発明の
他の実施例に用いる巡回型シフトレジスタのブロック図
である。
１０１・・・発振器、１０２・・・・・固体撮像素子駆
動回路、１０３・・・・・水平カウンタ、１０４・・・
・・・従来技術の垂直カウンタ、１０５・・・・・２分
周回路、１０６・・・・・水平デコーダ、１０７・・・
・・・従来技術の垂直デコーダ、］、 ０８・・・・・
コンポジットデコーダ、１０９・・・・・固体撮像素子
、２０１・・・・・本発明の垂直カウンタ、２０２・・
・・制御回路、２０３・・・・・・垂直カウンタ、２０
４ ・・・本発明の垂直デコーダ、２０５・・・・本発
明の水平カウンタ、２０６・・・・・・２ｆＨデコータ
、３０１・・・・・５段のシフトレジスタ、３０２・・
・・６段のシフトレジスタ、３０３・・・・・・７段の
シフトレジスタ、３０４・・・・・一致回路。
代理人 弁理士 内 原 晋FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention;
FIG. 2 is a block diagram showing the configuration of the horizontal counter 205,
Figure 3 is a diagram explaining the vertical line noise that occurs near the center of the effective video period, and Figure 4 is a diagram that explains the vertical line noise that occurs near the center of the effective video period.
FIG. 5 is a block diagram showing the configuration of a conventional technique, and FIG. 6 is a block diagram of a cyclic shift register used in another embodiment of the present invention. 101... Oscillator, 102... Solid-state image sensor drive circuit, 103... Horizontal counter, 104...
... Vertical counter of conventional technology, 105 ... 2 frequency divider circuit, 106 ... Horizontal decoder, 107 ...
...Prior art vertical decoder, ], 08...
Composite decoder, 109... Solid-state image sensor, 201... Vertical counter of the present invention, 202...
...Control circuit, 203...Vertical counter, 20
4... Vertical decoder of the present invention, 205... Horizontal counter of the present invention, 206... 2fH decoder, 301... 5-stage shift register, 302...
...6-stage shift register, 303...7-stage shift register, 304...matching circuit. Agent Patent Attorney Susumu Uchihara
Claims (1)
波数の２倍（２ｆＨ）のデコード用出力を含み、発振器
の出力を水平同期周波数（ｆＨ）に分周する水平カウン
タと、水平同期周波数（ｆＨ）で動作する垂直カウンタ
と、前記水平カウンタの水平同期周波数の２倍（２ｆＨ
）デコード用出力及び前記水平同期周波数の２倍（２ｆ
Ｈ）で動作する垂直カウンタを垂直ブランキング期間以
外の期間停止させる制御回路と、前記水平同期周波数（
ｆＨ）で動作する垂直カウンタと、前記水平同期周波数
の２倍（２ｆＨ）で動作する垂直カウンタとの出力信号
から固体撮像装置用同期信号を発生する垂直デコーダと
を有することを特徴とする固体撮像装置用同期信号発生
回路。A horizontal counter consisting of a recursive photoresist, including a decoding output of at least twice the horizontal synchronization frequency (2fH), and dividing the output of the oscillator to the horizontal synchronization frequency (fH); a vertical counter that operates at 2 fH, and a vertical counter that operates at
) decoding output and twice the horizontal synchronization frequency (2f
A control circuit that stops a vertical counter operating at the horizontal synchronization frequency (H) for a period other than the vertical blanking period;
a vertical counter that operates at twice the horizontal synchronization frequency (2fH); and a vertical decoder that generates a synchronization signal for a solid-state imaging device from an output signal of the vertical counter that operates at twice the horizontal synchronization frequency (2fH). Synchronous signal generation circuit for equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63266540A JP2758615B2 (en) | 1988-10-21 | 1988-10-21 | Synchronous signal generation circuit for solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63266540A JP2758615B2 (en) | 1988-10-21 | 1988-10-21 | Synchronous signal generation circuit for solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02113679A true JPH02113679A (en) | 1990-04-25 |
| JP2758615B2 JP2758615B2 (en) | 1998-05-28 |
Family
ID=17432282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63266540A Expired - Lifetime JP2758615B2 (en) | 1988-10-21 | 1988-10-21 | Synchronous signal generation circuit for solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2758615B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006035843A1 (en) * | 2004-09-30 | 2006-04-06 | Sharp Kabushiki Kaisha | Timing signal generating circuit, electronic device, display device, image receiving device and driving method |
-
1988
- 1988-10-21 JP JP63266540A patent/JP2758615B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006035843A1 (en) * | 2004-09-30 | 2006-04-06 | Sharp Kabushiki Kaisha | Timing signal generating circuit, electronic device, display device, image receiving device and driving method |
| JPWO2006035843A1 (en) * | 2004-09-30 | 2008-05-15 | シャープ株式会社 | Timing signal generating circuit, electronic device, display device, image receiving device, and driving method |
| JP4668202B2 (en) * | 2004-09-30 | 2011-04-13 | シャープ株式会社 | Timing signal generation circuit, electronic device, display device, image receiving device, and electronic device driving method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2758615B2 (en) | 1998-05-28 |
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