JPS60227570A - Pulse generating circuit for driving solid-state image pickup element - Google Patents

Abstract

PURPOSE:To put a TV camera with high resolution into practice by applying 2/3 frequency division to the output signal of an original oscillator and obtaining a horizontal/vertical synchronizing signal to obtain various drive pulses from a timing pulse generator circuit thereby saving power. CONSTITUTION:A signal of stable frequency 6fSC (fSC is a subcarrier frequency) of the original oscillator is divided into 4fSC by a 2/3 frequency divider circuit 15, this signal is led to a synchronizing signal generating circuit 8 so as to generate various synchronizing signals to an output terminal 9. Further, the horizontal/vertical synchronizing signals HD, VD from the circuit 8 are fed to a timing pulse generating circuit 16. The circuit 16 outputs (17) each drive pulse of a solid-state image pickup element in synchronizing with the HD, VD by using a signal frequency-dividing the 6fSC signal of an original oscillator 14 in synchronizing with the HD, VD. On the other hand, the 6fSC signal of the oscillator 16 is frequency-divied into a half frequency in the timing pulse in synchronizing with the HD, VD signal from the circuit 16 by a 1/2 frequency division circuit 18, and a 3fSC horizontal transfer pulse and a horizontal output reset pulse in synchronizing with the HD, VD are outputted (19).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a drive pulse generation circuit that generates drive pulses for a solid-state image sensor.

Configuration of a conventional example and its problems The present invention relates to a solid-state image sensor drive pulse generation circuit, and first, a general outline of a solid-state image sensor will be explained using FIG. 1. However, FIG. 1 is only a configuration diagram for understanding the solid-state image sensor, and the present invention is applicable to any other type of solid-state image sensor in which the frequency of the driving pulse for horizontal transfer is the same. If so, it can be applied to that drive pulse generation circuit.

Figure 1 shows an interline transformer 77 type C0D (hereinafter referred to as IL-CO), which is generally known as a solid-state image sensor.
(abbreviated as D), in which 1 is a semiconductor substrate, 2a and 2b are a large number of light receiving parts arranged in a matrix on this semiconductor substrate 1, and 3 is a light receiving part in the horizontal scanning direction. Vertical transfer shift registers 4 extending in the vertical direction are provided in the same number as 2a and 2b, that is, the number of horizontal pixels;
5a and 5b are transfer gates for transferring the charges in the light receiving sections 2a and 2b to the vertical transfer shift register 3. The vertical transfer register 3 has φ■1 shown in FIG.
A pulse having a period of one horizontal scanning period (hereinafter referred to as 1H period) such as φv2 is applied, and in the 1H period, charges for one stage of the vertical shift register 3 are transferred, and one stage is transferred to the horizontal transfer shift register 4. Transfers charges for a horizontal line. Then, in the horizontal transfer shift register 4, φH to φH shown in FIG.
4 horizontal transfer pulse, and the horizontal output section has the φ
A horizontal output unit reset pulse R is applied to output the charges of pixels of one horizontal line in 1H period. Note that the frequency of the horizontal transfer driving pulses of φH1 to φH4 and φR described above is determined by the number of light receiving sections arranged in one horizontal line, and for example, in the case of 384, it is approximately 7.
Total of 2.

As described above, the solid-state image sensing device to which the present invention is directed is based on the operating principle as described above.

FIG. 3 shows that the frequency of the driving pulse (horizontal transfer pulse) of the horizontal transfer shift register as a solid-state image sensor is the frequency f SC (= s ,
A solid-state image sensor requires a frequency (3fsc) three times that of 6s h (therefore, its effective horizontal pixel count is approximately 570).
The number of strokes. ) is a conventional example of a solid-state image sensing device drive pulse generation circuit.

The source oscillator 6 outputs a stable signal with a frequency of 12 fsc. This 12fsc signal is converted to 'fS' by the % frequency divider circuit 7.
The synchronizing signal generating circuit 8 generates a horizontal synchronizing signal HD, a vertical synchronizing signal VD, a subcarrier SC, and other various synchronizing signals (for example, composite) SYNC, BLK signal, etc.) is generated and taken out from the output terminal 9. Also, HD, V
D is guided to a timing pulse generation circuit 1o. The timing pulse generation circuit 10 converts the output signal of the original oscillator 6 into HD.
.

The output terminal 11 outputs various drive pulses (pulses other than horizontal transfer pulses and horizontal output unit reset pulses) for the solid-state image sensor synchronized with HD and VD by dividing the frequency in synchronization with VD.
get to. On the other hand, the 12fsc signal is sent to the Z frequency divider circuit 12,
HD, V obtained by the timing pulse generation circuit 1o
The horizontal transfer pulse of 3fSC and the horizontal output section reset pulse synchronized with HD and VD are divided into the Z frequency in synchronization with the timing pulse synchronized with the D signal, and are output to output terminal 1.
Output from 3.

As described above, conventional drive pulse generation circuits for solid-state image sensors, which have approximately 570 horizontal effective pixels and require a horizontal transfer pulse frequency of 3 fsc, have a frequency of 4 fsc as input signals to the synchronization signal generation circuit. Pulses are required and the frequency dividing circuit is 1/n (n: positive integer)
Since there is no simple frequency dividing circuit other than the frequency dividing circuit, 3fsc
It was necessary to generate and use a signal with a frequency of 12fsc, which is the least common multiple of 4fsc and 4fsc, using the original oscillator. However, the frequency of 12fsc is 42.95454 MIl! (
(In the case of NTSC system), this is a very high frequency, which saves power.

This has been a major obstacle in terms of the stability of IC implementation.

purpose of invention The present invention eliminates the above-mentioned drawbacks and saves power.

It is an object of the present invention to provide a drive pulse generation circuit for a solid-state image sensor that can be easily integrated into an IC.

Structure of the Invention The present invention comprises an original oscillator, a % frequency dividing circuit that divides the output signal of the original oscillator by %, and a synchronous signal generator that obtains horizontal and vertical synchronizing signals from the output signal of the % frequency dividing circuit. , a solid-state imaging device driving pulse generation circuit including a circuit for obtaining a solid-state imaging device driving pulse from the output signal of the synchronizing signal generator and the output signal of the original oscillator.

Description of examples Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 4 shows an example of the basic configuration of the present invention, and the same parts as in the conventional example shown in FIG. The source oscillator 14 outputs a signal with a stable frequency of 6 fsc.

Then, this 6fsc signal is divided into a frequency of % by the % frequency divider circuit 16, and is made into a signal with a frequency of 4fsc.
The fsc signal is guided to a synchronizing signal generating circuit 8, and as in the conventional example, various synchronizing signals are outputted to its output terminal 9. Further, HD and VD from the synchronization signal generation circuit 8 are guided to a timing pulse generation circuit 16. Then, the timing pulse generation circuit 16 converts the output signal 6fsc of the original oscillator 14 into HD
, a signal frequency-divided in synchronization with VD or a signal delayed by 6fsc or its frequency division signal using a shift register or the like is used to generate various drive pulses for the solid-state image sensor in synchronization with HD and VD. (pulses other than the horizontal transfer pulse and the horizontal output section reset pulse) are obtained at the output terminal 17. On the other hand, the 6fsc signal output from the original vibration damper 14 is passed through the frequency division circuit 18 and the timing pulse generation circuit 16.
The horizontal transfer pulse and the horizontal output section reset pulse with a frequency of 3 fSC, which are synchronized with the HD and VD signals, are divided into a frequency of 3 fSC in synchronization with the timing pulses that are synchronized with the HD and VD signals that are obtained from the output terminal 19. It will be outputted.

Next, the % frequency divider circuit will be explained.

5.7, 9, 11.13 are specific circuit examples of the % frequency divider circuit of FIG. 4, and 6., 8., 10.12.14 are waveform diagrams for explaining its operation.

Specific circuit examples of each side will be explained below.

FIG. 5 is a diagram showing a first embodiment of the % frequency divider circuit,
The operation will be explained with reference to the waveform diagram shown in FIG.

In FIG. 6, numeral 21 is an input terminal to which a pulse with a duty ratio of approximately 1:1 as shown in FIG. 6a is applied. 22 is a general % frequency divider circuit, which divides the frequency of the applied pulse to produce a pulse with a ratio of high level period to low level period of 2:1 as shown in Figure 6. Output. This pulse is transmitted to the shift register SR in Fig. 5.
Triggered by the positive leading edge of the input pulse (a) being applied to the data (D) terminal of 1 and the clock (CK) terminal, the output terminal (Q) of FIG.
The signal waveform shown in is obtained. This signal waveform is applied to the data terminal (D) of shift register SR2 in FIG. 5, triggered by the negative leading edge of the input pulse (a) applied to the clock (OK) terminal, and output terminal ( Q), a signal waveform as shown in FIG. 6d is obtained. Then, the output of the % frequency dividing circuit 22 (FIG. 6b) and the output of the shift register SR2 (FIG. 6d) are as shown in FIG.
The logical product is taken by the AND circuit, and the output terminal 24
An output pulse as shown in FIG. 6e is obtained. This output pulse is equal to 3 of the input pulses applied to the input terminal 21.
There are two periods of pulses in a period (for example, the period from t2 to t8 in FIG. 6), and the circuit shown in FIG. 6 constitutes a % frequency divider circuit.

FIG. 7 is a diagram showing a second embodiment of the % frequency dividing circuit, and the difference from FIG. 6 is that the duty ratio of the output waveform of the % frequency dividing circuit (the difference between the high level period and the low level period) is The ratio) is 1:2. The operation will be explained using the waveform diagram in FIG. The input pulse shown in FIG. 8a applied to the input terminal 21 is frequency-divided by the Z frequency dividing circuit 25 to obtain a pulse waveform as shown in FIG. Similar to the first embodiment shown in FIG. 6, this pulse waveform is delayed in SR1 and SR2 using the positive and negative leading edges of the input pulse (waveform in FIG. 8a) as clocks. The pulse shown in FIG. 8d is obtained as the output of shift register SR2. The output pulse of this SR2 (Fig. 8 d) and the output pulse of the % frequency divider circuit (Fig. 8 b) are ORed in the ○R circuit of Fig. 7, and the 8 An output pulse is obtained by dividing the frequency of the input pulse by % as shown in Figure e.

In other words, the output pulse obtained at terminal 27 is
3 periods of input pulse applied to 1 (e.g., t
12 to t18), there are two periods of pulses, and the circuit shown in FIG. 7 also constitutes a % frequency divider circuit.

Note that the Z frequency divider circuit shown in the above embodiment is a general % frequency divider circuit and is described in many documents related to digital circuits, so a detailed explanation thereof will be omitted.

FIG. 9 is a diagram showing another embodiment of the % frequency divider circuit, and the difference from the embodiments shown in FIGS. 5 and 7 is that the shift register SR1 in FIGS. It is also used as a flip-flop to simplify the configuration.

The input pulse shown in FIG. 10a applied to input terminal 21 causes flip-flops FF1. and FF2 and NAND circuit 28
% frequency divider circuit (Naoto's % frequency divider circuit is a well-known circuit, so a detailed explanation of its operation will be omitted), and the frequency is divided to a frequency of %, and the frequency is divided to a frequency of % by a % frequency divider circuit (Naoto's % frequency divider circuit is a well-known circuit, so a detailed explanation of its operation will be omitted). and the output terminal (Q) of flip-flop FF2 are shown in FIG. 10, respectively.

A pulse as shown in C is obtained. The output waveform of FF2 (FIG. 10C) is pulse-delayed by a shift register SR2 whose clock is the negative leading edge of the input pulse (FIG. 10a), and the pulse shown in FIG. 10E is output from SR2. obtained at the output terminal. Then, the output pulse of FF1 (Fig. 10b) and the output pulse of SR2 (10th
In Figure e), the AND circuit 23 calculates the logical product sum, and the output terminal 24 receives an output pulse in which the frequency of the input pulse is divided into % as shown in Figure 10. A % frequency divider circuit can be constructed with the simple circuit shown below.

FIG. 11 is a diagram showing a fourth embodiment of the % frequency divider circuit, and its operation will be explained using the waveform diagram shown in FIG. 12.

In FIG. 11, numeral 21 is an input terminal to which a pulse with a duty ratio of 1:1 as shown in FIG. 12a is applied. 28 is a % frequency divider circuit which divides the frequency of the applied pulse into % and outputs a pulse with a ratio of high level period to low level period of 1:2 as shown in Figure 12. be done. This pulse is then applied to the data terminal (D) of shift register SR3, delayed by one period of the input pulse (waveform a in Figure 12) applied to the clock terminal (OK), and then A pulse as shown in FIG. 12C is output to the output terminal (Q). Then, the pulse obtained by inverting the input pulse (Fig. 12a) by the inverter 29 and the output pulse of SR3 (12th
Figure C) is obtained by the AND circuit 30 and the 12th
The pulse shown in Figure e is obtained. On the other hand, the output pulse (FIG. 12b) of the frequency dividing circuit and the input pulse (FIG. 12a) are added to the AND circuit 31 to obtain a pulse as shown in FIG. 12D. And AND circuit 30.31
By obtaining the logical sum of the output pulses in the OR circuit 32,
At its output terminal 33, a pulse shown in FIG. 12f is obtained. This output pulse has two periods of pulses in the three periods of the input pulse applied to the input terminal 21 (for example, the period from t3 to t9 in FIG. 12), and the circuit shown in FIG. 11 is simple. Moreover, it constitutes an all-digital % frequency divider circuit.

FIG. 13 is a diagram showing a sixth embodiment of the % frequency dividing circuit, and the difference from FIG. 11 is that the shift register SR3 in FIG. 11 is also used as a flip-flop constituting the % frequency dividing circuit. The configuration has been simplified.

The input pulse shown in FIG. 14a applied to the input terminal 21 is applied to a well-known circuit consisting of flip-flops FFs and FF4 and a NOR circuit 34, which is triggered by the positive leading edge of the pulse applied to the clock terminal OK. % frequency divider circuit (this % frequency divider circuit is a well-known circuit, so the explanation of its operation will be omitted), and the frequency is divided to % frequency, and the frequency is divided to the flip-flop FF3. A pulse as shown in FIG. 14c is obtained at each output terminal of the FF4.

Then, the AND circuit 30 obtains the AND of the input pulse (Fig. 14a) inverted by the inverter 29 and the output pulse of the flip-flop FF4 (Fig. 14C), and the pulse shown in Fig. 14f is obtained. It will be done. On the other hand, the AND circuit 31 obtains the logical product of the output pulse of the flip-flop FF3 (FIG. 14b) and the input pulse (FIG. 14a) to obtain the pulse shown in FIG. 14E. And ○R circuit 3
2, the logical sum of the output pulses of the AND circuits 30 and 31 is obtained, and an output pulse as shown in FIG. 14q is obtained at the output terminal 33. This output pulse is generated during three cycles of the input pulse applied to the input terminal 21 (for example, from t13 to t13 in FIG. 14).
t19 period), there are two periods of pulses, and the 13th
The circuit shown in the figure constitutes an all-digital % frequency dividing circuit with a very simple configuration.

Effects of the Invention As described above, according to the present invention, by employing a % frequency dividing circuit, the original oscillator can be used as a drive pulse generation circuit for a solid-state image sensor that requires a signal with a frequency of 3 fsc as a horizontal transfer pulse. The oscillation frequency of 6fsc (=21.4
7727IIIZ) and the conventional 12f Bc (-42,
96464Wh), it is possible to obtain a stable solid-state image pickup device driving pulse generation circuit suitable for power saving and IC implementation, and greatly contributes to the practical application of high-resolution television cameras.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing the general configuration of a solid-state image sensor, Fig. 2 is a signal waveform diagram showing an example of driving pulses for the solid-state image sensor, and Fig. 3 is a schematic diagram showing the general configuration of a solid-state image sensor.
The figure is a block diagram showing a conventional example of a solid-state image sensor driving pulse generation circuit that outputs a pulse with a frequency of 3 fsc as a horizontal transfer pulse. FIG. FIG. 5 is a block diagram showing the configuration. 7, 9, 11, and 13 are circuit diagrams showing various specific circuit examples of the % frequency divider circuit used in the same embodiment, and
Fig. 8, Fig. 10, Fig. 12. FIG. 14 is a waveform diagram for explaining the operation. 8...Synchronization signal generation circuit, 14...Original oscillator, 15...% frequency division circuit, 16...timing pulse generation circuit, 18...% frequency division circuit. Name of agent Patent attorney Toshio Nakao and 1 other person Figure 2 Figure 3 Figure 7 β Figure 5 2 2/ / Figure 6 Figure 7-5 SRt 5Fz 38 Figure 9 Figure 10. Figure 11 Figure 2ρ 1 Figure 12

Claims (4)

[Claims] (1) An original oscillator, a % frequency dividing circuit that divides the output signal of the original oscillator by %, a synchronous signal generator that obtains horizontal and vertical synchronizing signals from the output signals of the % frequency dividing circuit, and this synchronization A solid-state imaging device drive pulse generation circuit comprising: a circuit that generates a solid-state imaging device driving pulse based on an output signal of a signal generator and an output signal of the original oscillator. (2) The oscillation frequency of the original oscillator is 6 times the subcarrier frequency (fSC) in the standard color television system, and the frequency of the drive pulse for the horizontal transfer shift register among the solid-state image sensor drive pulses is 3fSC. A solid-state image sensor driving pulse generation circuit according to claim 1. (3) The % frequency divider circuit divides the input pulse with a duty of approximately 1:1 into pulses with a frequency of % and a ratio of high level period to low level period of 2:1 or 1:2. a frequency divider circuit, and the output of this Z frequency divider circuit is set to one of the input pulses at either the positive or negative leading edge of the input pulse.
a first shift register that shifts by a clock amount;
a second shift register that shifts the output of the first shift register by one clock of the input pulse with a leading edge of opposite polarity to that of the first shift register; Logical product or logic image element drive pulse generation circuit with the output of the Z frequency divider circuit. (4) The % frequency divider circuit divides an input pulse with a duty of 1:1 into pulses with a frequency of % and a ratio of high level period to low level period of 1:2; a shift register that delays the output of the % frequency divider circuit by one period of the input pulse; a first AND circuit that obtains a logical product of the output of the shift register and a pulse obtained by inverting the input pulse; a second AND circuit that obtains a logical product between the output of the Z frequency divider circuit and the input pulse; Second
A solid-state image sensor driving pulse generation circuit according to claim 1 or claim 2, characterized in that the circuit is configured with an OR circuit that obtains the logical sum of the outputs of the AND circuits.