JPS59156077A - Generating circuit of television synchronizing signal - Google Patents

Abstract

PURPOSE:To eliminate up of a picture due to the mixing of a signal without causing the increase of cost and power consumption by providing a ring counter that makes one round at the frequency of odd number times of half of the horizontal scanning frequency of a television and a logical circuit that combines signals outputted from each part of the ring counter generate the reference signal of a horizontal synchronizing signal. CONSTITUTION:The waveform outputted by the ring counter output 53 rises up to ''1'' and at the 3rd clock falls down to ''0'' at the 38th clock. Similarly, the waveform outputted by the ring counter output 34 rises up at the 33th clock and falls down at the 68th clock. The two waveforms 3Q, 33Q is ANDed. A 13 times counter 35 is connected to the Q output of first step flip flop of the ring counter and count the risie, and controls which one is to be outputted out of the pulses made by the ring counter output waveforms 3Q, 33Q. A 13 times counter is used for the counter 35 because the ring counter makes 13 times of round to make the succeeding horizontal scanning and phase coincide.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a circuit that generates a television synchronization signal necessary for driving a television, a television camera, a video tape recorder, and the like.

[Technical background of the invention and its problems]

The circuit that generates the television synchronization signal is NT8.
Taking the case of the C system as an example, the subcarrier frequency (
This is generally done by directly dividing the frequency of a signal oscillated by an oscillator (14,31818 MHz) using a counter. An example of this is shown in FIG.

Multiple signals with four times the subcarrier frequency are input to the terminal circle, one of which is input to the l/4 frequency division counter (12) and output to the terminal (131) as an input subtransmission signal.The other is output to the terminal (131).
It enters the frequency division counter and becomes the reference signal for creating vertical and horizontal synchronization signals. This 1/7 frequency division reference signal is further divided into 1/65 frequency division counter (15i, which is twice the horizontal scanning frequency, 9, and is divided into three parts. One is the V525 frequency division counter. (At 1η, it becomes a signal with a vertical scanning frequency of υ.

The other one is divided by V2 by the 17i2 frequency division counter (L6) to become a horizontal scanning frequency signal, which is input to the horizontal decoder (1) along with the third output of the 1/65 frequency division counter (IQ), and the horizontal synchronization signal , a horizontal scanning period signal such as a horizontal deflection pulse, a clamp pulse, etc. is generated, and a terminal group (112)
is output to.

One of the outputs of the 17525 frequency division counter α7) is sent to the vertical decoder (111) together with the other output of the V2 frequency division counter (input to 18, no signal with l frame period, V525 frequency division counter). is input. This vertical decoder (111) generates vertically related pulses such as a vertical synchronization pulse, a vertical deflection pulse, and a field index, and outputs them to a terminal group (114). Mixed decoder (
110) is a horizontal decoder U and a vertical decoder U:! -ta(1
11), generates pulses such as composite sync, composite blank, burst fluff, etc.
Output to the terminal group (113).

The above is an example of a commonly used television synchronization signal generation circuit, but this circuit configuration may cause some inconvenience. For example, when this synchronization signal generation circuit drives a television camera using a solid-state image sensor, ]/7
The output signal of the frequency division counter a◇ may jump onto the screen, significantly deteriorating the image. This V7 frequency divider circuit (14)
The output signal frequency is approximately 2MH2, which is exactly 130 times the horizontal scanning frequency, so this signal mixes with the drive pulse of the solid-state image sensor, and this frequency component appears in the output signal, causing vertical stripes on the playback screen. It appears as.

As a means to prevent this, a method as shown in FIG. 2 was announced in a paper at the 1982 National Conference of the Television Society, pages 91 to 92 r4-5J. This is within the dotted line of the example in Figure 1 (the U-shaped circuit consists of 45
It is composed of multiple 5-bit ring counters.

A single pulse is input from the terminal 0υ only when the power is turned on, and is sequentially shifted in the ring counter @ by the transfer lock applied to the terminal (27I).

The frequency of the transfer lock applied to the terminal @ is 7.159
A pulse of 09MH2 is used to drive a 9455-stage ring counter with one horizontal scanning frequency, and the pulse is generated once. Therefore, signals of ``1'' appear in sequence at each output terminal Q1 to Q455 of the flip-flop, thereby making it possible to generate a synchronization signal with an arbitrary horizontal relationship.

If you do the above, you will get 14.3181 as in the example in Figure 1.
A horizontal synchronizing signal can be created without using any signals within the video band, such as the 8 h V7 frequency divided signal, and image deterioration due to signal mixing does not occur. However, in this case, it is safe to use 455 7-lip flops to form a 455-stage ring counter, but the circuit size is large, cost is high, and
This is disadvantageous in terms of power consumption.

Note that when a 455-stage ring counter is used, the vertically related synchronization signal is generated by counting 262 signals of one horizontal scanning period and delaying this by 1/2 horizontal scanning time.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a television synchronization signal generation circuit that does not cause image deterioration due to signal contamination, and does not increase cost or power consumption due to increase in circuit scale. purpose. [Summary of the Invention] The present invention provides a ring counter that scans once at a frequency that is an odd multiple of half the horizontal scanning frequency of a television, and a horizontal synchronization system that combines the signals output from each part of this ring counter. 1. A television synchronization signal generation circuit characterized by comprising a logic circuit that generates a signal serving as a reference signal.

〔Effect of the invention〕

According to the present invention, even if noise occurs in the synchronization signal generation circuit, the frequency of the ring counter used in the present invention is low, so that it is less likely to mix into the video signal and affect it.
Moreover, even if it is given, the phase will be reversed between lines, so it will not be visually noticeable. Further, according to the present invention, the number of circuit elements such as flip-flops constituting the ring counter is small, the circuit scale can be significantly reduced by He, and power consumption can be achieved by the reduction in the number of circuit elements.

[Embodiments of the invention]

Next, one embodiment of the present invention will be described using FIG. This is a ring counter that combines 135 D-type flip flora. Except for the first-stage flip-flop, the D outputs of each of the seven flip-flops are connected to the Q output of the previous stage. The D input of the first stage flip-flop is connected to the Q output of the 35th stage.

When the circuit is powered on, all the flip-flops are cleared by the reset generation circuit (313), and immediately after that, 11" is inputted to the first stage flip-flop from the Q output of this flip-flop with the role of 35. The counter starts working.

The clock input from the terminal (32) is 7.15909 MHz, which is twice the subcarrier frequency.When the shilling counter is released from the reset at power-on, the first clock causes the first stage's '1' is input to the flop, and at the 35th clock, this 11' reaches the 35th stage flip-flop and the Q output becomes '0'. Therefore, at the 36th clock, the first stage flip-flop is reaches the 35th stage when '0' is entered and the 970th shot, and the ring counter has completed one rotation. Therefore, the repeating frequency of the ring counter is 102273KH2, which is 65 times the horizontal scanning frequency.

Next, how to create a pulse with an arbitrary phase and pulse width will be explained. Taking the Q output (to) of the 3rd stage of the ring counter and the Q output of the 33rd stage as an example, the ring counter output H
), (goods) waveforms are 3Q shown in Figure 4 (a) and (b),
Strength like 33Q. That is, the ring counter output (
c) The output waveform rises to '1' at the 3rd clock and falls to '0' at the 38th clock.

Similarly, the waveform output from the ring counter output rises at the 33rd clock and falls at the 9.68th clock. For example, when these two waveforms 3Q and 33Q are ANDed, the waveform diagram (44) shown in FIG. 4(c) is obtained.

By doing as described above, any pulse can be generated, but if left as is, the pulse will be output many times during one horizontal scanning time. This is controlled by 13x Kaunk C3.
It is 51. This is connected to the ring counter output & Q output of the flip-flop and counts its rising edge. And ring counter output waveform 3Q
, 33Q controls which one of the pulses generated by the pulses is output. That is, for example, only when the 13x counter t3'jn is the 1st time υ of the ring counter'
1", the pulse shown in the waveform (41) is outputted only once in two horizontal scanning periods.

The reason why the counter Sω is set as a 13 times counter is that the ring counter starts and the next time the phase matches the horizontal scanning is when the ring counter has counted 13 times. However, if this continues, one pulse must be generated every two horizontal scanning periods, and a pulse must be generated even during horizontal constant distortion when no signal is output. This is expressed by the 13x counter G force, AND game) (310),
It is an OR gate (311).

Status 1 after one horizontal period has elapsed since the ring counter started
g is when the ring counter has completed 6.5 turns, and each output terminal is in exactly the opposite state as at the start. That is, '0'' is input from the 7 lip flops in the first stage,
'1'' is input again at the 36th pulse.This is
Regarding the Q terminal of the name-flip-flop that forms the ring counter, it is in the same state as when the counting counter started, and the Qa3 force side of the 3rd stage of the 1-long counter gauze and the 33rd stage ◇ From now on, each figure 4 3Q
, the same wave as 33Q can be obtained. As before, do this 1
Only υ one pulse is selected by the triple counter G force.

The 13x counter (37) counts the rise of the Q output of the first stage of the ring counter (B), and the 13x counter (to) and υ also start with a delay of 1/2 rotation of the ring counter. This 13x counter (3D) is ``1'' between the 6th and 5th times of the ring counter and the 11.5th time.
(If you make the circuit so that the i is output, it will be a game). From (310), the pulse of the same waveform as that which is output from the AND gate (audience) is hard. output during horizontal scanning. Therefore, AND game) (3(n
, OR the output of the AND gate (310)) (31
In addition to 1), the same pulse is output to terminal (312) for each horizontal scan. In this way, a signal that serves as a reference for the horizontal synchronization signal is created. Since the two 13 times counters (05) must be reset at the same time in synchronization with the ring counter, the reset generation circuit (313) is used to reset the counters when the power is turned on.

In the above example, one round of the ring counter is 9778μ
When creating a signal with a pulse width longer than seconds,
This can be done by specifying a plurality of cycles 1, which specifies synchronization of the ring counter with a 13x counter of 09.0η.

The external and vertical related pulses can be created in the same manner as in the conventional Dali described above.

In the embodiment whose configuration is shown in FIG.
Compared to the conventional synchronization signal generation circuit shown in the figure, the number of flip-flops is 420 fewer, and the circuit scale can be reduced accordingly and the power consumption can be reduced accordingly.

Furthermore, the period of the ring counter is approximately 10KH2, which is a signal within the video band, but is very low, and with such a frequency wave number, there is almost no possibility of it being radiated as noise.

By the way, in the above embodiment, a ring counter composed of 35 flip-flops was used, but the synchronization signal generation circuit can be similarly constructed using a ring counter composed of 65 7 flip-flops.

In this case, the frequency of one cycle of the ring counter is 8.5 times the horizontal scanning frequency. The original oscillation frequency is 14.3181
In the case of 8MH2, the above two methods are possible, but the embodiment shown in FIG. 3 is more advantageous in terms of the number of flip-flops.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the configuration of a conventional television synchronization signal generation circuit, FIG. 2 is a diagram showing an example of the configuration of a similar conventional circuit that improves the shortcomings of FIG. 1, and FIG. FIG. 4 is a waveform diagram illustrating the operation of the embodiment shown in FIG. 3. 12.13.14.15.16.17.18... Frequency division counter 112.113.114... Output terminal group μs
・455 step ring counter U...35 step ring counter 35.37...13 times counter Representative Patent attorney Kensuke Chika (and 1 other person) No.
! Figure 2 Figure 8 Figure 4

Claims (1)

[Claims] A ring counter that scans once at a frequency that is an odd multiple of half the horizontal scanning frequency of the television, and a logic circuit that completely synthesizes the signals output from each part of this ring counter and generates a signal that serves as a reference for a horizontal synchronization signal. A television synchronization signal generation circuit comprising: