JPS6247032B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal generator for television signals used in color television cameras and the like.

FIG. 1 shows a conventional television signal synchronization signal generator. In the figure, a reference clock 3 having a frequency _fCL is obtained by a reference frequency oscillator 2 using a crystal oscillator 1. In the periodic signal generator of the NTSC standard, 14.31818MHz is used as _fCL . The frequency of this reference clock 3 is divided by 4 using a frequency divider 4,
A color signal subcarrier 5 is obtained. On the other hand, the frequency of the reference clock 3 is divided by 7 by a frequency divider 6 to obtain a signal 7 with a frequency of f _CL /7, which is input to a counter circuit 8 capable of obtaining a minimum frequency of f _CL /910. NTSC
The standard horizontal frequency (hereinafter referred to as _fH ) is 14.31818/
Since the frequency is 910 MHz, by inputting the output signal 9 of the counter circuit 8 to the decoder circuit 10, a signal 11 of frequency f _H whose phase is determined by the signal 7 is obtained.
(for example, horizontal drive pulses, clamp pulses, etc.). Also, 2f _H from the decoder circuit 10
A signal 12 with a frequency of 2f _H /525 is input to a counter circuit 13 that can obtain the lowest frequency 2f H /525.

The vertical frequency (hereinafter referred to as _fV ) of the NTSC standard is
Since 2f _H /525, by inputting the output signal 14 of the counter circuit 13 to the decoder circuit 15, a signal 16 (for example, a vertical drive pulse, etc.) having a frequency f _V whose phase is determined by the signal 12 is obtained. Furthermore, by inputting the signal 17 of frequency f _H obtained from the decoder circuit 10 and the signal 18 of frequency f _V obtained from the decoder circuit 15 to the decoder circuit 19, information on the frequency f _H and frequency f _V is obtained. 20 (composite synchronization signal, composite blanking signal, burst flag, etc.) is obtained.

In the above-mentioned conventional synchronization signal generator, the frequency divider 6 and the counter circuits 8 and 13 are always operating, so when used in a color television camera, the video signal generated by the frequency divider or the counter circuit is added to the video signal. Frequency band noise may be mixed in.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization signal generating device that eliminates the above-described drawbacks of the prior art and reduces noise interference.

The gist of the present invention is that in a circuit that divides a reference clock and obtains a horizontal frequency synchronization signal of a television signal through a counter circuit and a decoder circuit,
The frequency dividing and counter circuit is configured to operate only during the horizontal blanking period of the television signal and to stop during other periods.

The present invention will be explained in detail using specific examples.

FIG. 2 shows a block diagram of an embodiment of the present invention. In the figure, block diagrams with the same functions as those in FIG. 1 are given the same numbers.

Output signal 22 of VCO 21 oscillating at frequency f _H
is input to the operation control circuit 23, and the frequency f _H is outputted.
The operation control signal 24 is obtained. This operation control signal 2
4 controls the operation and stopping of the frequency divider 6 and the counter circuit 8. Further, the output signal 22 is inputted to the field detection circuit 25, and a signal 26 having information on the start point of one vertical period of the television signal is obtained as an output, and inputted to the operation control circuit 27. An operation control signal 28 of the vertical frequency of the television signal (hereinafter referred to as _fV ) is obtained from the output of the operation control circuit 27, and this operation control signal 28 controls the counter circuit 13 and the reference clock 3.
455 and outputs a signal 29 with a frequency of _2fH .

Figure 3 shows signal waveforms at each part. The operation of the embodiment shown in FIG. 2 will be described in detail below using the signal waveforms shown in FIG.

FIG. 3A shows input and output signal waveforms of the operation control circuit 23. The output signal 22 of the VCO 21 has a period of one horizontal period _TH . The operation control signal 24 output from the operation control circuit 23 changes from level 0 to level 1 in synchronization with the change of the output signal 22 from level 0 to level 1.
change to the level. 31 is the decoder circuit 1 in FIG.
This is the composite blanking signal obtained as the output of 9. When the operation control signal 24 is at the 1 level, the frequency divider 6 and counter circuit 8 shown in FIG. 2 operate, and the composite blanking signal 31 changes from the 0 level to the 1 level after a specified time. In synchronization with this, the operation control signal 24 changes from 1 level to 0 level. The frequency divider 6 and the counter circuit 8 are configured so that the operation control signal 24 is 0.
Stop when level. Frequency dividers or counter circuits that operate and stop in response to the above-mentioned operation control signals are well known. Further, the above operation control circuit can also be easily realized using known digital circuit technology. As is clear from the above description, the frequency divider 6 and the counter circuit 8 operate only during the horizontal blanking period _TH.BLK in one horizontal period _{TH ,} and stop during the other periods. Generally, various synchronizing signal pulses in the horizontal period of a television signal are generated only during the horizontal blanking period T _H . _BLK , so the frequency divider ₆ and counter circuit 8 operate only during the T _H . A sync signal panel is obtained.

3B and 3C show input and output waveforms of the operation control circuit 27. Figure 3B shows the beginning of an odd field of the television signal (a field in which the start of the horizontal period and the start of the vertical period coincide), and Figure 3C
indicates the beginning of an even field (a field in which the start of the horizontal period and the start of the vertical period are shifted by T _H /2).

The output signal 22 of the VCO 21 is counted from the rising edge of the output signal 22 shown in FIG. 3C by a field detection circuit 25, which will be explained in detail later.
Signal 26 synchronized with the rising edge indicated by 〓〓 in Fig. 3B
get. The operation control signal 28 output from the operation control circuit 27 changes from 0 level to 1 level in synchronization with the signal 26 changing from 0 level to 1 level.
When the operation control signal 28 is at the 1 level, the frequency divider ₃₀ and the _counter circuit 13 shown in _FIG . Change to level 1. In synchronization with this, the operation control signal 28 changes from 1 level to 0 level. The frequency divider 30 and the counter circuit 13 stop when the operation control signal 28 is at 0 level. As described above, the frequency divider, counter circuit, and operation control circuit that operate as described above can be easily realized using known techniques.

In the even field shown in FIG. 3C, the field detection circuit 25 detects the output signal 2 of FIG. 3B.
The output signal 22 is counted from the rising edge of the signal indicated by – in _FIG . Operation control signal 2 from circuit 27
8 to control the stoppage of the frequency divider 30 and counter circuit 13.

As is clear from the above description, the frequency divider 30 and the counter circuit 13 operate during the vertical blanking period T _V .
Only _BLK operates, and the others stop. Generally, various synchronization pulses in the vertical period of a television signal occur only within the vertical blanking period T _V . _BLK , so
Since this occurs only within _TV.BLK , various synchronization signals can be obtained by operating the frequency divider _{30 and counter circuit 13 only during the TV.BLK period .}

By the way, the operation control signal 24 has a waveform as shown in _FIG . 3B and C within the vertical blanking period T _V . As in the conventional example shown in FIG. 1, if it is possible to obtain up to the lowest frequency _fH , a horizontal periodic pulse having the same phase as in other periods can be obtained even during this continuous operation period.

On the other hand, in order to prevent the oscillation frequency of the VCO 21 from fluctuating due to temperature characteristics, etc., the oscillation frequency obtained through _the frequency divider 30, _counter circuit 13, and decoder circuit 15 is A signal 32 with a frequency f _H obtained by dividing the reference clock 3 which is divided into two and the output signal 22 of the VCO 21 are inputted to a phase detection circuit 33, and the detected output is inputted to the VCO 21 as a control voltage 35 via a low-pass filter 34. A known phase lock loop circuit is configured to lock the frequency of the output signal 22 with a signal obtained by dividing the frequency of the reference clock 3.

FIG. 4 shows a specific example of the field detection circuit 25 of FIG. 2. Moreover, the signal waveforms of each part are shown in FIG. The output signal 22 of the VCO 21 is converted to the counter circuit 3.
Enter 6. The counter circuit 36 is configured to be reset after counting 525 pulses of the output signal 22 shown in FIG. Counter circuit 36
The output of the signal 22 is input to the decoder circuit 37, and the output of the signal 22 is input to the decoder circuit 37.
A signal 38 is obtained which is at 1 level during the period from the rise of the 263rd pulse to the rise of the 264th pulse and is at 0 level during the other periods, and the AND circuit 39 performs the AND of the signal 22 and the signal 38 to obtain the signal. Get 40.
Also, the level is 1 during the period from the rise of the 525th pulse of the signal 22 from the decoder circuit 37 to the rise of the first pulse (after the counter circuit is reset at the 525th pulse), and the level is 0 during the other periods. A signal 41 is obtained, and a signal 4 is obtained by inverting the polarity of the signal 22 by an AND circuit 42 and an inverter circuit 43.
4 and signal 41 to obtain signal 45.

The signal 40 and signal 45 obtained above are input to an OR circuit 46 to obtain an output signal 26. The counter circuit decoder circuit, AND circuit, OR circuit, and inverter circuit of the field detection circuit described above can be realized using known techniques.

As explained above, according to the present invention, in the television signal synchronization signal generator, the frequency dividing circuit and the counter circuit are configured to operate only during the horizontal blanking period and stop during other periods. There is no possibility that noise in the video signal band generated by the frequency dividing circuit or the counter circuit will be mixed into the video signal portion of the composite television signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional synchronizing signal generator, FIG. 2 is a block diagram of a synchronizing signal generator according to the present invention, FIG. 3 is a diagram showing signal waveforms of each part in FIG. FIG. 5 is a block diagram of a specific example of the field detection circuit 25 shown in the figure, and FIG. 5 is a diagram showing signal waveforms at various parts in FIG. 6, 13, 30: Frequency divider circuit, 8, 13: Counter circuit, 10, 15, 19: Decoder circuit, 2
1: VCO, 23, 27: Operation control circuit, 25:
Field detection circuit.

Claims (1)

[Claims] 1. An oscillation circuit that generates a reference high frequency signal, a counter circuit that divides the output signal of the oscillation circuit and uses this signal as a count input, and a decoder that uses the output signal of the counter circuit as an input and outputs a horizontal synchronization pulse. In a synchronization signal generator consisting of a circuit,
An operation control circuit is provided which receives a signal representing a horizontal blanking period of the television signal and controls the stoppage of the operation of the counter circuit, so that the operation of the counter circuit is stopped at least during the non-horizontal blanking period of the television signal. A synchronous signal generator comprising: