JPS5843310Y2 - Power synchronization device for facsimile equipment - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a power synchronizer that synchronizes various operations during reception and transmission to a power supply in a facsimile machine, and in particular includes an oscillation circuit that oscillates at a relatively high frequency. The present invention relates to a power synchronization device in a facsimile machine that uses output to supply scanning pulses to a reading system or a recording system.

In factor communication, images are sent and received via a transmission path such as a telephone line.

In this case, the transmitter and receiver must perform synchronized operations, and if this synchronization is lost, images cannot be reproduced.

Therefore, in such facsimile communication,
Synchronization between the transmitter and receiver is achieved by means such as a power supply synchronization method or an independent synchronization method.

In this case, the conventional power synchronization method performs synchronized operation between transmitters and receivers connected to the same power supply system, and the synchronous motor is rotated in synchronization with the power supply frequency, and the transmitter side transmits data. A method is adopted in which synchronization is achieved by mechanically locking the synchronous motor using a clutch when the phase signal received by the synchronous motor matches the rotational phase of the synchronous motor.

However, such conventional power synchronization methods have the disadvantage that high-precision one-phase operation cannot be achieved because synchronous operation is achieved through mechanical operation using clutches, etc. Furthermore, since the device operates in synchronization with the power supply after the synchronization operation is completed, it has various drawbacks, such as fluctuations occurring in the received image due to fluctuations in the power supply.

On the other hand, conventionally, the frequency division ratio determined by the shift amount is n.

The phase is designed to obtain a stable shift amount of 1/n with the same accuracy as the main oscillator, with n-1 as the center, by feeding back to or stopping the frequency division stages n-1 and n-2. The phase matching method shifts the excitation frequency of the synchronous machine necessary for matching, and the repetition frequency on the scanning side is set to 50% of the power supply frequency.
A scanning method has been proposed that improves the signal-to-noise ratio by scanning at a common multiple of Hz and 60 Hz, continuously transmitting signals, and scaling at 50 Hz or 60 Hz on the receiving side.

However, the former phase matching method uses a synchronous machine (
It is configured to perform phase matching with the transmitting side by increasing or decreasing the rotation speed of the main oscillator (same as increasing or decreasing the scanning speed).
A//, a///, a switch, and a feedback circuit are configured to change the overall division ratio of the frequency divider a' or the divider a.

This phase matching method consists of (a) dividing the output of the oscillator using a frequency divider to excite the synchronous machine;

(b) By feeding back the output of the frequency divider to a predetermined frequency divider, the frequency division ratios n-1 and n-2 are changed.

This is a method of changing the frequency division ratio of the frequency divider as a whole, and is a frequency division means that generates three types of motor drive frequencies from the same oscillator.

In addition, in the latter scanning method, the horizontal scanning frequency is set to a common multiple of the two power supply frequencies, and the frequency is divided so that the repetition frequency of the received image matches the power supply frequency used, but it is not synchronized with the power supply frequency. Due to the value limited to a common multiple of the power supply frequency (independently synchronized source oscillation cannot be achieved),
Further, it is inconvenient if the upper limit of the frequency is also restricted by circuit components, etc., and there is a drawback of lack of stability.

In view of the above points, the present invention was devised to solve such problems and eliminate such drawbacks.The main purpose of this invention is to provide an extremely accurate synchronization signal in which the output of an independent oscillator is frequency-divided. An object of the present invention is to provide a power synchronization device for a facsimile machine, which can obtain highly accurate power synchronization in a short time.

Another purpose of the present invention is that after the synchronization operation is completed, it is possible to prevent fluctuations in the received image due to fluctuations in the power supply, and it is also possible to communicate with devices using other power supply cycles. It is an object of the present invention to provide a power synchronization device for a facsimile machine that can overcome the constraints that the common multiple is a limited value and the upper limit of the frequency is also constrained by circuit components.

In order to achieve such an objective, the present invention includes a multiplier circuit that multiplies a power signal, a first frequency divider circuit that divides the output of the multiplier circuit, and an oscillation circuit that oscillates at a relatively high frequency. a second frequency dividing circuit which frequency divides the output and sends out a synchronizing signal having the same frequency as the output of the first frequency dividing circuit, and which is reset by the output of the first frequency dividing circuit; a reception control circuit that resets the first frequency divider circuit by a phase signal inputted from the input circuit and stops the synchronous control operation when synchronization between the phase signal and the output of the first frequency divider circuit is obtained; This is something I prepared for.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a power synchronization device for a facsimile machine according to the present invention.

In the figure, 1 is an input terminal to which a 50Hz or 60Hz power signal is supplied, 2 is a phase-locked loop that receives the power signal from input terminal 1, and 3 is a phase-locked loop.
This is a frequency divider that divides the output of lock loop 2. This frequency divider 3 divides the frequency by /4 and 1/ by the switch output described later.
It is configured to be switched to frequency division by 3.

4 is a frequency divider that further divides the output of the frequency divider 3 by 4 and supplies it to the input side of the phase-locked loop 20. It constitutes a multiplier circuit 5 that multiplies the power signal.

6 is a /19° frequency divider j1! composed of three frequency dividers 7 to 9 connected in series and an AND gate 10. r (first frequency dividing circuit), 11 is a differentiating circuit that differentiates the output of the first frequency dividing circuit 6 which frequency divides the output of this multiplier circuit 5, and this differentiating circuit 11 includes a capacitor 2, a resistor 13, and an inverter. 4.

15 is an oscillation circuit that oscillates a relatively high signal of, for example, 23.04 MHz, and 16 is a frequency dividing circuit (second frequency dividing circuit) that divides the output of this oscillation circuit 15 to obtain a power signal and a phase signal. Then, 11 This second frequency dividing circuit 16 is /c, ,7g, /2t
115.2. It is constituted by frequency dividers 17 to 21 that perform frequency division by /6.

22 is a phase signal output terminal, and 23 is a switch for switching the frequency division ratios of the frequency divider 3 and the frequency divider 18.

24 is a phase signal input terminal, 25 is a Nantes gate that searches for a match between the phase signal from the input terminal 24 and a synchronization completion signal, which will be described later, and 26 is a timer circuit operated by the output of the Nantes gate 25. resistance 27
An integrating circuit consisting of a capacitor 28 and a capacitor 28
The capacitor 28 is made conductive by the output of the unijunction transistor 29 and the Nant gate 25, which is made conductive to generate an output pulse every time the potential across both ends of the capacitor 28 reaches a predetermined value.
A transistor 30 short-circuits both ends of the transistor 30.

31 is an inverter that inverts the output of the timer circuit 26;
32 is a monomulti that is triggered by the output of the inverter 31, and this monomulti 32 has a period T of the phase signal.
It is set to transmit an output in a range wider than 2T and smaller than 2T.

33 is an inverter that inverts the output of the inverter 31 and supplies it to the flip-flop 34; 35 is a flip-flop triggered by the output of the flip-flop 34; these constitute a binary counter.

36 is an AND gate that finds a match between the set output of the flip-flop 34, the output of the inverter 33, and the output of the frequency divider circuit 6; 37 is a binary counter that counts the output of the AND gate 36 and supplies it as an input on one side of the tent game 1250; It is composed of two flip-flops 38 and 39.

Further, 40 to 42 are Nant gates, and 43 resets the first frequency divider circuit 6 by the phase signal inputted with the receiving operation, and also resets the first frequency divider circuit 6 by the phase signal and the output of the first frequency divider circuit 6. This is a reception control circuit that stops synchronization control operation when synchronization is obtained.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to the time chart shown in FIG.

This FIG. 2 is an operation explanatory diagram showing the operation waveforms of each part, where a shows the output of the first frequency dividing circuit 6, b shows the output of the timer circuit 26, C shows the output of the monomulti 32, d,
e is the output of the flip-flop 34, f is the output of the flip-flop 35, g is the output of the Nant gate 42, h is the output of the Nant gate 40, and i is the output of the AND gate 36.

In addition, I, II, III, and IV are the first statements, respectively.
2nd look... shows the area of 4th whitening, and also shows the area of 2nd figure g
It is shown that If I II is +1111 when it is normal.

First, when transmitting an image signal, if a power signal of, for example, 50) iz is supplied to the input terminal 1, this power signal is transmitted to the phase-locked loop 2, the 1 frequency divider 3, and the 1/1 frequency divider 3.
16 in the multiplier circuit 5 constituted by the 8 frequency divider 4
The signal is multiplied to 00Hz.

The output of this multiplier circuit 5 is frequency-divided by 1/2 in a first frequency divider circuit 6, and a signal of 8.33 Hz92 is sent out.

On the other hand, the oscillation circuit 15 has a relatively high frequency, for example 23.
A signal of 04 ME (z) is oscillated, and this oscillation output is frequency-divided by the second frequency divider circuit 16 so that a signal having the same period as the output of the first frequency divider circuit 6 can be obtained.

Therefore, the output of the oscillation circuit 15 is 23.04 MHz.
In the case of 1/15, 1/9, 1/2, 115.2.
/6 frequency dividers 17 to 21 may be connected in series.

In this case, the output of the first frequency dividing circuit 6 is the output of the differentiating circuit 1.
1, the second frequency divider circuit 160 is configured to reset the frequency dividers 17-21 through the second frequency divider circuit 160, thereby providing synchronization between the power supply signal and the output of the second frequency divider circuit 16. .

Since this synchronization operation is performed in the portion where a relatively high signal is frequency-divided, the synchronization accuracy is extremely high.

Next, when performing a receiving operation, a phase signal generated in conjunction with the receiving operation is supplied to the input terminal 24.

In this case, since the flip-flop 39 of the binary counter 37 is in the reset state, the phase signal supplied to the input terminal 24 is transmitted to the timer circuit 2 through the Nant gate 25.
The signal is supplied to the transistor 30 of No. 6, and the transistor 30 is turned off to start a timing operation.

That is, when the transistor 30 is turned off, the integrating circuit constituted by the resistor 27 and the capacitor 28 is activated, and the unijunction transistor 29 is turned on at regular intervals to send out an output pulse.

Therefore, by setting the time constant of the timer circuit 260 to be somewhat smaller than the phase signal, narrow signals are blocked, and multiple pulse outputs are sent out for signals that are too wide.

The output pulse of the timer circuit 26 is inverted in the inverter 31 (see Fig. 2) and then triggers the monomulti 32 so that the output pulse is longer than the period T of the phase signal by 2T.
(see FIG. 2C) and releases flip-flop 34.350 from reset.

Further, the output of the inverter 31 is further inverted in the inverter 33 and then triggers the flip-flop 34 at the falling edge.

(See Figure 2 d and e) In this case, the output of the Nant gate 41 is 1□ If during the output period of the inverter 330.
Along with this, Nantes Gate 40 to 111
11 outputs are sent to the first frequency divider circuit 60 and frequency dividers 7 to 9.
will be reset and synchronized.

That is, the first frequency dividing circuit 6 is reset by the first output I and the third output ■, which are the outputs of the Nant gate 40 shown in the second diagram.

Then, after time T, an output pulse is sent out from the first frequency dividing circuit 6, and if the synchronization is completely achieved, the next phase signal will be supplied in accordance with this timing.

Therefore, each time the phase signal and the output of the first frequency dividing circuit 6 are synchronized, a coincidence output is obtained from ANDK)3s, and this coincidence output is counted by the binary counter 37. be done.

Then, if such synchronous operation is obtained twice in a row,
The output of the binary counter 37 closes the Nante gate 25 and the synchronous control operation is completed.

In this way, when transmitting, the output of the first frequency dividing circuit 6 synchronized with the power supply frequency resets the second frequency dividing circuit 16 and extracts the transmission synchronization signal, and when receiving, the output of the first frequency dividing circuit 6 synchronizes with the power supply frequency. Since the first frequency divider circuit 6 is reset by the input phase signal and the received synchronization signal is taken out from the second frequency divider circuit 16 until synchronization is achieved with the In addition to obtaining extremely high-precision output by frequency-dividing the output, it is not affected by fluctuations in the power supply frequency after the synchronization operation is completed, and there is no fluctuation in the received image.
Not a single phenomenon occurs.

Next, if for some reason a phase signal with a width greater than a predetermined width or a signal that is mistaken for a phase signal is supplied during one cycle (T) of the phase signal, two The above pulses are supplied to the flip-flop 34, and accordingly, a set output is supplied from the flip-flop 35 to the Nant gate 42 when two pulses are counted.

Therefore, at this point, I
The I OI+ output is sent out and the counter 37 is reset, and the output of the Nantes gate 40 becomes II I I
It is inverted to I and the frequency divider circuit 6 is reset.

As a result, as described above, a synchronization operation is prevented for a phase signal having a width exceeding a specified value or for noise that may be mistaken for a phase signal.

That is, the Nant gate 41, which finds a match between the output of the monomulti 32, the output of the timer circuit 26, and the reset output of the flip-flop 34, and resets the first frequency dividing circuit 6 with the output, is activated when the monomulti 32 is in operation ( Figure 2C
), the phase signal equivalent to that generated after the second view (see N shown in Figure 2 f) is regarded as noise, and the first frequency dividing circuit 6 is made to perform an operation to reset it again. It is configured.

Next, when the power signal becomes 60Hz, the same operation can be performed by closing the switch 23 and switching the division ratios of the frequency divider 3 and the frequency divider 181 to /3 and /1o. can.

The second frequency dividing circuit 16 is not only used for the main scanning frequency, but also needs to extract a relatively high frequency for driving and scanning an optical reading device such as a solid-state scanning system, a recording system device, etc. These are independent synchronous oscillators (
The second frequency dividing circuit 16 is used with the oscillation circuit 15) as the base.

Therefore, it is not possible to communicate with other facsimiles whose main scanning frequency is synchronized with the power supply.

Therefore, the output of the first frequency division system, which is synchronized with the power signal supplied to input terminal 1, is set to the same synchronization signal frequency as the second frequency division output (independent synchronization), and the second frequency division system is synchronized with the power signal supplied to input terminal 1. By resetting the frequency division system, the second frequency division output system can obtain an output equal to the power supply cycle, and can communicate with devices having other power supply cycles.

The common multiple of the power supply frequency is a limited value (independently synchronized source oscillation cannot be achieved), and the upper limit of the frequency is also constrained by circuit components, etc., and it is unstable. Be able to do it.

As explained above, according to the present invention, in a facsimile machine equipped with an oscillation circuit that oscillates at a relatively high frequency for scanning a reading system or a recording system, and a second frequency dividing circuit, the power supply frequency is The output of the synchronized first frequency divider circuit resets the second frequency divider circuit and extracts the transmission synchronization signal, and at the time of reception, the first frequency divider circuit is reset by the input phase signal until it is synchronized with the output of the first frequency divider circuit. Since the configuration is such that the frequency dividing circuit of the second frequency dividing circuit is reset and the received synchronizing signal is taken out from the second frequency dividing circuit, an extremely highly accurate synchronizing signal obtained by dividing the frequency of the output of the independent oscillator can be obtained. After the synchronous operation is completed, it is not affected by fluctuations in the power supply frequency.
Since there is an advantage that no 11-fluctuation phenomenon occurs in the received image, the practical effect is extremely good.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a power synchronizing device for a facsimile machine according to the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 5... Multiplier circuit, 6... Frequency dividing circuit (first frequency dividing circuit), 15... Oscillation circuit, 16...
...Frequency divider circuit (second frequency divider circuit), 43...
・Reception control circuit.

Claims (1)

[Scope of utility model registration request] A power synchronization device for a facsimile machine includes an oscillation circuit that oscillates at a relatively high frequency and uses the output of this oscillation circuit to supply scanning pulses to a reading system or a recording system. a first frequency divider circuit that frequency divides the output of the multiplier circuit; and a first frequency divider circuit that frequency divides the output of the oscillation circuit to send out a synchronization signal having the same frequency as the output of the first frequency divider circuit; a second frequency divider circuit that is reset by the output of the frequency circuit; and a second frequency divider circuit that resets the first frequency divider circuit by a phase signal inputted along with the reception operation, and the phase signal and the output of the first frequency divider circuit. 1. A power synchronization device for a facsimile machine, comprising: a reception control circuit that stops a synchronization control operation when synchronization with the facsimile machine is achieved.