JPS584352Y2 - Vertical synchronization circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a vertical synchronization circuit, and when generating and outputting pulses synchronized with the vertical synchronization circuit using a countdown method, the above-mentioned pulses can be stably generated without any limitation on the pulse width of the vertical synchronization signal. Furthermore, the present invention provides a vertical synchronization circuit capable of outputting a vertical synchronization pulse that can extremely minimize the phase fluctuation of the above-mentioned pulse due to noise mixed in just before the input of the vertical synchronization signal, thereby obtaining a stable reproduced image. The purpose is to

FIG. 1 shows a block system diagram of a part of a conventional television receiver centering on the deflection system.

A composite video signal obtained by detection by a video detection circuit (not shown) enters the input terminal 1, and this composite video signal is amplified by an amplifier 2 and then divided into two parts. The other one is supplied to the synchronous separation circuit 4, respectively.

The composite synchronization signal containing both the horizontal synchronization signal and the vertical synchronization signal taken out from the synchronization separation circuit 4 is supplied to the differentiation circuit 5 where the horizontal synchronization signal is separated, and is supplied to the integration circuit 6 where the horizontal synchronization signal is separated. The vertical synchronization signal is separated.

The horizontal synchronization signal taken out from the differentiating circuit 5 is sequentially supplied to a phase detection circuit 7, a horizontal oscillation circuit 8, and a horizontal deflection output circuit 9.

The flyback pulse generated at the output of the horizontal deflection output circuit 9 is fed back to the phase detection circuit 7, and this feedback loop causes the output of the phase detection circuit 7 to be horizontally adjusted so that the phases of the flyback pulse and the horizontal synchronization signal match. Controls the oscillation circuit 8.

The output of the horizontal deflection output circuit 9, synchronized with the horizontal synchronization signal in this way, causes a horizontal deflection current to flow through the deflection coil 10.
At the same time, a high voltage is generated and applied to the anode of the cathode ray tube 11.

On the other hand, the vertical synchronizing signal taken out from the integrating circuit 6 is supplied to the vertical oscillation circuit 12, where vertical oscillation is synchronized.

The oscillation output from the vertical oscillation circuit 12 is transmitted to the vertical deflection circuit 13.
Here, it is converted into a sawtooth wave synchronized with the vertical synchronization signal, and further amplified to cause a vertical deflection current to flow through the deflection coil 10.

As described above, the composite video signal amplified by the amplifier 3 is reproduced and displayed on the cathode ray tube 11.

The above configuration is the circuit configuration most often seen in television receivers, and the vertical synchronization circuit is configured to apply a vertical synchronization signal as a trigger to the vertical oscillation circuit 12 for direct synchronization.

However, with this configuration, even if the vertical synchronization signal is not input for a short period of time for some reason, vertical synchronization may be lost, and complete interlacing is difficult.
Further, there are drawbacks such as the need to adjust the vertical oscillation frequency and the vertical synchronization becoming unstable due to noise.

Therefore, in order to eliminate the above-mentioned drawbacks, a countdown type vertical synchronization circuit, a general block diagram of which is shown in FIG. 2, is conventionally known.

This countdown method takes advantage of the fact that there is a certain relationship between the horizontal scanning period (hereinafter also referred to as the period of the horizontal synchronizing signal) and the vertical scanning period (hereinafter also referred to as the period of the vertical synchronizing signal). The ratio of both periods is 2 in the NTSC system.
1525, PAL system, SECAM system mainly 2
/625, 2/819, 2/405, etc., but in the following explanation, the case of 21525 will be described.

Note that the circuit configuration is the same as below in the case of other period ratio methods.

In FIG. 2, the same parts as in FIG. 1 are given the same numbers, and 14 is an oscillator with horizontal scanning frequency fH
In this method, it oscillates at a frequency of 2fH, which is twice the frequency of approximately 15.7kHz.

The output signal of this oscillator 14 is frequency-downgraded by a foot-flop 15 and supplied to the horizontal deflection output circuit 9, while a clock pulse (hereinafter referred to as , CP) and counted here.

The ratio between the CP period "Hp (=777,) and the vertical synchronization signal period TV is 525 when receiving an NTSC color video signal.

Therefore, when the counter 17 counts CP by 525, it supplies an output to the phase comparison pulse shaping circuit 18, which generates and shapes a pulse having a width within one cycle of CP.
This is supplied to one input terminal of the phase comparison circuit 20.

On the other hand, the vertical synchronizing signal taken out from the integrating circuit 6 is supplied to the waveform shaping circuit 19, where the waveform is shaped, and then applied to the other input terminal of the phase comparison circuit 20, and the phase comparison pulse shaping circuit 18 is applied to the other input terminal of the phase comparison circuit 20. The phase is compared with the output pulse of

The output signal of the phase comparison circuit 20 is applied as a switching signal to the switching circuit 21, and when the phases of the surface input signals of the phase comparison circuit 20 do not match, the vertical synchronization signal from the waveform shaping circuit 19 is selectively outputted and the counter 17 is outputted. Reset.

Therefore, like the conventional circuit shown in FIG. 1, the counter 17 enters a state in which it is reset for each input vertical synchronizing signal (hereinafter referred to as sync mode) when the phases do not match.

On the other hand, when the phases of the plane input signals of the phase comparison circuit 20 match, the switching circuit 21 selectively outputs the phase comparison pulse from the counter 17 according to the output signal of the phase comparison circuit 20, and uses this phase comparison pulse to output the phase comparison pulse from the counter 17. Reset.

Therefore, when the phases match, the counter 17 enters a state where the frequency is divided into (hereinafter referred to as countdown mode).

The vertical synchronization pulse shaping circuit 22 uses the output pulse of the switching circuit 21 obtained as described above and the counting output of the counter 17 that is output when the CP has been counted by a certain number (for example, 25) from the time when the counter 17 is reset. Therefore, in both the sync mode and countdown mode, a vertical synchronization pulse synchronized with the vertical synchronization signal is output, and the vertical deflection circuit 13
supply to.

Although the above is a general operation of a countdown type vertical synchronization circuit, a more detailed example of a conventional countdown type vertical synchronization circuit is shown in FIG.

In FIG. 3, the same parts as in FIG. 2 are given the same numbers.

In FIG. 3, 23 is a ripple counter formed by cascading ten flip-flops, which corresponds to the counter 17 shown in FIG. 2 and counts CP.

In addition to the above-mentioned input terminals, the counter 23 has a reset terminal R as an input terminal, and al as an output terminal.

a2. a3. a4. As shown in each a5, the CP count values are 500, 550, 25, 525.1 and 52 as examples.
6, each has an output terminal that outputs a pulse only at the time of 6.

The output vertical synchronization signal of the integrating circuit 6 is sent to the pulse shaping circuit 24.
As will be described later, the pulse is shaped into a pulse (hereinafter referred to as vertical synchronizing pulse a) having a pulse width within one cycle of CP, and then applied to one input terminal of the AND gate 25.

The other input terminal of the AND gate 25 is applied with the Q output of the RS flip-flop 26, which is set to a set state by a pulse output from the terminal a1 when the counter 23 counts 500 CP.

Therefore, the vertical synchronizing pulse a causes the counter 23 to set CP to 50.
From the point in time when the RS flip-flop 26 is reset until the RS flip-flop 26 is reset, the signal is outputted from the AND gate 25 and supplied to the two-man power NAND gate 27 and the three-man power NAND gate 32, respectively.

When the counter 23 counts CP by 525, a pulse is generated and output from the terminal a4 of the counter 23, and this pulse is supplied to the set terminal S of the two-man NAND gate 28 and the RS flip-flop 37, respectively.

In the sink mode, the Q terminal of the T-type flip-flop 36 is at H level and the Q terminal is at L level, so A
NA due to the vertical synchronizing pulse a passing through the ND gate 25
The ND gate 27.30 operates and sets the RS flip-flop 31, and at this time, the pulse generated at its output resets the counter 23 to O, and simultaneously resets the RS flip-flop 26 and sets the RS flip-flop 3.
8 is set.

The RS flip-flop 38 has a counter 23 with a CP of 25.
Since it is reset by the pulse from terminal a3 that is generated and output when counting, the RSS fluruff 0 fluff 03
The pulse width of the output pulse of CP is equal to 25 cycles of CP, and this pulse is used as a vertical synchronization pulse in the vertical deflection circuit 13.
is output to.

Also, in sync mode, vertical synchronization pulse a is NAN
When no input is made to the D gate 27, the counter 23 must be reset at a certain state after the count value 525 in order to continue counting.

Here, when the counter 23 counts 550 CP, a pulse is generated from the terminal a2, and this pulse operates the NAND gate 29.30 and sets the RS footflop 31, thereby resetting the counter 23. Ru.

In addition, in the countdown mode, the Q terminal of the T-type flip-flop 36 is at the L level and the Q terminal is at the H level, so when the counter 23 has counted 525, a pulse generated from the terminal a4 causes the NAND gate 2 to
8.30 operates to set the RS flip-flop 31 and reset the counter 23.

In any of the above cases, the pulse from the NAND gate 30 is supplied to the set terminal of the RS flip-flop 31, and the polarity of CP is inverted by the inverter 60 and supplied to the reset terminal. It is reset at the start of the level, and the period during which the RS flip-flop 31 is set is the H level period within approximately one cycle period of CP.

Further, the RS flip-flop 38 generates and outputs a vertical synchronizing pulse.

RS flip-flop 37.3 human powered NAND gate 32
．． 33.2 Manual NAND gate 34, counter 35 and T-type rough flip-flop 36 perform the phase comparison operation.

The RS flip-flop 37 is set by the output pulse of the terminal a4 of the counter 23, and reset by the output pulse of the terminal a5. Phase comparison pulses of H level and L level are generated and supplied to NAND gates I.32 and 33, respectively.

Counter 35 counts the output vertical synchronization pulses of RS flip-flop 38.

When the counter 35 counts a fixed number of times (4 times), a pulse is generated at its output to invert the output of the T-type flip-flop 36.

In the sink mode, the Q terminal of the T-type flip-flop 36 is at H level and the Q terminal is at L level.

In the case of the sync mode, if the reset pulse of the counter 23 and the phase comparison pulse from the RS flip-flop 37 do not match in phase, the NAND game (33.34) operates every time the reset pulse is generated. The output of 33 is L level, the output of 34 is 'H level),
Counter 35 is reset.

Therefore, the counter 35 cannot count the vertical synchronizing pulses from the RS flip-flop 38 four times in a row, and the output of the T-type flip-flop 36 is not inverted and the sync mode continues.

On the other hand, in the case of sink mode, when the reset pulse and the phase comparison pulse match in phase, the NAN
The reset operation of the counter 35 by the D gates 33 and 34 is no longer performed, and the counter 35 counts the vertical synchronizing pulses.

When the count value of the counter 35 reaches 4, the output of the T-type flip-flop 36 is inverted, and the Q output is at L level and the Q output is at H level.
Enter level countdown mode.

This countdown mode uses vertical synchronization pulse a and RS
If the phase matches the output phase comparison pulse of the flip-flop 37, the NAND game (32, 34) operates and resets the counter 35 each time the vertical synchronizing pulse a is generated, so that the operation continues.

On the other hand, in the countdown mode, when the vertical synchronization pulse a and the phase comparison pulse do not match in phase, the NAND gates t-32 and t-34 do not operate, and the output of the NAND gate 34 remains at the L level. , counter 3
5 is not reset.

Therefore, after four cycles of the vertical synchronization signal, the output of the T-type flip-flop 36 is inverted to enter the sync mode.

From the above operation, if the composite video signal has a ratio of the horizontal synchronization signal period to the vertical synchronization signal period which is not 2:525, it always operates in the sync mode.

On the other hand, in the case of a composite video signal having the period ratio relationship of 2 to 525, it normally operates in countdown mode,
When switching channels or when the vertical synchronization signal phase changes even when the signal is the same, the mode shifts from countdown mode to sync mode for a short period of time immediately after, and after vertical synchronization is established, it switches to countdown mode again.

Although the conventional vertical synchronization circuit shown in FIG. 3 can improve the drawbacks of the vertical synchronization circuit shown in FIG. 1 to some extent, it has the following drawbacks.

The first drawback is that once vertical synchronization is established and countdown mode is entered, countdown mode operation cannot be continued even when no vertical synchronization signal is input unless the phase of the vertical synchronization signal changes as described above. However, in the conventional circuit shown in FIG. 3, if the vertical synchronization pulse a is not generated, the NAND gate 3
2.34, the reset operation of the counter 35 is no longer performed, and the T-type flip-flop 3 is reset after 4 vertical scanning periods.
Since the output of 6 is inverted and becomes the sync mode, and the vertical synchronizing pulse a is not input to the NAND gate 27, the counter 23 performs a frequency dividing operation of 11550 by the reset operation of the counter 23 by the NAND gate 29 and 30. This had the disadvantage that vertical synchronization could be lost.

A situation in which the vertical synchronization signal is difficult to be output from the synchronization separation circuit 4 occurs when the sync chip level of the vertical synchronization signal section of the composite video signal is reduced compared to that of the horizontal synchronization signal section, and is caused by special conditions such as ghosting, etc. This can be seen in signals that pass through many satellite stations.

However, even if the composite video signal is in such a state, the sync separation circuit 4 often outputs a portion of the vertical sync signal, albeit intermittently and irregularly.

Therefore, in such a case, unlike the case where the vertical synchronization pulse a is not output at all as described above, vertical synchronization can sometimes be achieved, but there is a drawback that the vertical synchronization is unstable.

A second drawback is that the conventional pulse shaping circuit 24 has a circuit configuration as shown in FIG. In this case, the vertical synchronization pulse could not be properly shaped.

To explain this content below, T-type flip-flops 42, 43, 44 connected in cascade in FIG.
．． 45 is assumed to operate at the rising edge of the input pulse, and all output terminals Q are assumed to be at H level in the initial state.

Immediately before the positive polarity vertical synchronizing signal is input to the inverter 39, the output of the five-power NAND gate t-40 becomes L level, is passed through the AND gate 41, and is input to the input terminal T of the T-type flip-flop 42 of the CP. The application of is cut off.

When a positive vertical synchronization signal is input, NAND gate 4
The output of 0 becomes H level, and CP passes through the AND gate 41 and is applied to the input terminal T of the T-type flip-flop 42.

As a result, all T-type flip-flops 42 to 45 start operating.

Here, each output of the Q terminal of the T-type flip-flop 42, the Q terminal of the T-type flip-flops 43 to 45, and CP (the fifth
A) is configured to be applied to the five-power AND gate 46, so that after the vertical synchronization signal shown in FIG. 5B is input from the AND gate 46 as shown in FIG. Since all inputs of the AND gate 46 become H level only when the second CP is input, this CP is output as the vertical synchronizing pulse a.

Here, the input vertical synchronizing signal ' is obtained by integrating a composite video signal having a vertical synchronizing signal part of about 3H by the integrating circuit 6, so its pulse width is about 6H or less, that is, 12 cycles of CP. Since the following is true, the output of the inverter 39 becomes H level when at least the 13th or later CP is input.

Then, at the 16th pulse from when the vertical synchronization signal is input, the Q outputs of the T-type flip-flops 42 to 45 all become H level, so at this time, the output of the NAND gate 40 becomes L level, and the AND gate 41 becomes CP. prevent it from passing.

Even if a vertical synchronizing signal having a pulse width narrower than the L level period in one cycle of CP is input to the inverter 39 during the L level period of CP, the AND gate 41 does not operate at all.

Therefore, in order to stably generate the vertical synchronizing pulse a in the conventional pulse shaping circuit 24, the pulse width of the vertical synchronizing signal must be larger than the L level period within one cycle of CP.

However, under the conditions described above, the synchronous separation circuit 4
When only a portion of the vertical synchronizing signal is output to the output of the vertical synchronizing signal, the pulse width of the vertical synchronizing signal becomes narrow, and the conventional pulse shaping circuit 24 cannot stably obtain the vertical synchronizing pulse a.

In addition, as shown at 47 in FIG. 6B, if noise is mixed in just before the vertical synchronization signal, the vertical synchronization pulse corresponding to the vertical synchronization signal is applied to the AND gate 4, as shown at a' in FIG. 6C.
6 output is not generated.

That is, in the circuit configuration of the conventional pulse shaping circuit 24 shown in FIG. Since all outputs are at H level, the noise 47 and the leading edge of the regular vertical synchronization signal are 1 of CP.
If it is within 6 or 8H, it is a normal vertical synchronization pulse a.
is not generated.

Immediately before the vertical synchronizing signal part in the composite video signal, there is a 3H equalization pulse part, and the signal level during this period is at the pedestal level. Noise as shown in the figure is likely to be mixed in, and the pulse shaping circuit 24 is likely to malfunction due to this noise.

The conventional pulse shaping circuit 24 had the above-mentioned drawbacks.

Note that some conventional vertical synchronization circuits do not have the pulse shaping circuit 24 described above.

This circuit compares the phases of the vertical synchronizing signal from the integrating circuit 6 and the phase comparison pulses of the Q and Q outputs of the RS flip-flop 37.

The pulse width of the vertical synchronization signal from the integrating circuit 6 is sufficiently wider than the phase comparison pulse, which has a pulse width of one synchronization of CP, as described above.

The phase relationship between the phase comparison pulse and the vertical synchronization signal (shown in FIG. 5B) is the period between the leading edge and the trailing edge of the vertical synchronization signal, and is not always constant.

In addition, in the case of a signal that is slightly different from the ratio relationship between the vertical synchronization signal period and the horizontal synchronization signal period of the regular video signal, it takes many times to detect the phase shift with the vertical synchronization signal and phase comparison pulse mentioned above. Requires vertical period period, counter 3
The number of counts of 5 must be increased, which has the disadvantage that the phase detection ability is significantly reduced.

The present invention mainly eliminates the second drawback, and also eliminates the first drawback, and is shown in FIGS. 7 to 9 A-L.
One embodiment will be described with reference to the drawings.

FIG. 7 shows a circuit system diagram of an embodiment of the vertical synchronization circuit according to the present invention, and the same parts as in FIG. 3 are given the same numbers.

The difference from the conventional circuit shown in FIG. 3 is that the circuit configuration of the pulse shaping circuit 48 is as shown in FIG.
The point is that a vertical synchronizing signal or a shaped version thereof is input to the count input of the counter 35 via an RS flip-flop 49.

In FIG. 7, a vertical synchronizing signal g as shown in FIG. (corresponds to the vertical synchronizing pulse a shown in FIG. 5C).

When no noise is mixed in, the vertical synchronizing signal has a waveform as shown by a solid line, and at this time, the vertical synchronizing pulse g also has a waveform as shown by a solid line.

The specific configuration and operation of the above pulse shaping circuit 48 will be explained with reference to FIG. 8.

The vertical synchronizing signal is supplied to one input terminal of a two-way NOR gate 50 and a set terminal of an RS flip-flop 51, respectively.

D-type flip-flops 52 and 53 are connected in cascade to the Q output terminal of this RS flip-flop 51, respectively.
Further, the CP shown in FIG. 9A and the CP obtained by inverting the polarity of the CP shown in FIG. 9A are supplied to each clock pulse terminal of the D-type flip-flops 52 and 53.

The Q output terminal of the D-type flip-flop 53 is connected to the other input terminal of the NOR gate 50, while the
A D-type flip-flop 52 is connected to the input terminal of the ND gate 55.
It is connected together with the Q output terminal of .

Further, the Q output terminal of the D-type flip-flop 53 is connected to the set terminal of the RS flip-flop 49.

The D-type flip-flops 52 and 53 output the level of the pulse input to the D terminal at the rising edge of CP to the Q terminal, and output to the Q terminal a level with a polarity opposite to that of the Q terminal.

Furthermore, in the following explanation, one section of CP refers to the period from the rising point of CP to the rising point of the next CP.

The RS flip-flop 51 is reset until just before the positive vertical synchronization signal is input (Q terminal is at L level), and the Q terminals of D-type flip-flops 52 and 53 are both at L level.

Therefore, the Q terminal of the D-type flip-flop 53 is at the H level, and the output level of the NOR gate 50 (the reset terminal input level of the RS flip-flop 51) is at the L level.

In the above state, when a vertical synchronizing signal as shown in FIG. 9B is received, the RS flip-flop 51 is set, and an H level signal as shown in FIG. 9C is sent to the D terminal of the D-type flip-flop 52. C is applied.

As a result, the signal appearing at the Q terminal of the D-type flip-flop 52 goes to the H level at the next rising edge of CP, as shown by d in Figure 9, and the signal appearing at the Q terminal of the D-type flip-flop 53 goes to the H level at the falling edge of CP. A signal as shown in E of the same figure is generated.

The above state continues while the RS flip-flop 51 is set.

Therefore, the output of the AND gate 55 is D as shown in Figure 9.
During the period in which both the Q output signal of the D-type flip-flop 52 and the Q output signal of the D-type flip-flop 53 shown in FIG. A pulse corresponding to the H level pulse width of the incoming CP (in the countdown mode, this CP is the 525th one) is output as a vertical synchronizing pulse g as shown in FIG.

This vertical synchronization pulse g output backward type flip-flop 53
Since the Q output of the RS flip-flop 51 becomes L level, when the vertical synchronizing signal is no longer inputted in this state, the set terminal of the RS flip-flop 51 becomes L level and the reset terminal becomes H level, and is reset.

As a result, the Q output of the D-type flip-flop 52 is at the L level as shown in FIG. The Q output of 53 becomes L level as shown in FIG.

This state continues as long as the RS flip-flop 51 is reset.

If noise is mixed in immediately before the vertical synchronization signal, and if the leading edge of this noise is two or more intervals of CP from the leading edge of the vertical synchronization signal, and the trailing edge of the noise is one or more intervals of CP,
Regardless of the noise mixing period, the vertical synchronization pulse g is as shown in Fig. 9G.
It is output in phase during normal operation as shown by the solid line.

In FIG. 9B, the pulse indicated by a broken line indicates the noise mixed in just before the vertical synchronization signal, and this noise causes the Q output C, the D type flip flop output d, and the D type flip flop output f of the RS flip flop 51. , and the output g of the AND gate 55 become pulses shown by broken lines in FIG. 9, C, D, E, F, and G, respectively.

However, when the regular vertical synchronization signal comes in after that,
In the conventional circuit 24, no vertical synchronizing pulse is output as shown in FIG.
Since the regular vertical synchronization pulse g shown by the solid line is generated,
The phase comparison operation in the phase comparison circuit 20 can be performed normally.

In addition, the vertical synchronization signal is R
The next CP at the time the S flip-flop 51 is set
A pulse corresponding to the H level period of one section is generated as a vertical synchronizing pulse g at the output of the AND gate 55, that is, at the output of the pulse shaping circuit 48 which forms the essential part of the circuit of the present invention.

Next, to explain the operation of the RS flip-flop 49, in this embodiment, the Q output signal e of the above-mentioned flip-flop 53 is applied to the set terminal of the RS flip-flop 49, and the reset terminal of the RS flip-flop 49 is applied to the Q output signal e of the above-mentioned flip-flop 53. The Q output pulse of the RS flip-flop 31, which is the reset pulse of the counter 23, is applied.

As described above with reference to FIG. 9E, the signal e is from the falling edge of CP after the RS flip-flop 51 is set to the falling edge of CP after the RS flip-flop 51 is reset. It is a pulse with a width of H level, and at the time of its rise, the RS flip-flop 4
9 is set.

On the other hand, the reset pulse of the counter 23 is a pulse outputted from the terminal a4 when the counter 23 shown in FIG. 7 counts CP by 525.
30 and RS flip-flop 31, so the rising point of this reset pulse is at terminal a4.
It is slightly delayed from the rising edge of the output pulse or the vertical synchronizing pulse g.

Moreover, this reset pulse is applied to the RS flip-flop 31.
Since the pulse CP obtained by inverting the polarity of CP by the inverter 60 is applied to the reset terminal of the RS flip-flop 31, the RS flip-flop 31 is reset at the falling edge of CP within the same period after being set.

Therefore, the reset pulse of the counter 23 is h as shown in FIG.
It becomes as shown.

The RS flip-flop 49 shown in FIGS. 7 and 8 is
It is reset at the rising edge of the above reset pulse h.

Therefore, the Q output signal of the RS flip-flop 49 is applied to the count input terminal of the counter 35 in the form of a negative pulse generated once per vertical scanning period, as shown by i in FIG.

Now suppose that the pulse shaping circuit 48 is activated due to noise.
Even if a plurality of pulses e applied to the set terminal of the RS flip-flop 49 occur within one vertical scanning period, the reset pulse h of the counter 23, which is always generated and outputted once within one vertical scanning period, Once set by the next incoming pulse e after being reset, the RS flip-flop 49 will continue to be set unless the next reset pulse h comes in, so the RS flip-flop 49 will not malfunction due to noise. Only one pulse is generated at the Q output terminal of the pull-up 49 within one vertical scanning period.

In addition, in the circuit of this embodiment, when the vertical synchronization signal is not supplied, the pulse shaping circuit 48 does not operate and the RS flip-flop 49 is not set, so that the pulse shaping circuit 48 is not applied to the count input terminal of the counter 35. Pulses no longer occur.

Therefore, the counting operation of the counter 35 is stopped, and the countdown mode continues if it was in the countdown mode, and the sync mode if it was in the sync mode.

Once vertical synchronization is established from the above operations and the countdown mode is entered, the countdown mode will continue even if the vertical synchronization signal is not input as long as the phase of the input vertical synchronization signal does not change. Vertical synchronization will be achieved.

The mutually opposite phase pulses shown in FIG. 9 J and K, respectively, are RS
Phase comparison pulses j and k outputted from the Q and Q terminals of the flip-flop 37 are shown, and have the phase relationship with the above-mentioned CP and pulse b-i as shown in A to ■ in the figure.

Figure 9A- shows the pulse waveforms of various parts during the countdown mode, which is set by the reset pulse h mentioned above and reset by the pulse output from the a3 terminal of the counter 23 when counting the 25th CP. The Q output signal l of the RS flip-flop 38 (shown in FIG. 9) is supplied to the vertical deflection circuit 13 as a vertical synchronizing pulse.

In the circuit shown in FIG. 8, the clock inputs of the D-type flip-flops 52 and 53 may be two-phase CPs with different rising edges.

Further, although the CP has a frequency twice that of the horizontal synchronizing signal in the above embodiment, it may be an even number.

Furthermore, the input to the set terminal of the RS flip-flop 49 may be either the vertical synchronizing signal or the vertical synchronizing pulse g output from the integrating circuit 6.

However, when the vertical synchronization pulse g is input to the set terminal of the RS flip-flop 49, the RS flip-flop 49 needs to be a reset priority type RS flip-flop.

Furthermore, in the circuit of the present invention, a D-type flip-flop and an R
It goes without saying that the S flip-flop includes flip-flops that can be configured to be equivalent to JK flip-flops depending on how they are connected.

Furthermore, in the embodiment circuit shown in FIG. 7, in order to make the operation more stable, a CR is used to delay the Q output of the RS flip-flop 31 (however, by a time smaller than the H level pulse width of CP). Alternatively, an integrating circuit consisting of the following may be provided.

In any case, the circuit of the present invention is not limited to the above-described embodiment, and various other modifications are possible.

As described above, the vertical synchronization circuit according to the present invention is a countdown type vertical synchronization circuit that performs waveform shaping to generate and output a first pulse from a vertical synchronization signal separated from a composite video signal and a clock pulse for phase comparison. The circuit includes a flip-flop set by the vertical synchronization signal to output a pulse synchronized with the clock pulse as the first pulse every time the vertical synchronization signal and noise that may be mixed therein are input. , the first and second D-type flips are connected in cascade with the 70 tabs, respectively;
The clock pulses having different phases from each other are supplied to the clock input terminals of the first and second D-type flip-flops, and the output pulses of the first and second D-type flip-flops are logically synthesized. Since the configuration is configured to output the first pulse, even if noise is mixed immediately before the vertical sync signal, as long as the vertical sync signal is input, a pulse synchronized with the normal vertical sync signal can be reliably obtained.
Vertical synchronization has significantly improved noise resistance in countdown mode compared to conventional methods, and there is no limit to the pulse width of the vertical synchronization signal, allowing the first pulse to be generated stably, resulting in stable reproduced images. A vertical synchronizing signal or a shaped pulse is input to the count input terminal of a second counter that can stably generate pulses and is provided in the phase comparator circuit and receives pulses that are generated and output once every vertical scanning period as a count input. Since the output pulse of the flip-flop is supplied with the input pulse and the pulse that resets the first counter that counts the clock pulse, once vertical synchronization is established and the countdown mode is established, the signal can be output. As long as the phase of the vertical synchronization signal on the side does not fluctuate, the countdown mode operation continues and stable vertical synchronization can be achieved.From the above, it is possible to improve synchronization stability when the vertical synchronization signal is unstable and to improve noise resistance in weak electric fields. It has many features such as improvement.

[Brief explanation of drawings]

Figure 1 is a block diagram centered on the deflection system in a television receiver, Figure 2 is a block diagram showing a general countdown type synchronization circuit, and Figure 3 is an example of a conventional vertical synchronization circuit. Circuit system diagram, Fig. 4 is a circuit diagram showing an example of the main part of Fig. 3, Fig. 5 A-C1 Fig. 6 A-C
4 is a time chart for explaining the operation, and FIG. 7 is a circuit system diagram showing an embodiment of the vertical synchronization circuit according to the present invention.
FIG. 8 is a circuit diagram showing an embodiment of the main part of the circuit of the present invention, and FIGS. 9A to 9L are time charts for explaining the operations of FIGS. 7 and 8, respectively. 1... Composite video signal input terminal, 6...
Integrating circuit, 17.23.35... Counter, 1
8... Phase comparison pulse shaping circuit, 19...
... Waveform shaping circuit, 20 ... Phase comparison circuit, 2
1...Switching circuit, 24.48...Pulse shaping circuit, 26.31.37, 38, 49.51...
...RS flip-flop, 36°42~45...
...T-type flip-flop, 52, 53...
...D type flip-flop.

Claims (1)

[Scope of utility model registration request] A waveform shaping circuit that counts clock pulses whose frequency is selected to be an even multiple of the horizontal scanning frequency by a first counter, and outputs a first pulse from the vertical synchronization signal separated from the composite video signal and the clock pulse. output and the first
is generated from the second pulse output from the first counter when the count value of the counter reaches a predetermined value related to the ratio of the horizontal scanning period to the vertical scanning period of the composite video signal. A phase comparison circuit including a second counter compares the phase with a phase comparison pulse synchronized with the clock pulse, and the first counter is reset by the first pulse when the input signal phases of the phase comparison circuit do not match. and a second reset mode in which the input signal phase of the phase comparator circuit is reset by the second pulse when the input signal phase of the phase comparator circuit matches, and is reset in one vertical scanning period. The output of the 20th counter, which receives a pulse generated and outputted once every time and a pulse that resets the first counter as count inputs via a first flip-flop, causes the first counter to perform the phase comparison. When the input signal phases of the circuit do not match continuously for a predetermined vertical scanning period, the second reset mode is switched to the first reset mode; on the other hand, when the input signal phases of the circuit match continuously for the predetermined vertical scanning period, the first reset mode is switched. By switching from the reset mode to the second reset mode, the waveform shaping circuit is separated from the composite video signal in the countdown type vertical synchronization circuit in which the first counter generates and outputs pulses synchronized with the vertical synchronization signal. a second flip-flop that is set by the vertical synchronization signal to output a pulse synchronized with the clock pulse as the second pulse every time the vertical synchronization signal and noise that may be mixed therein are input; , first and second D-type flip-flops are connected in cascade, respectively, and the clock pulses having different phases are supplied to the clock input terminals of the first and second D-type flip-flops, and the output pulses of the first D-type flip-flop are logically synthesized to generate the first
A vertical synchronization circuit configured to output pulses.