JP2838878B2 - Pulse generation circuit for solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generation circuit of a solid-state imaging device that generates a horizontal transfer pulse for driving a solid-state imaging device in, for example, a solid-state imaging device. It is.

[Conventional technology]

At present, imaging devices using solid-state imaging devices are rapidly spreading, and further improvement in image quality is desired, and development thereof is being actively pursued.

Hereinafter, a conventional solid-state imaging device will be described with reference to the drawings.

FIG. 3 is a block diagram showing a configuration of the solid-state imaging device. In FIG. 3, reference numeral 24 denotes a solid-state imaging device constituted by a CCD device or the like. 21, a pulse generating circuit, the master clock [4 times the frequency of, for example, the color subcarrier (frequency f _sc) (hereinafter, 4f _sc abbreviated) signal], and the horizontal transfer pulse for driving the solid-state imaging device 24 φH and a vertical transfer pulse φV are generated. 22 is a synchronization signal generation circuit,
The horizontal drive signal HD and the vertical drive signal V are output based on the _4fsc master clock output from the pulse generation circuit 21.
Generates pulses required for signal processing, such as D, and other synchronization signals. 23 is a drive circuit, a pulse generation circuit
The horizontal transfer pulse φH and the vertical transfer pulse φV output from 21 are converted into voltage levels necessary for driving the solid-state image sensor 24, and are converted into a horizontal transfer drive pulse φH ′ and a vertical transfer drive pulse φV ′. Give to.

Here, the pulse generating circuit 21 for driving the solid-state imaging device 24 of horizontal 300H and vertical 240V will be specifically described with reference to FIG.

First, in the oscillator 1, the color subcarrier of 8 times the frequency (hereinafter, 8f _sc abbreviated) generates a pulse of, for the first frequency divider 2 and 5 divide the divided by two pulses of this 8f _sc Second
To the frequency dividing circuit 6. FIG. 5 (a) shows the pulse waveform of 8 _fsc .

The 4 _fsc pulse output from the first frequency dividing circuit 2, that is, the master clock, is sent from the output terminal 9 to the synchronization signal generating circuit 22 through the output buffer 3. The synchronizing signal generation circuit 22 generates a horizontal drive signal HD and a vertical drive signal VD based on the master clock, and supplies them to the pulse generation circuit 21. FIG. 5 (b) shows the 4f _sc pulse waveform.
Shown in

On the other hand, the pulse of (8/5) f _sc output from the second frequency dividing circuit 6 is input to a waveform shaping circuit, that is, a horizontal transfer pulse generation logic circuit 7, and the horizontal transfer pulse generation logic circuit 7 A horizontal transfer pulse φH is generated and sent from the output terminal 11 to the drive circuit 23 through the output buffer 8. (8/5) f _sc output from the second frequency divider 6
5 (c) is shown in FIG.

The circuit for generating the vertical transfer pulse φV is not shown because it is not directly related to the present invention.

[Problems to be solved by the invention]

However, in the configuration of FIG.
As can be seen from FIGS. 8B and 8C, the edge of the 4f _sc pulse at the rising edge of the (8/5) f _sc pulse alternates between rising and falling. Therefore, the rising edge of the (8/5) _fsc pulse is affected by the change in the current flowing through the output buffer 3 of the 4 _fsc pulse, and every one cycle as shown by the broken line in FIG. The shape is different. As a result, (8/5) This affects the horizontal transfer pulse φH is generated by the horizontal transfer pulse generation logic circuit 7 on the basis of the pulses of f _sc is Oyobi, the rising edge of the horizontal transfer pulse φH is FIG. 5 (C)
This is similar to the (8/5) _fsc pulse shown in FIG. When the solid-state imaging device 24 is driven by the horizontal transfer pulse φH, vertical stripes in which the brightness is changed by 1 bit in the horizontal direction are generated in the image captured by the solid-state imaging device 24.

Therefore, it is an object of the present invention to provide a frequency dividing output of the first frequency dividing circuit which appears at the same timing as the rising edge of the frequency dividing output of the second frequency dividing circuit. Of the rising edge of the divided output of the second frequency dividing circuit due to the switching between rising and falling every one cycle of the second frequency dividing circuit for each cycle of the divided output of the second frequency dividing circuit. An object of the present invention is to provide a pulse generation circuit of a solid-state imaging device that can prevent the occurrence of a pulse.

[Means for solving the problem]

A pulse generating circuit of a solid-state imaging device according to the present invention includes a first frequency dividing circuit for inputting an output signal of an oscillator and a second frequency dividing circuit, and the _first frequency dividing circuit outputs a frequency f ₁ from the _first frequency dividing circuit. 1 is output, the first frequency-divided output is input to a synchronization signal generating circuit that derives a synchronization signal from the first frequency-divided output, and the frequency f ₂ is output from the second frequency-divider circuit. Is output, and the second frequency-divided output is input to a pulse generation logic circuit that derives a horizontal transfer pulse from the second frequency-divided output. When n is an integer, f ₂ = 2f ₁ (1 + 2n), wherein the dividing ratio is set so as to satisfy the following relationship: a first dividing output from the first dividing circuit and the first dividing output from the first dividing circuit. And a phase-inverted output of the frequency-divided output.

[Action]

According to the configuration of the present invention, the change in the current flowing through the output buffer due to the divided output of the first divider circuit affects the divided output of the second divider circuit. 1
The effect that differs for each cycle is that the change in the current flowing through the output buffer due to the output obtained by inverting the phase of the first divided output affects the divided output of the second frequency dividing circuit. Each cycle is just offset by a different effect.
That is, the influence of the frequency-divided output of the first frequency-divided circuit and the output obtained by inverting the phase of the first frequency-divided output on the frequency-divided output of the second frequency-divided circuit depends on the frequency division of the second frequency-divided circuit. The cycle output becomes the same every cycle. As a result, when, for example, a horizontal transfer pulse for driving the solid-state imaging device is generated based on the divided output of the second frequency dividing circuit, this horizontal transfer pulse is also uniform for all bits, and The occurrence of vertical stripes in the image captured in step (1) is prevented.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1 and FIG.

FIG. 1 shows a horizontal 300H and a vertical 2 in one embodiment of the present invention.
FIG. 4 shows a circuit diagram of a pulse generation circuit 21 ′ of a 40 V solid-state imaging device. This pulse generation circuit 21 'is used in place of the pulse generation circuit 21 in the solid-state imaging device shown in FIG.

First, the oscillator 1 generates a pulse of 8f _{sc in} the same manner as in FIG. 4, and the first frequency dividing circuit 2 _divides the pulse of 8f _sc by 2 and the second frequency dividing circuit 6 divides 5 by 5 To each of. FIG. 2 (a) shows the pulse waveform of 8 _fsc .
Shown in

The pulse of 4f _sc output from the first frequency dividing circuit 2, that is, the master clock, is sent from the output terminal 9 to the synchronizing signal generating circuit 22 through the output buffer 3 as in FIG. The synchronizing signal generation circuit 22 generates a horizontal drive signal HD and a vertical drive signal VD based on the master clock, and supplies them to the pulse generation circuit 21. FIG. 2 (b) shows the 4f _sc pulse waveform.

The following part is not shown in FIG. 4 and is a main part of the present invention. The pulse of 4f _sc output from the first frequency dividing circuit 2 is a phase inverting circuit 4 composed of an inverter or the like.
And the phase inversion circuit 4 inverts the phase of the pulse of 4f _sc , that is, has a phase difference of π
Is output and output through an output buffer 5.
Will be sent to 10. FIG. 2 (c) shows the pulse waveform of this triangle.

On the other hand, the (8/5) _fsc pulse output from the second frequency dividing circuit 6 is input to a horizontal transfer pulse generation logic circuit 7 which is a waveform shaping circuit, as in FIG. The horizontal transfer pulse φH is generated by the pulse generation logic circuit 7 and sent from the output terminal 11 to the drive circuit 23 through the output buffer 8. FIG. 2D shows a pulse waveform of (8/5) f _sc output from the second frequency dividing circuit 6.

In the pulse generation circuit configured as described above, the pulse of 4 _fsc in FIG. 2B and the pulse in FIG.
Is equal to π, the sum of the current flowing through the output buffer 3 of the 4 _fsc pulse and the current flowing through the output buffer 5 of the pulse of ▼ is always constant at the edge. That is, the change in the current flowing through the output buffer 3 due to the 4 _fsc pulse output from the first frequency divider 2 is output from the second frequency divider 6 (8 /
5) on the pulse f _sc of the second frequency divider 6 (8/5) f _sc
Is different for each period of the pulse of the first frequency dividing circuit 2.
The output of the phase inverting circuit 4 having a phase difference of π with respect to the pulse of 4f _sc , that is, the change in the current flowing through the output buffer 5 due to the pulse of ▼ changes the (8/5) f _{sc of} the second frequency dividing circuit 6. Of the second frequency dividing circuit 6 (8 /
5) Each cycle of the _fsc pulse is just offset by a different effect. Therefore, the influence of the 4 _fsc pulse on the rising edge of the (8/5) _fsc pulse, which has been a problem in the conventional pulse generation circuit, becomes uniform for each period of the (8/5) _fsc pulse. As a result, for example, when a horizontal transfer pulse φH for driving the solid-state imaging device 24 is generated based on the (8/5) _fsc pulse of the second frequency dividing circuit 6, the horizontal transfer pulse φH is also changed. All the bits are uniform, and it is possible to prevent the occurrence of vertical stripes in the image picked up by the solid-state image sensor 24, and it is possible to significantly improve the image quality of the pixels picked up by the solid-state image sensor 24.

In the above embodiment, since the first frequency divider 2 outputs a pulse of 4f _sc, second frequency divider 6 outputs a pulse (8/5) f _sc, the first divider Frequency of the divided output of the circuit
The relationship between f ₁ and the frequency f _{2 of the} divided output of the second divider circuit is
a n = 2, f ₂ = but 2f was _1/5, even when n is other than 2 integer, the frequency f _1,
The present invention can be applied if f ₂ has a relationship represented by f ₂ = 2f ₁ / (1 + 2n).

〔The invention's effect〕

According to the pulse generation circuit of the solid-state imaging device of the present invention,
Since the first frequency divider outputs a first frequency divided output and an output obtained by inverting the phase of the first frequency divided output, the first frequency divided circuit outputs the first frequency divided output. The effect of the second divided output of the second divider circuit on the current flowing through the output buffer and the current obtained by inverting the phase of the first divided output and flowing through the output buffer cancel each other, and the second The same can be obtained in each cycle of the second divided output of the divider circuit. As a result, the edge of the first frequency-divided output of the first frequency-divider circuit that appears at the same timing as the rising edge of the second frequency-divided output of the second frequency-divider circuit is equal to the second frequency-divided output of the second frequency-divider circuit. The rising edge of the second divided output of the second frequency dividing circuit is switched between rising and falling every cycle of the divided output of the second frequency dividing circuit, and the shape of the rising edge of the second divided output of the second frequency dividing circuit is changed. 1
It can be prevented from being different for each cycle. As a result, the occurrence of vertical stripes in the image captured by the solid-state imaging device can be prevented, and the image quality can be significantly improved. The practical effect is extremely large.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a pulse generation circuit according to an embodiment of the present invention, FIG. 2 is a time chart of each part in FIG. 1, and FIG. 3 is a block showing an example of a configuration of a conventional solid-state imaging device. FIG. 4 is a block diagram showing an example of the configuration of a conventional pulse generation circuit, and FIG. 5 is a time chart of the fourth components. DESCRIPTION OF SYMBOLS 1 ... Oscillator, 2 ... 1st frequency divider circuit, 3 ... Output buffer,
4 phase inversion circuit, 5 output buffer, 6 second frequency divider circuit, 7 horizontal transfer pulse generation logic circuit

Claims (1)

(57) [Claims] 1. A and a first frequency divider and second divider circuits for receiving the output signal of the oscillator, the first divided output is the output of the frequency f ₁ from the first frequency divider The first frequency-divided output is input to a synchronizing signal generation circuit that derives a synchronizing signal from the first frequency-divided output, and the second frequency-divided circuit outputs a second frequency-divided _second frequency-divided output. And the second frequency-divided output is input to a pulse generation logic circuit that derives a horizontal transfer pulse from the second frequency-divided output. When n is an integer, f ₂ = 2f ₁ (1 + 2n) A pulse generation circuit for a solid-state imaging device having a frequency division ratio set so as to satisfy a relationship, wherein the first frequency division circuit inverts the first frequency division output and the first frequency division output from the first frequency division circuit. A pulse generating circuit for a solid-state imaging device, the pulse generating circuit performing the following operations.