JPH06113185A - Image pickup device - Google Patents

Abstract

PURPOSE:To always obtain a normal video image without necessitating adjustment corresponding to cable length in respect of a video camera in which a camera head using a solid state image pickup element consisting of a charge coupled element and a signal processing part are formed into separate bodies, and in addition, camera head and the signal processing part are connected by a cable. CONSTITUTION:A signal processing part 2 is provided with a counter circuit 21 so as to count the number of pulses of a drive signal of the solid state image pickup element 9 fed back through the cable 7, and by resetting a timing pulse generating means 12 when a count number exceeds a prescribed number, the phase of an output signal after being transmitted from the solid state image pickup element 9 to the signal processing means through the cable 7 and the phase of a timing pulse sent to the signal processing means can be synchronized with each other, and thus, a video camera 1 capable of obtaining always the normal video image without necessitating the adjustment corresponding to the length of the cable 7 can be realized.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Field of Industrial Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Action (FIG. 1) Example (FIG. 1) Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup device, and more particularly, to a camera head for picking up an image by using a solid-state image pickup device composed of a charge coupled device (hereinafter referred to as CCD) and an output signal of the CCD (hereinafter Is referred to as a CCD output signal) and a signal processing unit for performing signal processing is separately provided, and is suitable for application to an image pickup apparatus in which both are connected by a cable.

[0003]

2. Description of the Related Art In an image pickup apparatus of this type, a signal is transmitted and received through a cable so that a phase is generated between a CCD drive signal transmitted from a signal processing section to a camera head and a timing pulse formed in the signal processing section. A shift may occur, and conventionally, as a means for preventing this phase shift, it has been proposed to provide a so-called PLL (phase-locked loop) circuit in a part of the signal processing unit (Japanese Patent Laid-Open No. 63-232582). ).

The PLL circuit uses a part of CCD drive pulses from pulse signals (hereinafter collectively referred to as CCD drive pulse signals) for driving the CCD such as vertical transfer pulses and horizontal transfer pulses sent to the camera head. The signal is fed back, and the CCD driving pulse signal is adjusted so that the phase of the fed back CCD driving pulse signal and the reference pulse formed in the signal processing unit are synchronized, whereby the cable between the camera head and the signal processing unit is adjusted. The CCD can be accurately driven by compensating for the phase shift of a high frequency signal such as a transfer pulse due to transmission and reception of a signal via the CCD.

[0005]

However, in this type of image pickup device, although the CCD can be driven correctly, the C
A phase error occurs in the signal output from the CD through the cable and the signal in the signal processing unit, so that color separation and sample hold are performed at regular timing with respect to the CCD output signal supplied from the CCD in the signal processing unit. Since this is not possible, there is a problem in that a correct video signal cannot be obtained. The present invention has been made in consideration of the above points, and a camera head and a signal processing unit using a solid-state imaging device including a charge-coupled device are separately formed, and the camera head and the signal processing unit are connected by a cable. As for the video camera, an attempt is made to propose a video camera that can always obtain a regular image without requiring adjustment according to the cable length.

[0006]

In order to solve such a problem, according to the present invention, a camera head 8 using a solid-state image sensor 9 composed of a charge-coupled device and a signal processing means for an output signal S10 output from the solid-state image sensor 9. The signal processing unit 2 having 15 is separately configured, and a cable 7 is connected between the two, and a drive signal S4 for driving the solid-state imaging device 9 from the signal processing unit 2 via the cable 7 is supplied to the solid-state imaging device 9. In the image pickup device 1 for outputting, the drive signal S4 fed back from the solid-state image pickup device 9 to the signal processing unit 2 via the cable 7 and the drive signal synchronizing means 3 for synchronizing the phase of the timing pulse in the signal processing unit 2; First oscillating means 11 for generating an oscillating pulse of a frequency, and first timing pulse forming for forming and outputting a clock signal S20 based on the oscillating pulse. The stage 12, the synchronizing signal generating means 20 for forming the reset pulse of the driving signal S4 based on the clock signal S20 and outputting the reset pulse to the driving signal synchronizing means 3 and the signal processing means 15, and the driving signal S4 fed back via the cable 7. The counter 21 is provided for counting the number of pulses and for resetting the timing pulse generating means 12 to send the timing pulse for signal processing to the signal processing means 15 when the counted number exceeds a predetermined number.

Further, in the present invention, the drive signal synchronizing means 3 is provided with the reference pulse signal S serving as a frequency reference of the drive signal S4 supplied from the first timing pulse forming means 12.
7 and the phase of the drive signal S4 fed back from the camera head 8 via the cable 7, the phase comparison means 1
0, a filter 13 for extracting a low frequency component of the output signal S8 of the phase comparison means 10, a second oscillation means 4 for generating an oscillation pulse of a predetermined frequency according to the voltage of the low frequency component, and an oscillation pulse. The second timing pulse generating means 5 is formed by dividing the frequency to form a plurality of types of drive signals S4.

[0008]

The counter 21 counts the number of pulses of the drive signal S4 fed back through the cable 7, and when the counted number exceeds a predetermined number, the first timing pulse generating means 12 is reset and the signal processing means 15 is provided. Since the timing pulse for signal processing is transmitted, the phase of the output signal S10 after being transmitted from the solid-state imaging device 9 to the signal processing means 15 via the cable 7 and the phase of the output signal S10 are transmitted to the signal processing means 15. The phase of the timing pulse can be synchronized, and thus a video camera that can always obtain a normal image without requiring adjustment according to the length of the cable 7 can be realized.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes a video camera as a whole, and a voltage controlled oscillation circuit 4 (VCO) of a drive pulse synchronization circuit unit 3 in a signal processing unit 2 oscillates at a predetermined frequency in an initial state. The signal S1 is supplied to the timing generator 5. The timing generator 5 divides the oscillation signal S1 to form a plurality of types of CCD drive pulses, and outputs these to the vertical reset pulse signal S2.
Alternatively, the drive pulse signals S4 are sequentially output according to the input of the horizontal reset pulse signal S3.

At this time, the drive pulse signal S4 is supplied via a cable 7 consisting of a plurality of signal lines 6 to a CCD 9 of a camera head 8 provided in a housing separate from the signal processing unit 2, and as a result, the CCD 9 drives pulses. It is driven according to the signal S4. In this case, a part of the horizontal transfer pulse signal S4A of the drive pulse signal S4 is sent from the camera head 8 as the feedback horizontal transfer pulse signal S5 to the phase comparison circuit 10 via the signal line 6A.

At this time, the phase comparison circuit 10 supplies the oscillation signal S6 of a predetermined frequency output from the voltage controlled oscillation circuit 11.
A reference horizontal transfer pulse, which is formed by the timing generator 12 based on the above and serves as a phase reference of the horizontal transfer pulse signal S4A, is supplied as the reference horizontal transfer pulse signal S7.
Thus, the phase comparison circuit 10 compares the reference horizontal transfer pulse signal S7 and the feedback horizontal transfer pulse signal S5 and generates a signal having a voltage corresponding to the phase difference, and compares the reference horizontal transfer pulse signal S7 with the feedback horizontal transfer pulse signal S5.
It is sent to the low-pass filter circuit 13 as 8. The low-pass filter circuit 13 converts the comparison signal S8 into a direct current and then sends it as a direct current comparison signal S9 to the voltage controlled oscillation circuit 4, and the voltage controlled oscillation circuit 4 receives the direct current comparison signal S9.
The oscillation frequency of the oscillation signal S1 is changed according to the signal level of

As a result, the frequency of the CCD drive pulse signal S4 output by the timing generator 5 changes, and the phase of the CCD drive pulse signal S4 is phase-locked with the reference horizontal transfer pulse signal S7 in the signal processing unit 2, CCD9
It is possible to synchronize the timing for driving the and the operation timing in the signal processing unit 2. On the other hand, in the timing generator 12, the clock signal S20 is generated based on the oscillation signal S6 and is sent to the synchronizing signal generating circuit 20, and the synchronizing signal generating circuit 20 generates the vertical reset pulse and the horizontal signal based on the clock signal S20. Various timing pulses such as a reset pulse are formed.

In this case, the vertical reset pulse is sent to the timing generators 5 and 12 as the vertical reset pulse signal S3, and the other timing pulses are sent as the timing pulse signal S21 to the signal processing circuit 1.
5 is sent. Therefore, in the signal processing circuit 15,
The CCD output signal S11 input from the CCD 9 via the signal line 6B is processed by the timing pulse signal S21. On the other hand, the horizontal reset pulse is sent to the timing generator 5 and the signal processing circuit 15 as the horizontal reset pulse signal S3.

Here, a part of the feedback horizontal transfer pulse signal S5 is input to the counter circuit 21, and as a result, the counter circuit 21 counts the number of horizontal transfer pulses based on the feedback horizontal transfer pulse signal S5. The number of pulses is pre-programmed as preset information C
When the number of pixels for one horizontal line (for example, 768 pixels) of the CD 9 is exceeded, an overflow pulse is sent to the tamming generator 12 as a horizontal reset signal S22. The timing generator 12 resets in response to the input of the horizontal reset signal S22, and various timing pulses such as sample hold and color separation pulses are used as the timing pulse signal S30 in the signal processing circuit 1.
5, the signal processing circuit 15 outputs the CCD output signal S10.
Is processed based on the timing pulse signal S30 from the timing generator 12. As a result, the signal processing circuit 15 can perform signal processing such as color separation and sample hold at the correct timing with respect to the CCD output signal S10.

In the timing generator 5, the counter circuit 2 is activated when the video camera 1 is powered on.
By resetting the counter circuit 21 by sending the initial setting pulse signal S40 to 1, the counter circuit 21 is prevented from erroneous counting.

In the above structure, the drive pulse synchronization circuit section 3 is horizontally arranged so that the phase of the feedback horizontal transfer pulse matches the phase of the reference horizontal transfer pulse based on the feedback horizontal transfer pulse signal S5 and the reference horizontal transfer pulse signal S7. A CCD drive signal S4 for adjusting the output frequency of the transfer pulse signal S4A and for driving the CCD 9 based on the vertical reset signal S2 and the horizontal reset signal S3 formed at the timing of the timing generator 12 in the synchronizing signal generation circuit 20. Is output, the CCD 9 is driven in synchronization with the timing of the signal processing unit 2.

In addition to this, the counter circuit 21 uses the signal line 6
The number of pulses of the feedback horizontal transfer pulse signal S5 fed back via A is counted, and when the count exceeds the number of pulses of one horizontal line of the CCD 9 programmed in advance, the horizontal reset signal is sent to the timing generator 12. By sending S22 and resetting, the phase of the timing pulse signal S30 output from the timing generator 12 and the phase of the CCD output signal S10 after being transmitted from the CCD 9 via the signal line 6B are synchronized. .

With the above arrangement, a part of the feedback horizontal transfer pulse signal S5 is sent to the counter circuit 21 to count the number of pulses, and the number of counts is the number of pixels for one horizontal line of the CCD 9 programmed in advance. When the counter circuit 21 resets the timing generator 12 when the value exceeds the limit, when there is no loss such as DC resistance or frequency characteristic deterioration in each signal line 6 of the cable 7, in principle there is no cable. CCD without being aware of the length
The CCD output signal S10 transmitted from the signal processing circuit 9 to the signal processing circuit 15 via the cable 7 and the timing pulse signals S21 and S30 in the signal processing unit 2 can be synchronized, and thus fine adjustment according to the cable length. It is possible to always obtain a video signal at a regular timing without requiring.

In the above embodiment, the case where the counter circuit 21 overflows when the count number exceeds 768, for example, is described. However, the present invention is not limited to this, and the count cycle of the counter circuit 21 is not limited to this. The present invention can be applied to various television systems such as the NTSC system and the PAL system and various CCDs by adjusting.
Further, in the above embodiment, the CCD 9 to the signal line 6B
The case where the PLL circuit is used as a method of synchronizing the phase of the CCD output signal S10 after being transmitted to the signal processing circuit 15 via the signal processing circuit 2 with the phase of the timing pulse in the signal processing unit 2 has been described. Is not limited to this,
Various other methods can be applied.

[0021]

As described above, according to the present invention, the camera head using the solid-state image pickup device including the charge-coupled device and the signal processing section having the signal processing means for the output signal output from the solid-state image pickup device are separately provided. In the imaging device configured and connected with a cable between the two, a counter circuit is provided in the signal processing unit, the number of pulses of the drive signal returned through the cable in the counter circuit is counted, and the counted number is a predetermined number. When it exceeds, by resetting the timing pulse generating means to send the timing pulse of the signal processing to the signal processing means, the output signal after being transmitted from the solid-state imaging device to the signal processing means via the cable It is possible to synchronize the phase with the phase of the timing pulse sent to the signal processing means, and thus to the length of the cable. Flip adjustment always possible to realize a video camera obtained legitimate video without the need for a.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal synchronization processing system in a CCD and a signal processing unit of a video camera according to the present invention.

[Explanation of symbols]

1 ... video camera, 2 ... signal processing unit, 3 ... drive pulse synchronizing circuit unit, 4, 11 ... voltage control oscillation circuit, 5,
12 …… Timing generator, 6, 6A, 6B ……
Signal line, 7 ... Cable, 8 ... Camera head, 9 ...
CCD, 10 ... Phase comparison circuit, 13 ... Low-pass filter, 15 ... Signal processing circuit, 20 ... Synchronous signal generation circuit, S2 ... Vertical reset pulse signal, S3 ... Horizontal reset pulse signal, S4 ... CCD Drive pulse signal, S
4A ... horizontal transfer pulse signal, S5 ... feedback horizontal transfer pulse signal, S7 ... reference horizontal transfer pulse signal, S10 ...
... CCD output signal, S20 ... clock signal, S21,
S30: Timing pulse signal, S22: Reset signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Isao Kajino 539-5 Higashi-Asakawa-cho, Hachioji-shi, Tokyo Within CIS

Claims (2)

[Claims] 1. A camera head using a solid-state imaging device composed of a charge-coupled device and a signal processing unit having a signal processing unit for processing an output signal output from the solid-state imaging device are separately configured, and a cable is provided between the two. In an imaging device that outputs a drive signal for driving the solid-state imaging device from the signal processing unit via the cable to the solid-state imaging device, the solid-state imaging device returns to the signal processing unit via the cable. Drive signal synchronizing means for synchronizing the phase of the generated drive signal and the timing pulse in the signal processing section, first oscillating means for generating an oscillating pulse of a predetermined frequency, and forming a clock signal based on the oscillating pulse. And a first timing pulse forming means for outputting the reset pulse of the drive signal based on the clock signal. And the synchronizing signal generating means for outputting to the driving signal synchronizing means and the signal processing means, and the number of pulses of the driving signal fed back through the cable, and when the counted number exceeds a predetermined number, the timing pulse is generated. An image pickup apparatus, comprising: a counter for resetting the means to send a timing pulse for signal processing to the signal processing means. 2. The drive signal synchronizing means is a phase of a reference pulse signal which is a frequency reference of the drive signal supplied from the first timing pulse forming means,
And a phase comparison means for comparing the phases of the drive signals returned from the camera head through the cable, a filter for extracting a low frequency component of the output signal of the phase comparison means, and a voltage for the low frequency component according to the voltage. An image pickup apparatus comprising: a second oscillating means for generating an oscillating pulse having a predetermined frequency; and a second timing pulse generating means for dividing the oscillating pulse to form a plurality of types of the drive signals.