JP3310027B2 - Imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. INDUSTRIAL APPLICABILITY BACKGROUND OF THE INVENTION Problems to be Solved by the Invention Means for Solving the Problems (FIG. 1) Function (FIG. 1) Embodiment (FIG. 1) Effect of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus, and more particularly to a camera head adapted to pick up an image using a solid-state image pickup device comprising a charge-coupled device (hereinafter referred to as a CCD) and an output signal of the CCD (hereinafter referred to as CCD). Is referred to as a CCD output signal) and a signal processing unit for performing signal processing is provided separately, and the present invention is suitably applied to an imaging apparatus in which both are connected by a cable.

[0003]

2. Description of the Related Art In an image pickup apparatus of this type, a signal is transmitted / received via a cable to cause a phase shift between a CCD drive signal transmitted from a signal processing unit to a camera head and a timing pulse formed in the signal processing unit. A shift may occur, and as a means for preventing this phase shift, it has been proposed to provide a so-called PLL (phase-locked loop) circuit in a part of the signal processing unit (Japanese Patent Laid-Open No. 63-232582). ).

The PLL circuit includes a part of a CCD driving pulse from pulse signals for driving the CCD, such as a vertical transfer pulse and a horizontal transfer pulse sent to the camera head (hereinafter collectively referred to as a CCD drive pulse signal). The signal is fed back, and the CCD driving pulse signal is adjusted so that the phase of the returned CCD driving pulse signal and the reference pulse formed in the signal processing unit are synchronized, whereby the cable between the camera head and the signal processing unit is adjusted. The CCD can be driven accurately by compensating for a phase shift of a high-frequency signal such as a transfer pulse due to transmission and reception of a signal through the CCD.

[0005]

However, in this type of imaging apparatus, although the CCD can be driven correctly, the C
A phase error occurs in the signal output from the CD via the cable and the signal in the signal processing unit. Therefore, in the signal processing unit, color separation, sample hold, etc. are performed at regular timing with respect to the CCD output signal supplied from the CCD. Inconveniences such as not being able to obtain a correct video signal due to the inability to perform the operation have occurred. The present invention has been made in consideration of the above points, and a camera head and a signal processing unit using a solid-state imaging device including a charge-coupled device are separately formed, and the camera head and the signal processing unit are connected by a cable. It is an object of the present invention to propose a video camera which can always obtain a regular image without requiring adjustment according to the cable length.

[0006]

According to the present invention, there is provided a camera head using a solid-state imaging device comprising a charge-coupled device, and a signal processing means for outputting an output signal from the solid-state imaging device. And a drive signal S4 for driving the solid-state imaging device 9 from the signal processing unit 2 via the cable 7 to the solid-state imaging device 9. In the imaging device 1 for outputting, the driving signal S4 returned from the solid-state imaging device 9 to the signal processing unit 2 via the cable 7 and the driving signal synchronizing means 3 for synchronizing the phase of the timing pulse in the signal processing unit 2; First oscillating means 11 for generating an oscillating pulse of a frequency, and first timing pulse forming for generating and outputting a clock signal S20 based on the oscillating pulse. A stage 12, synchronizing signal generating means 20 for forming a reset pulse of the driving signal S4 based on the clock signal S20 and outputting the reset pulses to the driving signal synchronizing means 3 and the signal processing means 15, and a driving signal S4 fed back via the cable 7 And a counter 21 for resetting the timing pulse generating means 12 and transmitting the signal processing timing pulses to the signal processing means 15 when the counted number exceeds a predetermined number.

In the present invention, the drive signal synchronizing means 3 generates a reference pulse signal S which is a frequency reference of the drive signal S4 supplied from the first timing pulse forming means 12.
Phase comparing means 1 for comparing the phase of the driving signal S4 with the phase of the driving signal S4 returned from the camera head 8 via the cable 7.
0, a filter 13 for extracting a low frequency component of the output signal S8 of the phase comparison means 10, a second oscillation means 4 for generating an oscillation pulse of a predetermined frequency according to the voltage of the low frequency component, The second timing pulse generating means 5 divides the frequency and forms a plurality of types of drive signals S4.

[0008]

The counter 21 counts the number of pulses of the driving signal S4 which is fed back via the cable 7, and when the counted number exceeds a predetermined number, the first timing pulse generating means 12 is reset and the signal processing means 15 is reset. By transmitting the timing pulse of the signal processing, the phase of the output signal S10 transmitted from the solid-state imaging device 9 to the signal processing unit 15 via the cable 7 and transmitted to the signal processing unit 15 It is possible to synchronize the phase of the timing pulse with the phase of the timing pulse, thereby realizing a video camera capable of always obtaining a regular image without requiring adjustment according to the length of the cable 7.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

In FIG. 1, reference numeral 1 denotes a video camera as a whole, and a voltage controlled oscillation circuit 4 (VCO) of a drive pulse synchronization circuit unit 3 in a signal processing unit 2 oscillates at a predetermined frequency in an initial state. The signal S1 is supplied to the timing generator 5. The timing generator 5 divides the oscillation signal S1 to form a plurality of types of CCD drive pulses, and converts these into a vertical reset pulse signal S2.
Alternatively, they are sequentially output as drive pulse signals S4 in response to the input of the horizontal reset pulse signal S3.

At this time, the driving pulse signal S4 is supplied to a CCD 9 of a camera head 8 provided in a housing separate from the signal processing unit 2 via a cable 7 composed of a plurality of signal lines 6, and as a result, the CCD 9 It is driven according to the signal S4. In this case, a part of the horizontal transfer pulse signal S4A of the drive pulse signal S4 is sent from the camera head 8 to the phase comparison circuit 10 as the feedback horizontal transfer pulse signal S5 via the signal line 6A.

At this time, an oscillation signal S6 of a predetermined frequency output from the voltage control oscillation circuit 11 is supplied to the phase comparison circuit 10.
, A reference horizontal transfer pulse formed by the timing generator 12 and serving as a phase reference of the horizontal transfer pulse signal S4A is supplied as a reference horizontal transfer pulse signal S7,
Thus, the phase comparison circuit 10 compares the reference horizontal transfer pulse signal S7 and the feedback horizontal transfer pulse signal S5 to generate a signal having a voltage corresponding to the phase difference between the reference horizontal transfer pulse signal S7 and the feedback horizontal transfer pulse signal S5.
The number 8 is sent to the low-pass filter circuit 13. The low-pass filter circuit 13 converts the comparison signal S8 into a DC signal and sends it to the voltage controlled oscillation circuit 4 as a DC comparison signal S9.
The oscillating frequency of the oscillating signal S1 is changed in accordance with the signal level.

As a result, the frequency of the CCD driving pulse signal S4 output from the timing generator 5 changes, and the phase of the CCD driving pulse signal S4 is locked to the reference horizontal transfer pulse signal S7 in the signal processing section 2, CCD9
And the operation timing in the signal processing unit 2 can be synchronized. On the other hand, the timing generator 12 generates a clock signal S20 based on the oscillation signal S6 and sends it to the synchronizing signal generating circuit 20, and the synchronizing signal generating circuit 20 generates a vertical reset pulse and a horizontal reset pulse based on the clock signal S20. Various timing pulses such as a reset pulse are formed.

In this case, the vertical reset pulse is sent to the timing generators 5 and 12 as a vertical reset pulse signal S3, and the other timing pulses are sent as a timing pulse signal S21 to the signal processing circuit 1.
5 is sent. Therefore, in the signal processing circuit 15,
The CCD output signal S11 input from the CCD 9 via the signal line 6B is processed by the timing pulse signal S21. On the other hand, the horizontal reset pulse is sent to the timing generator 5 and the signal processing circuit 15 as a horizontal reset pulse signal S3.

Here, a part of the feedback horizontal transfer pulse signal S5 is input to the counter circuit 21. As a result, the counter circuit 21 counts the number of horizontal transfer pulses based on the feedback horizontal transfer pulse signal S5. The number of pulses is C which is preprogrammed as preset information.
When the number of pixels for one horizontal line (for example, 768 pixels) of the CD 9 is exceeded, an overflowing pulse is sent to the tamping generator 12 as a horizontal reset signal S22. The timing generator 12 resets according to the input of the horizontal reset signal S22, and various timing pulses such as a sample hold and a color separation pulse as a timing pulse signal S30.
5 and the signal processing circuit 15 outputs the CCD output signal S10
Is processed based on the timing pulse signal S30 from the timing generator 12. As a result, the signal processing circuit 15 can perform signal processing such as color separation and sample hold at a correct timing with respect to the CCD output signal S10.

In the timing generator 5, when the power of the video camera 1 is turned on, the counter circuit 2 is turned on.
By sending the initial setting pulse signal S40 to the counter 1, the counter circuit 21 is reset, thereby preventing erroneous counting of the counter circuit 21.

In the above configuration, the driving pulse synchronizing circuit section 3 horizontally adjusts the phase of the feedback horizontal transfer pulse to the phase of the reference horizontal transfer pulse based on the feedback horizontal transfer pulse signal S5 and the reference horizontal transfer pulse signal S7. The CCD drive signal S4 for adjusting the output frequency of the transfer pulse signal S4A and for driving the CCD 9 based on the vertical reset signal S2 and the horizontal reset signal S3 formed at the timing of the timing generator 12 in the synchronizing signal generation circuit 20. , The CCD 9 is driven in synchronization with the timing of the signal processing unit 2.

In addition, the counter circuit 21 is connected to the signal line 6
The number of pulses of the feedback horizontal transfer pulse signal S5, which is fed back via A, is counted. When the counted number overflows the number of pulses for one horizontal line of the CCD 9 which has been programmed in advance, the horizontal reset signal is sent to the timing generator 12. By transmitting and resetting S22, the phase of the timing pulse signal S30 output from the timing generator 12 and the phase of the CCD output signal S10 transmitted from the CCD 9 via the signal line 6B are synchronized. .

According to the above configuration, a part of the feedback horizontal transfer pulse signal S5 is sent to the counter circuit 21 to count the number of pulses, and the counted number is set to the number of pixels for one horizontal line of the CCD 9 which is programmed in advance. The counter circuit 21 resets the timing generator 12 when the signal exceeds the limit, so that if there is no loss such as DC resistance or frequency characteristic deterioration in each signal line 6 of the cable 7, the cable is in principle no cable. CCD without worrying about the length
9, the CCD output signal S10 transmitted to the signal processing circuit 15 via the cable 7 and the timing pulse signals S21 and S30 in the signal processing unit 2 can be synchronized, and thus, fine adjustment according to the cable length , And a video signal at a regular timing can always be obtained.

In the above-described embodiment, the case has been described in which the overflow occurs when the count number of the counter circuit 21 exceeds, for example, 768. However, the present invention is not limited to this. The present invention can be applied to various television systems such as the NTSC system and the PAL system and various CCDs by adjusting.
In the above embodiment, the signal line 6B
The case where the PLL circuit is used as a method for synchronizing the phase of the CCD output signal S10 transmitted to the signal processing circuit 15 via the signal processing section 15 with the phase of the timing pulse in the signal processing section 2 has been described. Is not limited to this,
Various other methods can be applied.

[0021]

As described above, according to the present invention, a camera head using a solid-state imaging device composed of a charge-coupled device and a signal processing unit having signal processing means for processing an output signal output from the solid-state imaging device are separately provided. In an imaging apparatus configured and connected to each other by a cable, a counter circuit is provided in the signal processing unit, and the counter circuit counts the number of pulses of the drive signal that is fed back via the cable, and the count number reaches a predetermined number. By resetting the timing pulse generating means when it exceeds, the timing pulse for signal processing is sent to the signal processing means, so that the output signal transmitted from the solid-state imaging device to the signal processing means via the cable is output. It is possible to synchronize the phase and the phase of the timing pulse sent to the signal processing means, and thus to the length of the cable. Flip adjustment always possible to realize a video camera obtained legitimate video without the need for a.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a signal synchronization processing system in a CCD and a signal processing unit of a video camera according to the present invention.

[Explanation of symbols]

1 video camera 2 signal processing unit 3 drive pulse synchronization circuit unit 4 11 voltage controlled oscillator circuit 5
12 Timing generator, 6, 6A, 6B
Signal line, 7 ... Cable, 8 ... Camera head, 9 ...
CCD, 10 ... Phase comparison circuit, 13 ... Low pass filter, 15 ... Signal processing circuit, 20 ... Synchronization signal generation circuit, S2 ... Vertical reset pulse signal, S3 ... Horizontal reset pulse signal, S4 ... CCD Drive pulse signal, S
4A: horizontal transfer pulse signal, S5: feedback horizontal transfer pulse signal, S7: reference horizontal transfer pulse signal, S10:
... CCD output signal, S20 ... Clock signal, S21,
S30: timing pulse signal; S22: reset signal.

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Isao Kajino 539-5 Higashiasakawa-cho, Hachioji-shi, Tokyo CIS Co., Ltd. (56) References JP-A-63-232581 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/232 H04N 5/335

Claims (2)

(57) [Claims] A camera head using a solid-state imaging device comprising a charge-coupled device and a signal processing section having signal processing means for output signals output from the solid-state imaging device are formed separately, and a cable is provided between the two. An imaging device connected to the solid-state imaging device to output a drive signal for driving the solid-state imaging device from the signal processing unit via the cable to the solid-state imaging device, wherein the solid-state imaging device returns to the signal processing unit via the cable A driving signal synchronizing means for synchronizing the phase of the driving signal and the timing pulse in the signal processing section, a first oscillating means for generating an oscillating pulse of a predetermined frequency, and a clock signal based on the oscillating pulse. First timing pulse forming means for outputting a reset pulse of the drive signal based on the clock signal. A synchronization signal generating means for outputting to the drive signal synchronizing means and the signal processing means, counting the number of pulses of the drive signal fed back via the cable, and generating the timing pulse when the count exceeds a predetermined number. An imaging apparatus comprising: a counter for resetting the means and causing the signal processing means to transmit a signal processing timing pulse. 2. The driving signal synchronizing means includes: a phase of a reference pulse signal serving as a frequency reference of the driving signal supplied from the first timing pulse forming means;
A phase comparison unit that compares the phase of the drive signal that is fed back from the camera head via the cable; a filter that extracts a low-frequency component from an output signal of the phase comparison unit; An imaging apparatus comprising: a second oscillating unit that generates an oscillation pulse having a predetermined frequency; and a second timing pulse generating unit that divides the oscillation pulse to form a plurality of types of the drive signals.