JPS585626B2 - How to combine video signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for synthesizing video signals used to display characters, graphics, etc. on a cathode ray tube screen.

When displaying graphics or characters on the screen of a television receiver or cathode ray tube display device using a video signal obtained by synthesizing digital signal processing, consider horizontal synchronization signals, vertical synchronization signals, pixel frequency signals, and color images. Then, a 3.58 MHz subcarrier is required.

The relationship between the horizontal synchronizing signal frequency fH and the vertical synchronizing signal frequency fV is satisfied based on the subcarrier frequency fC.

In this case, the relationship between the subcarrier fC and the horizontal synchronization signal fH is such that the phase shifts by 1/2 period for each horizontal scan, as shown in FIGS. 2A and 2B.

Therefore, the pixel frequency signal obtained by frequency-dividing this subcarrier fC by an appropriate number also has a phase shift for each horizontal scanning line.

If the phase is shifted in this way, when displaying characters or graphics, the vertical arrangement of the bright spots that make up the characters or graphics shifts back and forth for each horizontal scanning line, which becomes an eyesore.

To prevent this, the pixel frequency signal (clock pulse)
The phase of must be synchronized with the rising or falling edge of the horizontal synchronizing signal pulse.

To do this, either (1) create an independent oscillator and adjust the frequency to match the phase, or (2) configure a locked oscillator using horizontal synchronizing signal pulses to generate the pixel frequency signal (clock pulse) of characters or graphics. There is a need.

In the case of (1), it is necessary to create a highly stable oscillator, which requires time and effort for adjustment.

In the case of (2), the configuration becomes complicated and the cost increases.

In addition, either method requires two clock oscillators (a subcarrier oscillator and a pixel frequency signal oscillator).

The present invention is a method for solving the above problems, and makes it possible to stably supply a horizontal synchronization signal fH, a vertical synchronization signal fV, and a pixel signal without adjustment using a single reference oscillator. .

According to the present invention, a reference frequency signal is frequency-divided to generate a horizontal synchronization signal and a vertical synchronization signal.

Then, the phase of this reference frequency signal is inverted every horizontal scanning period to synchronize with the rising or falling phase of each horizontal synchronizing signal pulse, and the signal obtained by this operation is divided by an appropriate number to generate a pixel frequency signal. It is said that

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of a circuit for implementing the method of the present invention.

Reference numeral 10 denotes an oscillator that oscillates a subcarrier fC as a reference frequency, and obtains its output synchronization signal fH.

The horizontal synchronizing signal fH is obtained and applied to a control signal generating circuit 16 and a video signal synthesizing circuit 19 consisting of a flip-flop.

A vertical synchronizing signal fV is also applied to the combining circuit 19.

The reference frequency signal fC obtained from the oscillator 10 is divided into a signal having passed through a buffer amplifier 14 and a signal fC' whose phase has been inverted by passing through a phase inverter 13, and both signals are applied to a switch circuit 15.

The control signal generation circuit 16 is triggered by the horizontal synchronization signal fH, and generates a switching control signal so that the switch circuit 15 selects and outputs signals fC and fC' whose phases are alternately inverted every horizontal scanning period. .

The output signal of the switch circuit 15 is frequency-divided by 1/N to become a predetermined pixel frequency signal and is applied to the video signal synthesis circuit 19.

The circuit 19 is appropriately supplied with character or graphic representation signals from the generator 18, where a predetermined video signal is synthesized and output to the cathode ray tube drive circuit for display.

As mentioned above, the output fC of the oscillator 10 is out of phase by π with respect to the horizontal synchronizing signal pulse D in FIG. 2, as shown in FIGS. 2A and B in the first and second lines of horizontal scanning. When the phase of the output signal is inverted through the phase inverter 13, it becomes the same phase as the output through the buffer amplifier 14, as shown in FIG. 2C.

Therefore, if the fC and fC' signals are switched and extracted every horizontal scanning period and used to form a video signal for displaying characters or figures, it is possible to obtain characters or figures without bright spot deviation. .

Note that the buffer amplifier 14 has a function of providing the signal fC with the same transmission delay time characteristics as the phase inverter 13.

As explained above, the present invention has the following effects because the horizontal synchronizing signal fH, the vertical synchronizing signal fV, and the pixel frequency signal (clock signal) can be formed from the same reference frequency signal (subcarrier oscillation frequency fC).

(1) The frequency of the pixel frequency signal can be made unadjusted, and the phase relationship with the horizontal and vertical synchronization signals is stable.

(2) Compared to configuring a locked oscillator or the like, the circuit configuration is simplified and equivalent performance can be obtained.

(3) The frequency of the video signal synthesis clock can be divided arbitrarily, and a video signal consisting of an arbitrary pixel frequency and a valid period can be set.

That is, you can select the font size, width, number of characters, etc.

Note that although the frequency divider 17 in FIG. 1 is provided after the switch circuit 15, it may be provided in front of the phase inverter 13 and the buffer amplifier 14 as well.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a circuit providing the method of the present invention, and FIG. 2 is a time chart for explaining the present invention. 10... Reference frequency signal oscillator, 11...
...Frequency divider that generates horizontal synchronization signal fH, 12...
...Frequency divider that generates vertical synchronization signal fV, 13...
... Phase inverter, 15 ... Switch circuit, 16
...Control signal generation circuit.

Claims (1)

[Claims] 1. Divide the reference frequency signal to form a horizontal synchronization signal,
This horizontal synchronization signal is frequency-divided to form a vertical synchronization signal, and the reference frequency signal or the signal obtained by frequency-dividing this signal is inverted every horizontal scanning period to form a pixel frequency signal. A method of synthesizing a video signal, characterized by synthesizing a video signal using a synchronization signal and a pixel frequency signal as basic components. 2. The video signal synthesis method according to claim 1, wherein the reference frequency signal is a color subcarrier frequency.