KR970031912A - Synchronous signal generator for on screen display - Google Patents

Synchronous signal generator for on screen display Download PDF

Info

Publication number
KR970031912A
KR970031912A KR1019950040857A KR19950040857A KR970031912A KR 970031912 A KR970031912 A KR 970031912A KR 1019950040857 A KR1019950040857 A KR 1019950040857A KR 19950040857 A KR19950040857 A KR 19950040857A KR 970031912 A KR970031912 A KR 970031912A
Authority
KR
South Korea
Prior art keywords
vertical
generating
screen display
horizontal
signal
Prior art date
Application number
KR1019950040857A
Other languages
Korean (ko)
Other versions
KR0155923B1 (en
Inventor
장강열
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950040857A priority Critical patent/KR0155923B1/en
Publication of KR970031912A publication Critical patent/KR970031912A/en
Application granted granted Critical
Publication of KR0155923B1 publication Critical patent/KR0155923B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/445—Receiver circuitry for the reception of television signals according to analogue transmission standards for displaying additional information

Abstract

본 발명은 동기신호 생성장치에 관한 것으로서, 특히 TV(텔레비젼) 복합영상신호가 인가되지 않을 때 동기신호를 자체 생성하는 온스크린 디스플레이용 동기신호 생성장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating a synchronization signal, and more particularly, to an apparatus for generating an on-screen display for generating a synchronization signal when a TV (TV) composite video signal is not applied.

온스크린 디스플레이(OSD)용 동기신호 생성장치는, 소정의 안정된 발진 클락을 생성하는 발진부 ; 상기 발진부에서 생성된 클락을 수직 및 수평동기신호에 근접하게 분주하는 분주부 ; 분주한 클락을 수직 및 수평동기 신호의 주기에 맞게 보다 세밀히 분주하는 프리스케일러부 ; 수직 및 수평동기신호의 펄스폭에 해당하는 카운트 데이터를 저장하는 동기데이터 레지스터부 ; 저장된 펄스폭 데이터에 따라 펄스폭을 카운트하여 수직 및 수평동기신호 생성하는 카운터부 ; 및 수직 및 수평동기신호를 복합동기신호의 검출신호에 의해 출력여부를 스위칭하는 선택부를 포함함을 특징으로 한다. 본 발명에 따른 온스크린 디스플레이용 동기신호 생성장치는 복합영상신호가 인가되지 않을 경우에는 안정된 수직 및 수평동기신호를 생성함으로써 OSD에 의해 디스플레이되는 문자의 떨림을 방지한다.An on-screen display (OSD) synchronization signal generating apparatus includes: an oscillating unit for generating a predetermined stable oscillation clock; A divider for dividing the clock generated by the oscillator in close proximity to the vertical and horizontal synchronization signals; A prescaler unit for dividing the divided clock in more detail according to the period of the vertical and horizontal synchronization signals; A synchronization data register section for storing count data corresponding to the pulse widths of the vertical and horizontal synchronization signals; A counter unit for counting the pulse width according to the stored pulse width data to generate vertical and horizontal synchronization signals; And a selector for switching the output of the vertical and horizontal synchronous signals by the detection signal of the composite synchronous signal. The apparatus for generating on-screen display synchronization signals according to the present invention prevents the shaking of characters displayed by the OSD by generating stable vertical and horizontal synchronization signals when a composite video signal is not applied.

Description

온스크린 디스플레이용 동기신호 생성장치Synchronous signal generator for on screen display

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 온스크린 디스플레이(OSD)용 동기신호 생성장치를 보이는 블록도이다.2 is a block diagram showing an apparatus for generating a synchronization signal for an on-screen display (OSD) according to the present invention.

제3a도 및 제3b도는 본 발명의 장치에서 출력되는 수평 및 수직동기 신호의 타이밍도이다.3A and 3B are timing diagrams of horizontal and vertical synchronization signals output from the apparatus of the present invention.

Claims (6)

온스크린 디스플레이(OSD)용 동기신호 생성장치에 있어서, 소정의 안정된 발성 클락을 생성하는 발진부 ; 상기 발진부에서 생성된 클락을 수직 및 수평동기 신호에 근접하게 분주하는 분주부 ; 상기 분주부에서 분주한 클락을 수직 및 수평동기 신호의 주기에 맞게 보다 세밀히 분주하는 프리스케일러부 ; 수직 및 수평동기신호의 펄스폭에 해당하는 카운트 데이터를 저장하는 동기데이터 레지스터부 ; 상기 동기데이터 레지스터부에 저장된 펄스폭 데이터에 따라 펄스폭을 카운트하여 수직 및 수평동기신호 생성하는 카운터부 ; 및 상기 카운터부에서 생성한 수직 및 수평동기신호를 복합동기신호의 검출신호에 의해 출력여부를 스위칭하는 선택부를 포함함을 특징으로 하는 온스크린 디스플레이용 동기신호 생성장치.An on-screen display (OSD) synchronization signal generator, comprising: an oscillator for generating a predetermined stable talk clock; A divider which divides the clock generated by the oscillator in close proximity to the vertical and horizontal synchronization signals; A prescaler for dividing the clock divided by the divider more precisely in accordance with the period of the vertical and horizontal synchronization signals; A synchronization data register section for storing count data corresponding to the pulse widths of the vertical and horizontal synchronization signals; A counter unit for counting a pulse width according to the pulse width data stored in the synchronization data register unit and generating vertical and horizontal synchronization signals; And a selection unit for switching output of the vertical and horizontal synchronous signals generated by the counter by the detection signal of the composite synchronous signal. 제1항에 있어서, 상기 분주부는 상기 발진부의 클락을 각각 유입하여 수직동기신호의 주기에 근접하게 분주하는 제1분주부와 수평동기신호의 주기에 근접하게 분주하는 제2분주부를 포함함을 특징으로 하는 온스크린 디스플레이용 동기신호 생성장치.The frequency divider of claim 1, wherein the divider includes a first divider which injects the clocks of the oscillator and divides the frequency of the vertical synchronization signal, and a second divider that divides the frequency of the horizontal synchronization signal. A synchronization signal generator for on-screen display, characterized in that. 제1항에 있어서, 상기 프리스케일러부는 상기 분주부에서 출력된 클락을 수직동기신호의 주기와 일치하게 분주하는 제1프리스케일러와 수평동기신호의 주기와 일치하게 분주하는 제2프리스케일러를 포함함을 특징으로 하는 온스크린 디스플레이용 동기신호 생성장치.The method of claim 1, wherein the prescaler comprises a first prescaler for dividing the clock output from the dividing unit in accordance with the period of the vertical synchronization signal and a second prescaler for dividing the clock in the same manner as the period of the horizontal synchronization signal. Sync signal generator for on-screen display. 제1항에 있어서, 상기 프리스케일러부는 사용자가 4비트의 데이터 세팅으로 상기 발진부의 발진클락의 주파수에 따라 가변하여 설정후 분주함을 특징으로 하는 온스크린 디스플레이용 동기신호 생성장치.The sync signal generator of claim 1, wherein the prescaler divides the prescaler according to a frequency of the oscillation clock of the oscillator by setting a 4-bit data. 제1항에 있어서, 상기 동기데이터 레지스터부는 수직동기신호의 펄스폭 카운트 데이터를 저장하는 수직동기 데이터 레지스터부와 수평동기신호의 펄스폭 카운트 데이터를 저장하는 수평동기데이터 레지스터부를 포함함을 특징으로 하는 온스크린 디스플레이용 동기신호 생성장치.The method of claim 1, wherein the synchronous data register comprises a vertical synchronous data register for storing pulse width count data of a vertical synchronous signal and a horizontal synchronous data register for storing pulse width count data of a horizontal synchronous signal. Synchronization signal generator for on-screen display. 제1항에 있어서, 상기 카운터부는 자체 카운트한 값이 상기 카운트 데이터값 이상이 될 때 출력하는 펄스를 하이에서 로우레벨로 유지함을 특징으로 하는 온스크린 디스플레이용 동기신호 생성장치.The synchronization signal generating device for on-screen display according to claim 1, wherein the counter unit maintains a pulse output from a high level to a low level when a self-counted value becomes equal to or greater than the count data value. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950040857A 1995-11-11 1995-11-11 Synchronizing signal generator for on-screen display KR0155923B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950040857A KR0155923B1 (en) 1995-11-11 1995-11-11 Synchronizing signal generator for on-screen display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950040857A KR0155923B1 (en) 1995-11-11 1995-11-11 Synchronizing signal generator for on-screen display

Publications (2)

Publication Number Publication Date
KR970031912A true KR970031912A (en) 1997-06-26
KR0155923B1 KR0155923B1 (en) 1998-11-16

Family

ID=19433779

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950040857A KR0155923B1 (en) 1995-11-11 1995-11-11 Synchronizing signal generator for on-screen display

Country Status (1)

Country Link
KR (1) KR0155923B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100512512B1 (en) * 2001-11-14 2005-09-07 산요덴키가부시키가이샤 Semiconductor device
KR100521942B1 (en) * 1998-08-22 2006-01-27 엘지전자 주식회사 OSD Character Stabilizer and Stabilization Method
KR100521634B1 (en) * 1998-10-29 2006-01-27 주식회사 현대오토넷 Antenna Diversity Using LCD Vertical Synchronization Signal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100521942B1 (en) * 1998-08-22 2006-01-27 엘지전자 주식회사 OSD Character Stabilizer and Stabilization Method
KR100521634B1 (en) * 1998-10-29 2006-01-27 주식회사 현대오토넷 Antenna Diversity Using LCD Vertical Synchronization Signal
KR100512512B1 (en) * 2001-11-14 2005-09-07 산요덴키가부시키가이샤 Semiconductor device

Also Published As

Publication number Publication date
KR0155923B1 (en) 1998-11-16

Similar Documents

Publication Publication Date Title
KR910007267A (en) How to generate two reference signals of the same frequency as the time base generator circuit
KR970057340A (en) TV's two-screen device
KR950001360A (en) How to display data on digital oscilloscopes and oscilloscopes using color plane indicators
KR970075975A (en) Liquid crystal display
JPS581785B2 (en) cathode ray tube display device
KR970031912A (en) Synchronous signal generator for on screen display
KR970007781A (en) Timing generator for LCD driving
KR890006059A (en) TV receiver
JP3911862B2 (en) Pixel clock signal generation device and synchronization signal generation device
KR920009222A (en) Character display
KR890011439A (en) Image display
US6229865B1 (en) Phase difference detection circuit for liquid crystal display
JP2714302B2 (en) Pixel synchronizer
KR0123651Y1 (en) Circuit for motion control of osd generation
KR100266164B1 (en) Method for emboding sync of divided picture and apparatus thereof
JP2715179B2 (en) Microcomputer
KR930003094A (en) Jitter Detection Circuit
JP3221562B2 (en) Pseudo video signal generation circuit
KR960003443B1 (en) Letter display apparatus
JP2657917B2 (en) Horizontal sync waveform generator
JP3257490B2 (en) Synchronous protection circuit and method
KR960006486A (en) Clock generator
KR970004645A (en) Width Control Unit of Horizontal Sync Signal for Plasma Display Televisions
JPS585626B2 (en) How to combine video signals
KR950034183A (en) Still Image Control Device of Digital Video Data

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100630

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee