KR0155923B1 - Synchronizing signal generator for on-screen display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating a synchronization signal, and more particularly, to an apparatus for generating an on-screen display for generating a synchronization signal when a TV (TV) composite video signal is not applied.

An apparatus for generating a synchronization signal for an on-screen display (OSD) includes: an oscillator for generating a predetermined stable oscillation clock; A divider for dividing the clock generated by the oscillator in close proximity to the vertical and horizontal synchronization signals; A prescaler unit for dividing the divided clock in more detail according to the period of the vertical and horizontal synchronization signals; A synchronization data register unit for storing count data corresponding to the pulse widths of the vertical and horizontal synchronization signals; A counter unit for counting the pulse width according to the stored pulse width data to generate vertical and horizontal synchronization signals; And a selector for switching the output of the vertical and horizontal synchronous signals by the detection signal of the composite synchronous signal. The apparatus for generating on-screen display synchronization signals according to the present invention prevents the shaking of characters displayed by the OSD by generating stable vertical and horizontal synchronization signals even when a composite video signal is not applied.

Description

Synchronous signal generator for on screen display

1 is a block diagram illustrating a sync separator for applying a sync signal to a conventional OSD unit.

2 is a block diagram showing an apparatus for generating a synchronization signal for an on-screen display (OSD) according to the present invention.

3A and 3B are timing diagrams of horizontal and vertical synchronization signals output from the apparatus of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating a synchronization signal, and more particularly, to an apparatus for generating an on-screen display for generating a synchronization signal when a TV (TV) composite video signal is not applied.

On-screen display (OSD) is widely used in TVs for channel selection, time setting, and on / off setting of reservation time.

In the related art, when the synchronization signal is applied to the OSD unit by separating the synchronization signal from the TV composite image signal, the OSD unit displays the character information on the TV screen in synchronization with the synchronization signal.

However, when the TV composite video signal is not applied, the synchronization signal generated by the unstable oscillation itself is applied to the OSD unit, and as a result, the displayed characters are vibrated violently on the TV screen due to the synchronization being inconsistent. .

The present invention has been made to solve the above problems, even when the TV composite video signal is not applied, automatically detects the presence or absence of the composite video signal to generate stable sync signals to prevent the shaking of the characters displayed on the OSD An object of the present invention is to provide a synchronizing signal generator for a display.

An apparatus for generating a synchronization signal for an on-screen display (OSD) according to the present invention for achieving the above object,

An oscillation unit for generating a predetermined stable oscillation clock;

A divider for dividing the clock generated by the oscillator in close proximity to the vertical and horizontal synchronization signals;

A prescaler unit which divides the clock divided by the division unit in more detail according to the period of the vertical and horizontal synchronization signals;

A synchronization data register unit for storing count data corresponding to the pulse widths of the vertical and horizontal synchronization signals;

A counter unit for counting the pulse width according to the pulse width data stored in the synchronous data register unit and generating vertical and horizontal synchronous signals; And

And a selection unit for switching the output of the vertical and horizontal synchronization signals generated by the counter by the detection signal of the composite synchronization signal.

Hereinafter, a conventional apparatus will be described in detail to help the understanding of the present invention.

1 is a block diagram illustrating a sync separator for applying a sync signal to a conventional OSD unit.

Referring to the operation according to the configuration of FIG. 1, when the TV composite video signal is applied to the synchronous separator 100, the vertical synchronous signal and the horizontal synchronous signal are separated from the TV composite video signal and applied to the OSD unit 110.

At this time, the OSD unit 110 introduces stable vertical and horizontal synchronous signals and applies character data at regular intervals between the horizontal synchronous signal and the vertical synchronous signal to output the R, G, B signals and the luminance signal Y to the TV screen. Allow stable characters to be displayed.

On the other hand, when the TV composite synchronizing signal is not applied to the synchronizing separator 100, that is, when there is no broadcasting signal, the synchronizing separator 100 oscillates the vertical and horizontal synchronizing signals by itself and free-running them. And the horizontal synchronizing signal is unstablely output to the OSD unit 110.

Subsequently, the OSD unit 110 outputs the color signals R, G, B and the luminance signal Y by inputting text data at predetermined intervals of the vertical and horizontal synchronous signals, respectively. The characters displayed on the screen are severely shaken.

2 is a block diagram showing an apparatus for generating a synchronization signal for an on-screen display (OSD) according to the present invention.

The apparatus shown in FIG. 2 includes an oscillator 200, a divider 202, a prescaler 208, a counter 214, a sync data register 220, a selector 226, and a sync separator 231. And an OSD unit 232.

The frequency division unit 202 cycles the clock generated by the oscillation unit 200 at a predetermined division ratio to the clock oscillated by the oscillation unit 200 at a predetermined division ratio, and the clock generated by the oscillation unit 200. And a second dispensing unit 206 dispensing at a predetermined dispensing ratio close to.

The prescaler 208 receives the clock signal divided by the first division unit 204 and the second division unit 206 from the first prescaler 210 and the second prescaler 212, respectively. Dispense the dispensed clock precisely to coincide with the vertical and horizontal periods.

The synchronization data register unit 220 includes a vertical synchronization data register unit 222 for storing pulse width count data of a vertical synchronization signal and a horizontal synchronization data register unit 224 for storing pulse width count data of a horizontal synchronization signal. .

The counter unit 214 repeatedly counts during the synchronizing signal period and outputs an output signal level from high to low level when the vertical synchronizing data register unit 222 is equal to or greater than the count data value to generate an accurate vertical synchronizing signal. 216 and a second counter unit 218 for outputting an output signal level from high to low level to generate an accurate horizontal synchronous signal if the counted value is equal to or greater than the horizontal synchronous data register unit 224. .

The selector 226 inputs a synchronous detection signal having a high or low level signal according to the presence or absence of a composite synchronous signal, and switches the vertical synchronous signal output from the first counter 216 when the composite synchronous signal does not exist. A first selection unit 228 to be applied to the unit 232, and a second selection to switch the horizontal synchronous signal output from the second counter 218 to the OSD unit 232 when the composite synchronous signal does not exist. The unit 230 is included.

Looking at the operation according to the configuration of Figure 2 the oscillator 200 oscillates a stable clock higher than the vertical and horizontal synchronous frequency.

The first divider 204 flows in the clock oscillated by the oscillator 200 and divides it in close proximity to the period of the vertical synchronization signal, and the second divider 206 enters the clock oscillated in the oscillator 200 and horizontally. Divide close to the period of the synchronization signal.

The first prescaler 210 can be set to 4 bits so that the user can divide the variable from 0 to 15 so that the clock signal divided by the first divider 204 can generate a clock coinciding with the period of the vertical synchronization signal. do.

In addition, the second prescaler 212 can be set to 4 bits to vary the frequency from 0 to 15 and thus divide the clock signal divided by the second divider 206 to generate a clock coinciding with the period of the horizontal synchronization signal. do.

On the other hand, the vertical synchronization signal register 222 stores data to be counted to calculate the pulse width of the vertical synchronization signal, and the horizontal synchronization signal register 224 stores data to be counted to calculate the pulse width of the horizontal synchronization signal. .

The counter unit 214 keeps the pulse width high until the count data value is reached.

The first counter 216 is a 4-bit counter that counts repeatedly during the vertical synchronization signal period. The first counter 216 outputs a clock that is output from the first prescaler 210 and coincides with the period of the vertical synchronization signal. The high level is maintained for only 2.25 mS, which is less than or equal to the count data value of the register 222, and the remaining period is kept at a low level, thereby generating a synchronization signal such as the vertical synchronization signal of FIG.

In this case, the frequency of the clock of the oscillator 200 is 8 MHz, the 4-bit value of the first prescaler is 9, the division of the first divider 204 is 1000, and the data value of the vertical synchronization data register 222 is 2, the first. If the counter 216 is 4 bits, the vertical synchronization frequency and the vertical synchronization signal pulse width are as follows.

Vertical synchronization frequency = oscillation frequency / (first division * first prescaler value * first counter 4 bits)

The vertical synchronization frequency = 8000000 / (1000 * 9 * 16) = 56 Hz (period = 17.8 mS).

Vertical Sync Signal Pulse Width = Vertical Sync Register Value * (1st Division * 1st Prescaler Value) / Oscillation Frequency

The vertical synchronization frequency pulse width = 2 * (1000 * 9) / 8000000 = 2.25mS.

The second counter 212 is a 4-bit counter that counts repeatedly during the horizontal synchronization signal period. The second counter 212 outputs a clock that is output from the second prescaler 212 and coincides with the period of the horizontal synchronization signal. The high level is maintained only for 11.2 ms or less, which is equal to or less than the count data value of the register 224, and the remaining period is kept low to generate a synchronization signal such as the horizontal synchronization signal of FIG. 3b.

In this case, the frequency of the clock of the oscillator 200 is 8 MHz, the 4-bit value of the second prescaler is 3, the division of the second divider 206 is 10, and the data value of the horizontal synchronous data register 224 is 3, the second. If the counter 218 is 4 bits, the horizontal synchronization frequency and the horizontal synchronization signal pulse width are as follows.

Horizontal Synchronization Frequency = Oscillation Frequency / (2nd Division * 2nd Prescaler Value * 2nd Counter 4bit)

Horizontal sync frequency = 8000000 / (10 * 3 * 6) = 16.67 Hz (cycle = 60 Hz)

Horizontal Synchronization Signal Pulse Width = Horizontal Synchronization Register Value * (2nd Division * 2nd Prescaler Value) / Oscillation Frequency

Vertical sync frequency pulse width = 3 * (10 * 3) / 8000000 = 11.25 ㎲

The vertical and horizontal synchronizing signals generated by the counter unit 226 are maintained at a high level when the composite synchronizing signal detection unit (not shown) is maintained at a high level, and when the composite synchronizing signal is not detected, the output signal is maintained at a low level. do.

At this time, the first selector 228 injects the synchronous detection signal output from the composite synchronous signal detection unit, and when the synchronous detection signal is at a high level, is output from the first counter 216 and applied to the OSD unit 232. The vertical synchronous signal is blocked and the vertical synchronous signal obtained by introducing the composite video signal from the synchronous separator 231 and connected to the OSD unit 232.

In addition, when the synchronous detection signal is at a low level, the synchronous detection signal is output from the first counter 216 to switch the vertical synchronous signal applied to the OSD unit 232.

The second selector 230 injects the synchronous detection signal output from the composite synchronous signal detection unit, and when the synchronous detection signal is high level, is output from the second counter 218 and applied to the OSD unit 232. Block and input the composite video signal from the sync separator 231 to the OSD unit 232.

In addition, when the synchronous detection signal is at a low level, the synchronous detection signal is output from the second counter 218 to switch the horizontal synchronous signal applied to the OSD unit 232.

Therefore, when the synchronization detection signal is at the high level, the OSD unit 232 performs on-screen display using the vertical and horizontal synchronization signals obtained by injecting the composite video signal from the synchronization separator 231, and the synchronization detection signal is at the low level. When on screen display using the stable vertical and horizontal synchronization signal generated in the device of the present invention.

The synchronization signal generator for on-screen displays of the present invention can be applied to semiconductor circuits.

As described above, the on-screen display synchronization signal generating apparatus according to the present invention provides a function of preventing the shaking of characters displayed by the OSD by generating stable vertical and horizontal synchronization signals even when a composite video signal is not applied. .

Claims (6)

An on-screen display (OSD) synchronization signal generator, comprising: an oscillator for generating a predetermined stable oscillation clock; A divider for dividing the clock generated by the oscillator in close proximity to the vertical and horizontal synchronization signals; A prescaler unit for finely dividing the divider divided by the division unit in accordance with the period of the vertical and horizontal synchronization signals; A synchronization data register unit for storing count data corresponding to the pulse widths of the vertical and horizontal synchronization signals; Whether to output the vertical and horizontal synchronous signals generated by the counter unit by counting the pulse width according to the pulse width data stored in the synchronous data register unit and the vertical and horizontal synchronous signals generated by the counter unit by the detection signal of the composite synchronous signal. And a selection unit for switching. The frequency divider of claim 1, wherein the divider includes a first divider which injects the clocks of the oscillator and divides the frequency of the vertical synchronization signal, and a second divider that divides the frequency of the horizontal synchronization signal. Synchronous signal generator for on-screen display, characterized in that. The method of claim 1, wherein the prescaler comprises a first prescaler for dividing the clock output from the dividing unit in accordance with the period of the vertical synchronization signal and a second prescaler for dividing the clock in the same manner as the period of the horizontal synchronization signal. Sync signal generator for on-screen display. The sync signal generator of claim 1, wherein the prescaler divides the data after setting by varying the frequency of the oscillation clock of the oscillator with a 4-bit data setting. The method of claim 1, wherein the synchronous data register comprises a vertical synchronous data register for storing pulse width count data of a vertical synchronous signal and a horizontal synchronous data register for storing pulse width count data of a horizontal synchronous signal. Synchronization signal generator for on-screen display. The synchronization signal generating device for on-screen display according to claim 1, wherein the counter unit maintains a pulse output from a high level to a low level when a self-counted value becomes equal to or greater than the count data value.