JPH0799870B2 - TV tuning display - Google Patents

Description

The present invention relates to a channel selection display device for a television.

[Outline of Invention]

The present invention relates to a channel selection display device of a television, and more particularly, to a channel selection display device that displays a channel selection indicator on a screen of a television by a change in brightness and moves the indicator horizontally by channel selection of the television. A voltage controlled oscillator that oscillates at N times the horizontal sync signal frequency in a synchronous PLL circuit (hereinafter
VCO) and the oscillation signal (frequency NH,
H is a counter (B) that counts the horizontal synchronizing signal frequency
The tuning voltage of the tuner and the tuner is detected by detecting the code matching with the up-down counter (A) which is generated by the digital code, and at that time, the constant voltage is superimposed (clamped) on the video signal, and the position of the tuning indicator on the screen An object of the present invention is to obtain a stable tuning display device that does not vibrate due to fluctuations in power supply voltage or a non-stationary state (state where there is no synchronization signal).

[Conventional technology]

Known techniques for displaying a channel selection indicator on a television screen are disclosed in JP-A-58-222679 and JP-A-54-124634.

In the first example, flyback. Integrates the pulse to form a sawtooth wave, superimposes the sawtooth wave on the tuning voltage, compares it with a constant voltage, and generates a pulse for channel selection display when the voltages match, and displays it on the TV screen. Excuse me.

In the second example, the tuning indicator is displayed on the television screen in the same way by the charge / discharge circuit of the multivibrator and the capacitor.

[Problems and Objectives to be Solved by the Invention]

However, the conventional circuit has the following problems.

When the power supply fluctuates, in the first example, the slope of the integrated sawtooth wave changes, and the position of the tuning indicator deviates from the normal position. In the first example, to prevent this, the flyback pulse is clipped by a Zener diode, etc., but the element such as a Zener diode changes the Zener voltage due to the bias current, so it is completely prevented. You cannot do it.

Similarly, in the second example, when the power supply voltage fluctuates, the charge amount charged in the capacitor also changes, and as a result, the tuning indicator deviates from the normal position.

Next, in the non-stationary state (the state where there is no synchronization signal between stations), since there is no horizontal synchronization signal, the horizontal AFC circuit oscillates at the free-run frequency. Therefore, since the frequency of the desired H shifts, the tuning indicator, which should be in the normal position in the stationed state, shifts in the non-stationed state. (For example, in the first example, since the frequency of the sawtooth wave is different in the local state and the non-local state, the slope of the waveform changes in each state.) The present invention has the above-mentioned disadvantages of the conventional technique. Improve,
An object of the present invention is to obtain a stable channel selection display device in which the position of the channel selection indicator does not swing even when the power supply voltage fluctuates or in a channelless state.

[Means for solving problems]

In order to solve the above-mentioned problems of the prior art, in the channel selection display device of the present invention, a first counter that counts a clock signal and a digital counter that generates a voltage corresponding to the count value of the counter.
An analog converter, a tuner that is supplied with the voltage as a tuning voltage, a video signal detector that generates a video signal based on the output signal of the tuner, a voltage-controlled oscillator, and a frequency-divided output signal of the voltage-controlled oscillator. A frequency divider, a phase comparator for comparing the phase of the horizontal synchronizing signal in the video signal and the output signal of the frequency divider, and the oscillation frequency of the voltage controlled oscillator based on the output value of the phase comparator. A horizontal PLL circuit including a low-pass filter that outputs a control voltage to be controlled, and a first signal obtained based on oscillation of the voltage-controlled oscillator are counted, and an output signal of the voltage-controlled oscillator is divided. Second reset by second signal obtained
A counter and a tuning signal superimposing circuit that superimposes a constant voltage on the video signal in response to detecting that the count values of the first and second counters have a predetermined relationship.

[Action]

According to the present invention, a counter (counting the oscillation signal of the voltage controlled oscillator that oscillates at N.H in the horizontal synchronization PLL circuit (the oscillation frequency of N.H in the case of a station)) is constituted by the above-described means. B) and an up-down counter (A) that generates a tuning voltage to the tuner by the D / A converter in the latter stage.
It has a code matching detector that detects a code matching when a part or all of the codes match with. Further, a code matching detection signal generated there causes a channel indicator to be displayed on the screen by superimposing a certain voltage level on the video signal detected by the video detector to modulate the luminance.

[Specific Example]

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a television channel selection display device according to the present invention. 101 is China. 104 is an up-down counter (A) for generating a tuning voltage, whose code is added or subtracted by a pulse generated by an external switch, a clock signal forming circuit or the like (neither is shown). The digital output signal of the up-down counter (A) 104 is converted into a DC tuning voltage by the D / A converter 103 and output to the tuner 101. The tuner 101 selects a channel according to the tuning voltage and generates an IF signal. The IF signal is video-detected by the video detector 102, and a video signal A (see FIG. 3) is output. The video signal A is sync separated by the sync separation circuit 105, and a sync separation signal B is output. (See FIG. 3) 106 is a horizontal synchronization PLL circuit. Reference numeral 110 is a voltage controlled oscillator, which oscillates at N.H in the case of a station. Therefore, the horizontal direction of the television screen is the oscillation signal, and is always divided into N regardless of whether it is stationed or not. The oscillation frequency of the voltage controlled oscillator 110 is controlled by the DC voltage from the low pass filter 109. The oscillation signal E (see FIG. 3) of the voltage controlled oscillator 110 is output to the frequency divider 107 and the counter (B). The frequency divider 107 outputs the oscillation signal to N
The frequency division is performed to generate the frequency division signal c, while the reference signal is supplied to the display unit drive circuit 114 that drives the display unit 115. Also,
The start signal D is supplied to the counter 111. Phase comparator 1
At 08, the phase comparison between the sync separation signal B and the frequency-divided signal C from the frequency divider 107 is performed. In the presence of the sync signal in the station, B and C match as shown in FIG. 3 (However, the pulse width of the divided signal C does not match that of the sync separation signal B depending on the configuration of the PLL. However, the phase relationship is constant), and the frequency-divided signal C is a signal obtained by dividing the oscillation signal of the voltage-controlled oscillator 110 (oscillating at the free-run frequency) by N in a state in which the synchronization signal is not present. is there. The phase comparison output of the phase comparator 108 is converted into a direct current by the low pass filter 109 to control the oscillation frequency of the voltage controlled oscillator 110. When the station is present with a synchronization signal, the horizontal synchronization PLL circuit 106 is stable, and the frequency of the frequency-divided signal C of the frequency divider 107 is H.

The counter (B) 111 counts the oscillation signal of the voltage controlled oscillator 110. The signal D (frequency H) from the frequency divider 107
As a counting start signal, the counter (B) 111 is reset by the signal D, and the signal E is counted, as shown in FIG. When the code F of the counter (B) 111 and the code G of the up-down counter (A) 104 match, the code match detector 112 obtains the code match detection signal H. (Refer to the timing chart of FIG. 3) The code coincidence detector is composed of a plurality of EX-NOR gates 201 and AND gates 202 as shown in FIG.

By the code match detection signal H, the tuning display signal superimposing circuit 11
At 3, a constant voltage level is superimposed on the video signal A.
For example, as shown in FIG. 2, the tuning display signal superimposing circuit 113 includes an analog switch 203 and a power source 204 connected to the analog switch 203.
Composed of. The code match detection signal H closes the analog switch 203, and the video signal A is forcibly fixed to a constant voltage set by the power supply 204 during that period. As a result, the video signal 1 is output. (See FIG. 3) In the channel selection display device of the television having the above configuration,
A vertical strip-shaped tuning indicator 40 as shown in FIG. 4 is obtained on the screen.

〔effect〕

As described above, according to the present invention, the oscillation signal of the voltage controlled oscillator which is oscillating at N.H in the local state (there is a synchronization signal) is counted by the counter (B), and the up-down counter (A ) And the code match, the channel display signal is generated.Therefore, regardless of the presence / absence of a synchronization signal, that is, even if the horizontal synchronization PLL circuit is not phase-synchronized with the external synchronization signal, the voltage is always applied during the horizontal period of the TV screen. Since there is a fixed relationship with N oscillation signals of the controlled oscillator, the tuning indicator shifts from the normal position on the screen in a non-station state where there is no power supply fluctuation or synchronization signal, which was a problem with conventional circuits. Can be prevented.

Further, unlike the prior art, since no capacitor is required, the entire circuit can be monolithic to reduce the space.

[Brief description of drawings]

FIG. 1 ... Block diagram of channel selection display device according to the present invention FIG. 2 ... Block diagram of channel selection display signal generation circuit FIG. 3 ... Timing chart of each part of FIG. 1 and FIG. … Front view of TV screen displaying tuning indicator 101 is tuner, 102 is video detector, 103 is D / A converter, 10
4 is an up-down counter, 106 is a horizontal synchronization PLL circuit, 1
07 is a frequency divider, 108 is a phase comparator, 109 is a low-pass filter, 110 is a voltage controlled oscillator, 111 is a counter (B), 112
Is a code matching detector, and 113 is a tuning display signal superimposing circuit.

Claims (1)

[Claims] 1. A first counter for counting clock signals, and a digital counter for generating a voltage according to the count value of the counter.
An analog converter, a tuner that is supplied with the voltage as a tuning voltage, a video signal detector that generates a video signal based on the output signal of the tuner, a voltage-controlled oscillator, and a frequency-divided output signal of the voltage-controlled oscillator. A frequency divider, a phase comparator for comparing the phase of the horizontal synchronizing signal in the video signal and the output signal of the frequency divider, and the oscillation frequency of the voltage controlled oscillator based on the output value of the phase comparator. A horizontal PLL circuit including a low-pass filter that outputs a control voltage to be controlled, and a first signal obtained based on oscillation of the voltage-controlled oscillator are counted, and an output signal of the voltage-controlled oscillator is divided. Second reset by second signal obtained
A television selection comprising: a counter; and a tuning signal superimposing circuit that superimposes a constant voltage on the video signal in response to detecting that the count values of the first and second counters have a predetermined relationship. Station display.