JPS6268373A - Channel selection display device for television - Google Patents

Abstract

PURPOSE:To stabilize the position of the channel selection indicator at the screen by overlapping the constant voltage to the video signal when the coincidence of the code of the counter to count the oscillating signal of a VCO in a horizontal synchronizing PLL circuit and the up-down counter to generate the tuning voltage of the tuner is detected. CONSTITUTION:When the digital output signal of an up-down counter A104 is converted to the direct current tuning voltage by a D/A converter 103 and outputted to a tuner 101, in accordance with the tuning voltage, the channel is selected, the video is detected by a video detecting device 102 and a video signal A is outputted. A signal A is synchronized and separated by a synchronizing separator circuit 105, for a synchronizing separator signal B, the phase comparison with a frequency dividing signal C from a frequency dividing device 107 is executed by a phase comparator 108, the output is made into the direct current low-pass filter 109 and the oscillating frequency of a voltage controlled oscillator VCO110 is controlled. A counter B111 counts an oscillating signal E of the VCO110, is coincident to a code G of the up-and-down counter A104, and then, a code coincident detecting signal H is generated by a code incident detecting device 112, in a channel selection display signal overlapping circuit 113, the constant voltage level is overlapped to the video signal A and a video signal 1 is outputted.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a television channel selection display device.

[Decided invention]

The present invention relates to a channel selection display device for a television, and particularly to a channel selection display device that displays a channel selection indicator on the screen of the television by changing the brightness, and displays the indicator by moving it in the horizontal direction as the entire television tunes. A voltage controlled oscillator (hereinafter abbreviated as VCO) that oscillates at N times the horizontal synchronization signal frequency using a synchronous PLL circuit? The code includes a counter (13) that counts the oscillation signal of the VCO (frequency Nfl (, fH is the horizontal synchronizing signal frequency) and an up/down e counter (c) that generates the tuner tuning voltage in a digital code). When a match is detected, a constant voltage is superimposed on the video signal (
Clamp) Then, especially, the station selection indicator on the screen is placed vertically, W! The purpose of this invention is to obtain a stable channel selection display device that does not vibrate due to fluctuations in the source voltage or in a no-station state (a state in which there is no synchronizing signal).

[Conventional technology]

Known techniques for displaying a channel selection indicator on a television screen include JP-A-58-222679 and JP-A-54-12.
No. 4634.

In the first example, the flybank integrates the pulse to form a sawtooth wave, superimposes the sawtooth wave on the tuning voltage, compares it with a constant voltage, and if the voltages match, generates a pulse to indicate the tuning. is generated and displayed on the TV screen.

No. 42 IIHI''C similarly displays a channel selection indicator on the television screen using a multivibrator and a capacitor charging/discharging circuit.

[Problems and Objectives to be Solved by the Invention] However, in the conventional circuit, there were the following gaps.

If there is a power supply fluctuation, the slope of the integrated sawtooth wave will change in the first example, causing the tuning indicator to deviate from its normal position. The first column shows an example in which the flyback pulse is clipped with a Zener diode, etc. to prevent this, but since Zener diodes and other devices change the Zener voltage due to the bias current. , cannot be completely prevented.

Similarly, in the second example, when the power supply voltage fluctuates, the charging pin that charges the capacitor changes, and as a result, the channel selection indicator deviates from its normal position. .

Next, in a no-station state (a state in which there is no synchronizing signal between stations), since there is no horizontal synchronizing signal, the horizontal AFC circuit oscillates at a free-run frequency convergence. As a result, the frequency of fH deviates from the desired frequency, so the tuning indicator, which should be in the correct position when there is a station, becomes deviated when there is no station.
For example, in the case of π-, the frequency of the sawtooth wave is different between the stationed state and the non-stationed state, so the slope of the waveform changes in each state. ) The present invention improves the drawbacks of the conventional technology as described above,
A stable channel selection display device that does not fluctuate in the position of the channel selection indicator even when the power supply voltage fluctuates or there is no station.
The purpose is to obtain.

〔problem? Means to solve]

In order to solve the problems of the prior art as described in @, the channel selection display device of the present invention includes α) an up/down counter (
A).

b) A digital-to-analog converter (
(hereinafter abbreviated as D/A f converter) C) Electronic tuning tuner in which the DC voltage is taken as a tuning voltage d) IF signal from the electronic tuning tuner? e) A voltage-controlled oscillator that oscillates at N times the frequency of the horizontal synchronizing signal in the signal, and a voltage-controlled oscillator that divides the oscillation frequency of the voltage-controlled oscillator into 1/41. a frequency divider, and the phase of the frequency-divided signal divided by the frequency divider and the horizontal synchronization signal? A horizontal synchronous PLL circuit whose key is collected by a phase comparator for comparison and a low-pass filter that integrates the phase comparison signal from the phase comparator and applies it to the voltage controlled oscillator counts the oscillation signal of the voltage controlled oscillator. counter (
13) g) a code match detector for detecting a match between the codes of the up/down counter (A) and the counter (h) when a code match detection signal is generated from the code match detector;
It is characterized by being modified from a channel selection display signal superimposing circuit that superimposes a constant voltage level on the video signal.

[Effect]

In the present invention, by modifying vI by the means described above,
The oscillation signal of the voltage controlled oscillator that oscillates N, fg''C! in the horizontal synchronous PLL circuit (the oscillation frequency of N, fH in the case of a station)? counter (13) that counts, and the subsequent D/A
The converter has a code match detector that detects a code match when a part or all of the codes match with the up/down number counter (Jun) which generates a tuning voltage to the tuner. Furthermore, a code match detection signal generated therein is used to superimpose a certain voltage level on the video signal detected by the video detector and modulate the brightness, thereby displaying a channel selection indicator on the screen.

[Specific examples]

Embodiments of the present invention will be described below with reference to the drawings.

Figure 1 is a block diagram of a television channel selection display device according to the present invention. It is a 101 tuner. 104t: is an up/down counter (A) for generating a tuning voltage,
The codes are added or subtracted by pulses generated by an external switch or a clock signal forming circuit (none of which are shown). up/down-counter GA) 104
The digital output signal is converted into a DC tuning voltage by the D/A converter 103 and output to the tuner 101. The tuner 101 selects a channel according to the tuning voltage and generates an IF signal. The IF signal is subjected to video detection by a video detector 102, and a video signal A (see FIG. 3) is output.

The video signal A is synchronously separated by a synchronous separation circuit 105, and a synchronous separated signal Bi is output. (See Figure 3) 106 is a water synchronized PLL circuit. 110i11: Voltage controlled oscillator, when stationed, VC oscillates at N and fH. Therefore, the horizontal direction of the television screen is always divided into N by the oscillation signal, regardless of whether there is a station or not.

The oscillation frequency is controlled by the DC voltage from the voltage controlled oscillator 110Fi and the low pass filter 109. The oscillation signal E (see FIG. 3) of the voltage controlled oscillator 110 is divided by '5.
107 and the 1 frequency divider 107 output to the counter (E)
Then, the frequency of the oscillation signal is divided by N to generate a frequency-divided signal Ci, and a reference signal is supplied to the display section drive circuit 114 that drives the display section 115. Further, in the 1 phase comparator 108 which supplies the start signal Di to the counter 111, the synchronization separation signal B
B and C match as shown in Figure 3 when a station is present and a synchronization signal is present. Depending on the situation, the pulse width of the frequency-divided signal C does not match that of the synchronization separation signal B, but the phase relationship is constant.
The phase comparison output of the 0 phase comparator 108, which is obtained by dividing the oscillation signal of Control. If there is a station and a synchronous signal, l'i! : The horizontal synchronization PLL circuit 106 is stable and the frequency of the divided signal C of the frequency divider 107 is fH.

A counter 111 counts the oscillation signals of the voltage controlled oscillator 110. Note that the signal D (frequency fH) from the frequency divider 107 is used as the counting start signal, and as shown in FIG. 2, the counter (B) 111 is reset by the signal and continues counting the signal E. , 111 of the counter 0) and the code G of the up/down counter GA) 104 match, the code match detector 112 obtains a code match detection signal H. (Refer to the timing chart 1 in Figure 3) For example, as shown in Figure 2, the code coincidence detector includes a plurality of F'X-NOR gates 201 and AN
It is composed of a D gate 202.

Based on the code matching detection code H, the channel selection indication signal superimposition circuit 1
13, the one-channel moxibustion indicating signal superimposing circuit 113 that superimposes a constant voltage level on the video signal A is connected to an analog switch 203 and a power supply connected thereto, as shown in Fig. 2, for example. The analog switch 203 is closed by the code match detection signal HK, and the voltage is fixed at a constant voltage set by the forced Kttl[204 during the video signal suppression period.As a result, the video signal l is output. (See Figure 3) In the SIE television channel selection display device as described above, a vertically band-shaped channel selection indicator 40 as shown in FIG. 4 is obtained on the screen.

〔effect〕

As described above, according to the present invention, the oscillation signal of the voltage controlled oscillator oscillating at NJH in the stationed state (there is a synchronization signal) is counted by the gold counter (B), and the up/down counter GA) is counted. Since a channel selection display signal is generated when the codes match, regardless of the presence or absence of a synchronization signal, f, i.e., water synchronization PI, I, even if the circuit is not in phase synchronization with an external synchronization signal, the horizontal direction of the TV screen Since the period is always fixed to N@ minutes of the oscillation signal of the voltage controlled oscillator, the channel selection indicator on the screen will not show up in the absence of a synchronization signal or m source fluctuations, which were problems with conventional circuits. It is possible to prevent deviation from the normal position.

Also, unlike conventional technology, capacitors? Since it is not necessary, space can be reduced by combining circuits compared to monolithic circuits.

[Brief explanation of drawings]

Figure 1: Block diagram of the channel selection display device according to the present invention. Figure 2: Block diagram of the channel selection display word creation circuit. Figure 3:
・Figure 1, Figure 2 Timing chart diagram of each part Figure 4 ・Front view of the TV screen displaying the 1-channel selection indicator 101 is the tuner, 102 is the TV receiver, 103 is the D/
A converter, 104 is up/down e counter, 106V
107 is a frequency divider, lO8 is a phase comparator, 109 is a low-pass filter, 110 is a voltage controlled oscillator, 111 is a counter GB), 112 is a code
113 is a channel selection display signal superimposing circuit. that's all

Claims (1)

[Claims] a) Up/down counter for counting clock signals (
A), b) a digital-to-analog converter for converting the digital output signal of said up-down counter (A) into a DC voltage; c) an electronic tuning tuner to which said DC voltage is added as a tuning voltage; d) a signal from said electronic tuning tuner; A video detector that detects an IF signal and generates a video signal e) A voltage controlled oscillator that oscillates at N times the frequency of the horizontal synchronizing signal in the video signal, and the oscillation frequency of the voltage controlled oscillator is divided into 1/N. a phase comparator that compares the phase of the frequency-divided signal frequency-divided by the frequency divider and the horizontal synchronization signal; and a phase comparator that integrates the phase comparison signal from the phase comparator and outputs the signal to the voltage-controlled oscillator. a horizontal synchronous PLL circuit configured with a low-pass filter that applies voltage; f) a counter (B) that counts the oscillation signal of the voltage controlled oscillator; g) codes for the up/down counter (A) and the counter (B); A code match detector, h
) A television channel selection display device comprising a channel selection display signal superimposing circuit that superimposes a constant voltage level on the video signal when a code match detection signal is generated from the code match detector.