JP2552313Y2 - Display area correction circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a display area correction circuit applicable to an image display device such as a liquid crystal television.

[Prior Art and Problems to be Solved] In an image display device such as a liquid crystal television, a PLL circuit locks a phase of a horizontal synchronization signal generated internally to a horizontal synchronization signal of a video signal. However, due to variations in individual products and the effects of temperature changes, the phase comparison output is locked with a change occurring, and the screen is displaced and the left and right sides of the screen may be missing.

The present invention has been made in view of the above circumstances, and has an object to correct a screen shift caused by variations in individual products.

[Means and Actions for Solving the Problems] In order to achieve the above object, the present invention compares a means for sampling a video signal with a horizontal synchronization signal of the video signal and a phase of a horizontal synchronization signal generated internally, Means for detecting a phase advance or delay, and means for changing the display position of a horizontal scanning line by changing the sampling start timing of the sampling means according to the detection result of the means. To provide a display area correction circuit.

With this configuration, even if the phase comparison signal of the PLL circuit fluctuates, the display position of the horizontal scanning line on the screen is changed by changing the sampling start timing for sampling the video signal according to the fluctuation. This can prevent the left and right sides of the screen from being chipped.

[Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numeral 1 denotes a PLL circuit to which a composite synchronizing signal CS is input, and outputs an oscillation clock OSC of the voltage controlled oscillator VCO and an internal horizontal synchronizing signal φH to the timing circuit 2 and a phase comparison signal PD to the detection circuit 3, respectively. The timing circuit 2 generates various timing signals in response to the oscillation clock OSC and the horizontal synchronization signal φH. The timing circuit 2 sends the basic clock CK, the sampling clock φS, and the internal horizontal synchronization signal φH to the detection circuit 3 for driving the liquid crystal. Various timing signals are supplied to the liquid crystal drive circuit 4 respectively. The detection circuit 3 is a circuit for detecting a change in the phase comparison signal PD.
The sampling clock φS is supplied to the A / D conversion circuit 5 at a timing corresponding to the fluctuation of the phase comparison signal PD detected in the step (1). The analog video signal VD is supplied to the A / D conversion circuit 5. The analog video signal VD is sampled by the sampling clock φS, converted into digital data, and supplied to the liquid crystal drive circuit 4.

FIG. 2 shows the configuration of the PLL circuit 1, and FIG.
4 is a time chart showing signal waveforms of main parts of the figure.

In FIG. 2, 1H as shown in FIG.
(Horizontal scanning period) A clock pulse φH having a period and a duty of 50% is input, and a composite synchronizing signal CS obtained from a video signal as shown in FIG.
It is input as a control signal via 13. The analog switch 11 is opened and closed in accordance with a composite synchronizing signal CS inputted from a terminal 12 via an inverter 13, and controls a 1H (horizontal scanning period) cycle of the input reference signal and a clock pulse φH at a duty of 50%. Phase comparison signal as shown in
The PD is output to the low-pass filter 14. This low-pass filter 14 integrates the phase comparison signal PD input from the analog switch 11 and outputs it to a voltage controlled oscillator (VCO) 15. The voltage-controlled oscillator 15 generates an oscillation clock OSC having an oscillation frequency fvco of several MHz determined by the output voltage level input from the low-pass filter 14, outputs the oscillation clock OSC to the output terminal 16, and outputs the oscillation clock OSC to the frequency divider 17. The frequency divider 17 divides the frequency of the oscillation clock OSC input from the voltage controlled oscillator 15 and uses a clock pulse φH of 1H (horizontal scanning period) and 50% duty as a comparison signal as a reference signal to the analog switch 11. Output. Then, the clock pulse φH
Is used as an internal horizontal synchronization signal, sent to the timing circuit 2 together with the oscillation clock OSC, and the phase comparison signal PD is sent to the detection circuit 3. The PLL circuit 1 is a negative feedback circuit composed of a phase comparison analog switch 11, a low-pass filter 14, a voltage controlled oscillator (VCO) 15, and a frequency divider 17, and is a comparison signal of the analog switch 11. The control voltage of the voltage controlled oscillator 15 is automatically controlled so that the input clock pulse φH and the composite synchronizing signal CS as a control signal are synchronized. Therefore, the clock pulse φ
When the phase of H advances with respect to the composite synchronizing signal CS, the low level period B of the phase comparison signal PD becomes longer as shown in FIG. 4A, and when the phase of the clock pulse φH is delayed, as shown in FIG. ), The period A of the high level of the phase comparison signal PD becomes longer.

FIG. 5 is a diagram showing a configuration of the detection circuit 3. PLL
The phase comparison signal PD input from the circuit 1 is input to the high-level detection circuit 21 where only the high-level portion A of the waveform is detected and the low-level detection circuit 22 detects only the low-level portion B of the waveform. You. The detected high level part A and low level part B are each a pulse width detection circuit.
The length is measured by counting the number of reference clocks CK during the high level period or the low level period according to 23 and 24, and the length is measured, and the comparison circuit 25 compares them. The enable signal generation circuit 26 receives the internal horizontal synchronizing signal φH and the reference clock.
An enable signal EN for determining the sampling timing of the video signal during one horizontal scanning period is generated based on CK. The timing of the enable signal EN is changed according to the comparison output of the comparison circuit 25. That is, the pulse width detection circuits 23 and 24 measure the pulse width in the form of the count number of the reference clock CK, and output this to the comparison circuit 25. The comparison circuit 25 subtracts the two, and determines the phase delay based on the sign, and also determines the phase shift amount based on the magnitude of the subtraction value. Then, the time from the edge of the internal horizontal synchronization signal φH to the rise of the enable signal EN is adjusted by changing the number of times of counting the reference clock CK in accordance with the magnitude of the subtraction value, thereby generating the enable signal EN. It is. The gate circuit 27 sends the sampling clock φS sent from the timing circuit 2 to an enable signal.
The signal passes through only the period when EN is at a high level, and is transmitted to the A / D conversion circuit 5.

Next, the operation of the above embodiment will be described. Composite sync signal CS
And when the phase of the internal horizontal synchronizing signal φH matches, the third
As shown in the figure, the high level portion and the low level portion of the phase comparison signal PD are equal. Here, assuming that the phase of the internal horizontal synchronizing signal φH has advanced due to variations in elements, the influence of temperature changes, and the like, the high level portion A of the phase comparison signal PD is lower than the low level portion B as shown in FIG. Since the internal clock generated based on this becomes faster with respect to the video signal, the sampling timing also becomes earlier, and a stripe appears on the left end of the screen as shown in FIG. I can see it. That is, in FIG. 7, the center of the video signal VD is normally sampled using the enable signal EN as a window during one horizontal period of the video signal VD as shown in FIG. If the internal horizontal synchronizing signal φH is advanced earlier, the rise of the enable signal EN is also advanced as shown in FIG. 9G, and sampling may start before the display image is displayed as shown in FIG. At this time, the detection circuit 3 compares the lengths of the high-level portion A and the low-level portion B of the phase comparison signal PD, and when the comparison circuit 25 determines that the low-level portion B is shorter, the enable signal generation circuit 26 On the other hand, the rise of the enable signal EN is delayed. The enable signal generation circuit 26 generates an enable signal EN having a phase delayed with respect to the internal horizontal synchronization signal φH in FIG. This is substantially equal to FIG. 11 (d), so that the gate circuit 27 has a delayed sampling timing for the internal horizontal synchronizing signal φH as shown in FIG. Since the sampling signal φS having almost the same phase is output, normal display can be performed.

On the other hand, if the phase of the internal horizontal synchronizing signal φH is delayed as shown in FIG. 7 (i), the high level portion A of the phase comparison signal PD is lower than the low level portion B as shown in FIG. 4 (b). Since the internal clock generated on the basis of this becomes longer than the video signal VD as shown in FIG. 7 (i, k), the sampling timing is also delayed, and the internal clock generated as shown in FIG. As shown in the figure, a stripe appears at the right end of the screen. Upon detecting this, the detection circuit 3 performs the correction by advancing the enable signal EN and advancing the sampling timing in a manner opposite to the above.

Therefore, even if the PLL circuit is locked with the phase of the internal horizontal synchronizing signal being shifted for some reason, the display position of the screen can be corrected and a normal display can be performed.

[Effects of the Invention] Since the invention is configured as described above, even if the phase comparison signal of the PLL circuit fluctuates, the sampling start timing for sampling the video signal is changed in accordance with the fluctuation, whereby the horizontal position of the screen is changed. Since the display position of the scanning line is changed, the left and right sides of the screen can be prevented from being chipped.

[Brief description of the drawings]

The drawings show an embodiment of the present invention. FIG. 1 is a block diagram showing the overall configuration, FIG. 2 is a diagram showing the configuration of the PLL circuit of FIG. 1, and FIG. 3 is an operation of FIG. FIG. 4 is a time chart for explaining, and FIG.
FIG. 5 is a diagram showing the configuration of the detection circuit of FIG. 1, FIG. 6 is a diagram for explaining the state of the display screen, and FIG. 7 is a time chart for explaining the operation of FIG. 1. PLL circuit 2. Timing circuit 3. Detection circuit 4. Liquid crystal drive circuit 5. A / D conversion circuit

Claims (1)

(57) [Scope of request for utility model registration] A display area correction circuit of a display device for sampling a video signal and displaying the sampled video signal on a display means, comprising: a means for sampling a video signal; a horizontal synchronization signal for the video signal and a horizontal synchronization signal generated internally. Means for comparing the phases and detecting the advance or delay of the phase; and means for changing the display position of the horizontal scanning line by changing the sampling start timing of the sampling means according to the detection result of the means. And a display area correction circuit.