JPS59224928A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To improve the temperature characteristic of an oscillating circuit suitable for a driving pulse generating circuit and starting oscillation always at the same phase in synchronizing with a trigger pulse by providing an oscillator, a frequency dividing circuit frequency-dividing an output pulse of the oscillator and an FF circuit. CONSTITUTION:The oscillator 50 starts oscillation at the same phase in synchronizing with the trigger pulse 16 and its oscillating frequency is controlled by a power supply voltage. A frequency dividing circuit (counter circuit) 51 frequency- divides an output pulse of the oscillator 15 into 1/m. Since a pulse generated from the frequency dividing circuit 51 is superimposed on a video signal and becomes a noise source deteriorating a screen, its operation is controlled by the FF circuit 54, causing the oscillator to be operated only at the outside of a horizontal blanking period not causing a video output. That is, the circuit 54 is set by a horizontal synchronizing pulse 16 and an operation command signal Q is given to the circuit only during the set period. The circuit counts an input pulse from the oscillator 50 accordingly and an output pulse in counting m set of pulses during the horizontal blanking period resets the circuit 54.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pulse generation circuit, and particularly to a pulse generation circuit suitable for generating drive pulses for a television camera using a solid-state image sensor.

[Background of the invention]

The MO8 type solid-state image sensor has a light-receiving section composed of photodiodes arranged in a matrix, and by switching vertical and horizontal readout switches connected to the photodiodes in an orderly manner, optical signals are read in a time (1) series. It is designed to be read out sequentially as a signal.

In this case, the vertical and horizontal readout switches are opened and closed by each output pulse of the vertical and horizontal shift registers built into the solid-state image sensor, and in order to operate these vertical and horizontal shift registers, two-phase vertical clock pulses and vertical A start pulse, a two-phase horizontal clock pulse and a horizontal start pulse are required.

Furthermore, in order to convert the output signal of the solid-state image sensor into a television signal, blanking pulses, horizontal and vertical synchronization signals, etc. are also required.

Conventionally, these pulses are generated by using an oscillator circuit to generate high-frequency pulses from several MHz to 10-odd MHz, which are divided to a predetermined frequency by a frequency divider circuit, and the output pulses from each stage of the frequency divider circuit are combined by a logic circuit. By doing so, we were able to obtain the various pulses we needed.

By the way, in conventional solid-state cameras, synchronous noise that appears in the image output has been a major problem, but the inventors have determined that the source of the synchronous noise is as described above (2) between the frequency dividing circuit and the logic circuit. He noticed that there was a problem with drive pulse generation circuits consisting of combinations, and proposed a drive circuit with a new configuration that solved this problem in Utility Model Application No. 54-138412.

In other words, if a method is adopted in which an oscillator circuit generates high-frequency pulses and a frequency divider circuit (counter circuit) is used to reduce this to a predetermined low frequency, the pulse noise generated at each stage of the frequency divider circuit is jumps into the output signal line via the line, ground line, or by capacitive coupling, etc.
In particular, noise pulses on the horizontal shift register side appear as vertical striped noise on the screen. The feature of the drive circuit of the above application that solves this problem is that the horizontal synchronization frequency pulse is
By generating horizontal clock pulses generated by one oscillator and synchronized with this by a second oscillator, the required pulses on the horizontal shift register side can be created without using a frequency divider circuit, while preventing synchronous noise from appearing on the screen. On the vertical register side, which is not affected, a frequency divider circuit is used to generate pulses of the desired frequency from high-frequency oscillation pulses.

(3) The main parts of this drive pulse generation circuit will be further explained with reference to FIG. 1. First, the oscillator 34 oscillates a horizontal synchronization frequency to obtain the horizontal synchronization pulse 16. Horizontal sync pulse 1
6 is used for synchronously generating the horizontal clock pulse generator 35. Horizontal clock pulse generator output 25
together with the pulse 17 generated by the delay circuit 36 and the pulse width control circuit 37 becomes a two-phase horizontal clock pulse.

The horizontal synchronizing pulse 16 is also applied to a pulse width control circuit 38 and a horizontal blanking pulse generation circuit 39.

The output pulse of the pulse width control circuit 38 is combined with the horizontal synchronization pulse 16 in the logic circuit 40 to generate the horizontal synchronization signal (H-
8YNC pulse) becomes 20. H・5VNC pulse 20
also becomes the clock pulse that drives the vertical shift register.

In addition to being used as a vertical clock pulse, the horizontal blanking pulse 21 is combined with the horizontal clock pulse 25 in the horizontal input pulse generation circuit 41 to generate the horizontal input pulse 29.
becomes.

(4) Also, the pulse 21 is a counter circuit 42, a logic circuit 43.4
4, these circuits produce a vertical input pulse 30 and a composite blanking signal. Also, vertical synchronization signal generation 4
6 creates a composite synchronization signal together with a logic circuit 45.

However, although the conventional drive pulse generation circuit shown in FIG. 1 can eliminate synchronous noise, there is a problem with the temperature stability of the horizontal clock pulse generation circuit 35, and the oscillation frequency fluctuates by several percent with a temperature change of 60°C. Temperature stability is achieved by using a crystal resonator in a normal oscillation circuit, but a crystal cannot be used in a circuit that synchronizes with a horizontal synchronization signal and always performs synchronous oscillation with the same phase. .

[Object of the Invention] The present invention has been made in view of the above reasons, and provides an oscillation circuit that always starts oscillation at the same phase in synchronization with a trigger pulse, which is suitable for a drive pulse generation circuit for a solid-state image sensor. The purpose is to improve temperature characteristics.

[Embodiments of the invention]

1(5) FIG. 2 shows one embodiment of an oscillation circuit according to the invention, which corresponds to circuit 35 in FIG.

In the figure, 50 is the trigger pulse (horizontal synchronization pulse)
This is an oscillator that starts oscillating in synchronization with 16 and with the same phase, and uses, for example, a Schmitt circuit S as shown in FIG. 3, and its oscillation frequency can be controlled by the power supply voltage (voltage at terminal C).

51 is a frequency dividing circuit (counter circuit) for dividing the output pulse of the oscillator 50 into 1/m.

As already mentioned in the detailed explanation of the invention, the pulses generated in the division circuit become a noise source that is superimposed on the video signal and degrades the screen.
The operation of the divider circuit is controlled by a slip-flop circuit 54, so that the frequency divider circuit operates only during the horizontal blanking period when no video output occurs.

That is, the flip-flop circuit 54 is set by the horizontal synchronizing pulse 16, and the frequency divider circuit 5 is set only during the set period.
The 6th division circuit 51 which gives the operation command signal Q to the oscillator 1 starts counting the input (6) pulses from the oscillation $50, and calculates m within the horizontal blanking period.
The flip-flop 54 is reset by the output pulse when the number of pulses is counted.

4 shows waveforms of various parts of the circuit shown in FIG. 2, 16 is a trigger pulse synchronized with the horizontal synchronization signal, 25 is a horizontal clock pulse generated by the oscillator 50, and 51S is an output pulse of the frequency dividing circuit 51. Further, Q is an output pulse of the flip-flop circuit 54, and this pulse width is equivalent to m clock pulses 25. When the frequency of the clock pulse 25 changes due to temperature or the like, the pulse width of the output pulse Q of the flip-flop also changes.

Therefore, when the output pulse Q of the flip-flop circuit 54 is integrated by the integrating circuit 52, its DC level is determined by the oscillator 5.
It is proportional to the frequency of 0.

In the circuit of the present invention, the output of the integrating circuit 52 is input to the differential amplifier circuit 53 and compared with a reference voltage 55, and the power supply voltage of the oscillator 50 is controlled with an output voltage proportional to the difference between the two.

As is clear from the above embodiments, according to the present invention (7), even if the frequency of the output pulse 25 of the oscillator 50 fluctuates, this can be automatically corrected without causing synchronous noise, resulting in stable operation. can be done.

In the above embodiment, the output pulse Q of the flip-flop circuit 54 was used as the pulse for detecting the DC level.
Instead of the above pulse Q, the output pulse 51S of the frequency dividing circuit 51
may also be used. Further, the counter circuit 51 generates horizontal blanking pulses by counting the clock pulses 25, and the pulses of various pulse widths generated in this process can be used for the above-mentioned DC detection, and any pulse width can be used. By appropriately selecting the reference voltage 55, the oscillator 50 can be caused to oscillate at a desired frequency.

Further, as shown in FIG. 5, the V of the DC component detection pulse 60 is
. If the drift of LpVOll becomes a problem, for example, as shown in FIG. 6, the transistor 61 and the resistor 62 .
The output 68 of the reference voltage circuit 63 and the output (8) 69 of the DC component detection circuit consisting of the transistor 64, resistors 65, 66, and capacitor 67 may be applied to the differential amplifier 53, respectively.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an example of a drive pulse generation circuit for a solid-state image sensor, and 2yA is a block diagram showing an example of a drive pulse generation circuit for a solid-state image pickup device. FIG. 3 is a circuit diagram showing an example of the pulse generating circuit shown in FIG. 2, and FIG.
This figure is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 2, and FIGS. 5 and 6 are signal waveform diagrams and circuit diagrams for explaining the present invention in detail. In FIG. 2, 50 is an oscillator, 51 is a frequency dividing circuit, and 52
53 is an integrating circuit, 53 is a differential amplifier, and 54 is a flip-flop circuit. Agent Patent Attorney Akio Takahashi (9) Su I Seki

Claims (1)

[Claims] A pulse oscillator that oscillates in synchronization with a trigger pulse, a counter circuit that periodically counts the output pulses of the pulse oscillator by a predetermined number, and means that outputs a DC voltage proportional to the counting operation period of the counter circuit. , means for controlling the operation of the pulse oscillator according to the DC voltage.