JPH088650B2 - Frequency control circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency control circuit which can be used in a horizontal synchronizing circuit of a display device for displaying signals of various signal sources in which the synchronizing signal changes in a wide range from 15 kHz to 40 kHz. Regarding

Conventional technology In a conventional CRT display device, the horizontal oscillation / AFC circuit system is adjusted to the horizontal frequency of the input signal by 15-40kH.
When operating in the z range, there are many systems in which the CR or LC time constant of the oscillation circuit is switched or the time constant of the low-pass filter of the AFC circuit is switched. In these methods, for example, 15 to 20 kHz in the combination of the first time constant,
22 to 27 kHz with the second time constant combination, 28 to 33 kHz with the third time constant combination, 40 to 43 kHz with the fourth time constant combination
Each Hz is oscillated to cover the required frequency range.

The problem to be solved by the invention is that, in the conventional circuit configuration, it is necessary to switch the circuit of 3 to 4 types of time constants as described above in order to cover and oscillate the range of 15 to 40 kHz. If the number of combinations of constants is reduced, the oscillation will stop or become unstable at the boundary of the frequency.

It is an object of the present invention to solve the above problems and provide a frequency control circuit which stably oscillates in a wide range of frequencies and has no oscillation discontinuity.

Means for Solving the Problems In the present invention, the original oscillation is stabilized by a crystal oscillator circuit, and a PLL loop is formed and reset so as to be synchronized with an external input synchronizing signal, so that stable oscillation is achieved over a wide range. Is configured as follows.

Effect According to the present invention, the frequency division ratio of the original oscillation can be automatically switched according to the frequency of the external input synchronizing signal to obtain the oscillation output phase-locked with the external input synchronizing signal, and the deflection based on the oscillation output can be obtained. By generating a sawtooth voltage for
Stable deflection can be achieved.

Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 and 2. In FIG. 1, reference numeral 1 is an original oscillator of a crystal oscillation circuit, which oscillates at 14 kHz, for example, and a counter 2 acting as a frequency divider divides its oscillation output. A flip-flop (FF) 5 compares the phases of the divided output and the external input synchronizing signal. The oscillator 1, the counter 2, the inverter 8, the flip-flop 5, the LPF 6, and the buffer amplifier 7 form a PLL loop. The frequency division ratio of the counter 2 is written in the latch memory 4 as a frequency division ratio corresponding to the frequency of the external input synchronizing signal by means described later, so that the change can be followed even if the frequency of the external input synchronizing signal changes. To do so. The output of the comparator 3 is synchronized with the external input synchronizing signal, and the pulse output drives the sawtooth wave generation circuit for CRT deflection.

 The operation will be described in detail below with reference to FIG.

The original oscillator 1 is oscillated at, for example, 14.31818 MHz. The frequency divider can divide by 1/4096 with the 12-bit counter 2,
When divided by 1/4096, it becomes about 3495.6 Hz. 34 for 1/4095
It becomes 96.5Hz, and becomes a step of about 1.0Hz. Considering around 15.75kHz, the frequency division ratio of 1/910 is 15.734kHz, and the frequency division ratio of 1/909 is 15.7.
It becomes 52kHz, and becomes a step of about 18Hz. Also, 1/320 is 44.7
44kHz, 1/319 becomes 44.885kHz, in this part about 140Hz
It becomes the tick of. If this circuit covers the range of 15kHz to 45kHz, the maximum difference is 150Hz or less with respect to the external input synchronizing signal. Considering the original oscillation of 14MHz, the difference of 150Hz becomes the difference of 48kHz. That is, for 14.31818MHz,
If the frequency is shifted by 48KHz, the difference between 44.885KHz and 44.744KHz can be absorbed with the same division ratio to stably operate the PLL loop. Actually, it is only necessary to change at ± 24 KHz with respect to 14.31818 MHz, and it is assumed that the frequency of the oscillator 1 stably changes at ± 24 KHz for the explanation of the principle of the present invention. The flip-flop 5 of FIG. 1 is set by the front pulse of the output of the counter 2 (1/910 frequency division output) and reset by φ1. The Q output of the flip-flop 5 is integrated by the LPF 6, the obtained DC voltage is amplified by the buffer amplifier 7 to an appropriate DC level, and the voltage-dependent impedance element (eg, varicap) forming the oscillator 1 is controlled. A PLL loop is formed by changing the oscillation frequency.

Now, consider the actual operation in two parts. First, φ ₁
2 does not match the output of the comparator 3, the outputs φ ₂ and φ ₁ of the sampling gate 13 are t ₁₀ -t in FIG.
_It looks like ₂₁ . Here, the repetition of φ ₂ has a higher frequency than φ ₁ . The output of the comparator 3 is generated in the central portion of φ ₂ , and the FF constituting the sampling gate 13 has an output pulse of "0, 1" of the counter 2 and an appropriate time, for example, "32" count or " The 64th count pulse is added, set and reset, and the coincidence output of the comparator 3 is generated with a delay of "16" or "32" clocks. For this purpose, the output of the counter 2 is decremented by, for example, "32" counters and stored in the latch memory 4. In this way, in the synchronized state, the output of the comparator 3 can be obtained in the same phase as φ ₁ shown in T ₁₀ of FIG. By doing this, the counter 2
Even if the point at which is reset changes, the sampling gate pulse always has a 64-bit width (or 32-bit width) with the output of the comparator 3 in the center.

When not synchronized, the relationship between φ ₂ and φ ₁ is shown in Fig. 2.
t _{10 to} t ₂₁ and almost all φ ₁ are AND gates 12
Pass through. Since phi phi ₁ to be the phi ₁ contained within a period of low level immediately (e.g. within one second) of ₂ out of the low level period of phi _2, the counter 11 is the phi ₁ to 56 counts. If the counter 11 counts 56 φ ₁ before 64 φ ₁ comes, the counter 11
The output φ ₃ of T goes high at T ₀₁ . That is, the counter 11 is φ
Assuming that the leading edge of ₁ is counted, as shown in T ₀₁ of FIG. 2, the portion except the leading edge of φ ₁ passes through AND gate 10 and becomes φ _{4 because} φ ₃ is at a high level, and passes through OR gate 9. , Clear counter 2. φ ₄ has almost the same phase as φ ₁ (the trailing edge is the same if gate delay is ignored), and the counter 2 starts from φ ₁
The frequency division is started in synchronization with. On the other hand, before T ₀₁ , as shown in FIG. 2, the output of the comparator 3 is obtained in correspondence with the frequency division of the counter 2, whereby the sawtooth wave generating circuit 19 produces a sawtooth wave for deflection such as φ _8. It has occurred. Various operations from T ₀₁ can be considered depending on the configuration of the sawtooth wave generation circuit 19, but here it is assumed that the maximum point of the sawtooth wave continues for T _{0y to} T _{10 as} shown in the vicinity of T _{11 in} FIG. . at the trailing edge of φ ₄ (1
The pulse generation circuit 17 of + Δ) H width (H is a horizontal scanning period, the value of H changes depending on φ ₁ ) is triggered. Therefore, φ ₆ appears at the output of the AND gate 15 at the next φ ₁ (T ₁₀ ), and the value of the counter 2 at that time is loaded into the latch memory 4 by φ ₆ . It is desirable that the width of φ ₆ be shorter than one cycle of oscillation of the original oscillator 1. Further, at this time, the value of the counter 2 is loaded into the latch memory 4 after decrementing by "32", for example. The sawtooth wave output from the sawtooth wave generation circuit 19 from T ₁₀ also has a waveform synchronized with φ ₁ .

Once synchronization takes place at T ₁₀ , the rest becomes a sawtooth wave with the same period as φ ₁ .

Now, when T ₁₁ and T ₁₀ are described in detail, when the counter 2 is reset by φ4 at T ₀₁ , the output of the counter 2 becomes 0 (low level). At this time, the latch memory 4 is cleared at the same time, but when cleared, all the outputs of the latch memory 4 become 1 (high level).
By configuring the above, it is possible to prevent the coincidence output of the comparator 3 from appearing at T ₁₀ . Therefore, at T ₁₀ , the output of the comparator 3 does not appear and the counter 2 is cleared at φ ₆ . Clear counter 2 phi _4, cleared by phi _6. Counter 2
Is cleared at the trailing edge of φ ₄ and φ ₆ ,
_The above-mentioned subtraction (decrease the "32" count from the output of the counter 2) may be completed in a high level period of ₆ (for example, 50 nsec to 100 nsec), which is possible in the hard logic. Therefore, after the data of the counter 2 is subtracted and written into the latch memory 4 by φ ₆ at T ₁₀ , the next data is written.
From T ₂₁ the gate phi ₂ withdrawn from the position of FIG. 2 T ₁₁ are formed, blocking the input of the AND gate 12. Counter 11 is T ₀₁
It goes high for a maximum of 8 pulses (for φ ₁ 8), but when it is cleared by the 64th pulse output of the counter 14,
After that, the counter 11 does not count because the AND gate 12 does not output as long as the synchronization is normal, and the output φ _{3 of the} counter 11 is at a low level. If the vertical blanking period (VBL) starts after T ₀₁ , the counter 2 will be cleared by a pulse of 1/2 cycle of φ ₁ , but will return to the normal state eventually.

Further, since the maximum 8 pulses φ ₁ have the same phase as the outputs of φ ₄ , φ ₆ and the comparator 3, the output of the OR gate 9 is φ ₄ , φ ₆ or the output of the comparator 3. Has spread slightly, and there is no effect.

With the configuration as described above, stable pulses synchronized with any frequency between 15 and 45 kHz can be obtained.

Note that the relationship as shown in Fig. 2 t _{10 to} t _y2 continues until the synchronization pull-in, but normally the field frequency of a CRT display is 60H.
Since it is about z, it becomes T ₀₁ and is drawn in within 1 to 2 seconds.

Figure 3 shows the timing after T ₀₁ when φ ₁ is used as a reference. P ₂ is T ₀₁ . φ ₁ pulse width of 50ns
ec and the oscillation frequency of the original oscillator 1 is 14.31818 MHz, the width of one pulse interval of the output of the original oscillator 1 is about 70 nsec. Therefore, in the case of FIG. 3, P _{2 to} P ₁₁ are 75 nsec.
40n and if this in action is inappropriate P ₂ ~P ₇ (ie, φ ₁ of width)
If it is sec, P _{2 to} P ₁₁ will be 65 nsec. P ₁ ~P ₅ is 5nsec
Step, P ₅ ~ P ₆ is 30nsec, P ₆ ~ P ₁₀ is 5nsec step, P ₁₀ ~ P ₁₁
Is every 10 nsec. As described above, the output of the counter 2 is cleared at the trailing edge P ₁₀ of φ ₄ (or φ ₆ ) and becomes "0" at P ₁₁ , while the latch memory 4 starts from P ₅ to the counter 2.
Is subtracted, and the subtraction result is stored in P ₁₀ , for example. There is no problem if P ₉ is closer to P ₅ . The output of the comparator 3 has a jitter of about ± 5 nsec relative to φ ₁ . In reality, φ ₁ is often jittered.

Next, the configuration of the (1 + Δ) H width pulse generation circuit 17 will be supplemented. The circuit 17 is constructed as e.g. of FIG. 4, phi ₄
FF17F is set at the trailing edge, its Q output is added to the OR gate 17G, and the monostable multivibrator 17M is triggered at the next φ ₁ . At time T ₀₁ , Q of FF17F is low level, so it is not triggered by φ ₁ but triggered by T ₁₀ . The Q output of the monostable multivibrator (MM) 17M is delayed by the buffer circuit 17R, and the NAND gate 17A obtains a thin negative pulse at the trailing edge of the Q output of the MM 17M. If FF17F is reset here, the output of the OR gate 17G has a pulse width of (1 + Δ) H, and Δ is determined by the pulse width of the monostable multivibrator 17M.

Next, the comparator 3 and the latch memory 4 will be supplemented with reference to FIG. Counter output is a hard logic subtraction circuit
It is always subtracted (decremented by "32" count) at 4C,
The output is loaded into the latch memory 4M at the trailing edge of φ ₆ .
The output of the comparator 3C becomes a high level output 32 clocks less than the correct division ratio, and this is delayed by the 32-bit shift register 3S, so the output of the shift register 3S is output at the normal division ratio. It

On the other hand, to the sampling gate generation FF13, the comparison output (1
(Bit width) is added and the FF13 is set at the trailing edge, and the FF13 is reset by the inverted output (negative pulse) of the 32nd bit of the counter ₂ to obtain φ ₂ .

An example of the sawtooth wave generation circuit 19 is shown in FIG.

The output of the comparator 3 is inverted by the inverter 19R and the flip-flop 19F for the PLL4 detector is reset. On the other hand, the output of the oscillator 19S is divided into 1/256 by the counter 19C, and the counter 19C
To the D / A converter 19D to form a sawtooth wave output. During the frequency-divided output of counter 19C, the output is exactly 180 ° out of phase with the output of inverter 19R (128th bit output)
Is extracted as a thin negative pulse and FF19F is set. When phase locked, the duty ratio of Q output of FF19F is 5
It becomes 0% and the frequency of the oscillator 19S is a constant value (256 times φ ₁ )
become. 19A is a buffer amplifier and 19L is a low pass filter (LPF).

As described above, according to the present invention, the oscillation output can be obtained by continuously and stably pulling in the phase with respect to the external input synchronizing signal whose horizontal frequency is at least twice as large as that of the external input synchronizing signal. It is possible to eliminate the need for switching, operate normally even if the external input synchronizing signal is interrupted for a moment, and ignore the impulse noise added to the external input synchronizing signal and obtain a stable oscillation output.

[Brief description of drawings]

FIG. 1 is a block diagram of a frequency control circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation thereof, FIG. 3 is a partially enlarged waveform diagram of the waveform, and FIGS. , FIG. 6 is a detailed circuit diagram of a part thereof. 1 ... Original oscillator, 2 ... Counter, 3 ... Comparator, 4 ...
Latch memory, 5 Flip-flop for PLL detection, 6 low pass filter (LPF), 7 buffer amplifier, 8 inverter, 9 OR gate, 10 AND gate, 11 ... Counter, 12 …… AND gate, 13 …… Sampling gate generation circuit, 14 …… Counter, 15 …… AND gate, 1
6 …… Inverter, 17 …… Pulse generator, 18 …… Buffer amplifier, 19 …… Sawtooth wave generation circuit.

Claims (2)

[Claims] 1. An oscillation circuit forming a PLL loop is formed of a crystal oscillation circuit, and an oscillation frequency is at least 100 times higher than a frequency f _s of an external input synchronizing signal, and an output of the oscillator is divided. A circuit for presetting the division ratio of the counter-type frequency divider to a value corresponding to the frequency of the external input synchronization signal is provided, and the phase of the external input synchronization signal and the phase of the output obtained by dividing the output of the oscillator are arranged. A frequency control circuit, characterized in that the frequency divider is configured to be reset and newly preset only when the phase difference exceeds a certain value. 2. A latch circuit is provided with means for writing a frequency division ratio corresponding to an external input synchronizing signal, and a comparator circuit for comparing the contents of the latch memory with the output of the frequency divider counter, and the horizontal deflection is performed by the output of the comparator circuit. The frequency control device according to claim 1, which controls a sawtooth wave generation circuit that drives the system.