JPH0761012B2 - PLL circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and particularly to a reference clock of a digital signal when recording / reproducing a digital signal using a rotary head and a recording frame. The present invention relates to a PLL circuit that synchronizes a phase with a drum flip-flop (DFF) signal indicating a reference position.

[Conventional technology]

When digitally recording / reproducing a video signal or an audio signal, the phase of a high frequency reference clock of the digital signal and the DFF signal of a relatively low frequency are often synchronized.

Therefore, in the conventional PLL circuit of this type, the reference clock of the digital signal and the DFF signal are phase-synchronized by using the PLL.

FIG. 10 is a block diagram showing an example of a conventional synchronous circuit portion, and FIG. 11 shows output waveforms of respective portions in FIG.

In FIG. 10, reference numeral 1 is a DFF signal input terminal.
The FF signal is a signal whose state changes according to the change of the rotation phase of the drum. As shown in FIG. 11 (A), the FF signal has half the frequency of the vertical synchronizing signal of the video signal, and its duty ratio is It is almost 50%.

The DFF signal applied to the input terminal 1 is supplied to the phase comparator 2
Applied to. The phase comparator 2 includes a pulse generator 3
As a result, the phase comparison pulse shown in FIG. 11 (B) is applied, and the comparison output of both is as shown in FIG. 11 (C). That is, in the phase comparator 2, the phase comparison pulse is “H”.
At the time of, the DFF signal is multiplied by the phase comparison pulse, and when the phase comparison pulse is "L", the output of the phase comparator 2 becomes open.

The output from the phase comparator 2 is applied to the low pass filter 4, and the low pass filter 4 is
The error signal shown in FIG. 11 (D) is output.

The error signal is a voltage controlled oscillator (hereinafter referred to as VCO)
5, the VCO 5 oscillates at a frequency corresponding to the DC level of the error signal.

The output from the VCO 5 is applied to the n-ary counter 6, and the counter 6 outputs a trigger signal to the pulse generator 3 when n outputs from the VCO 5 arrive.

Therefore, the pulse generator 3 generates the phase comparison pulse shown in FIG. 11 (B) at the generation timing of the trigger signal from the n-ary counter 6 to form the phase locked loop.

The output from the VCO 5 is used as a reference clock for the signal processing circuit 7 that processes an input video signal or audio signal, and the video or audio signal digitally processed by the signal processing circuit 7 is output to the head 8. It

The above has described the state where the PLL is locked in the center of the lock range. However, for example, when the oscillation frequency of VCO5 decreases, the phase of the phase comparison pulse is delayed as shown in FIG. 11 (E). Like As a result, the error signal output from the low-pass filter 4 becomes as shown in FIG. 11 (F), and the DC level of the error signal gradually increases. As a result, the oscillation frequency of the VCO 5 rises, acts to advance the generation timing of the phase comparison pulse in the pulse generator 3, and approaches the state of being locked in the center of the lock range of the PLL.

On the contrary, if the oscillation frequency of VCO5 drops,
The phase of the phase comparison pulse advances as shown in FIG. As a result, the error signal output from the low-pass filter 4 becomes as shown in FIG. 10 (H), and the DC level of the error signal gradually decreases. As a result, the oscillation frequency of the VCO 5 also decreases, the generation timing of the phase comparison pulse in the pulse generator 3 is delayed, and the state approaches the state of being locked in the center of the PLL lock range.

By the way, where the position of the phase comparison pulse from the pulse generator 3 comes to the DFF signal at the time of starting the operation of the PLL when the power is turned on or the like, it is decided by chance. When this phase comparison pulse comes near the falling edge of the DFF signal, VC
The oscillation frequency of O5 changes, and the position of the phase comparison pulse moves gradually.

In the case of NTSC system, the DFF signal is about 30 Hz and one cycle is about 33.
The lock-in time is inevitably long because it is 33 mSec, the variation range of the oscillation frequency of the VCO 5 is limited, and the low-pass filter 5 also has a time constant.

To shorten this, the width of the phase comparison pulse may be increased.

For example, if the pulse width for phase comparison is widened as shown in FIG. 11 (I), the lock-in time that can enter the lock range is reduced, but the output of the low-pass filter 4 is shown in FIG. 11 (J). As shown, it has a large ripple component R.

Since the oscillation frequency of VCO5 is relatively higher than that of the DFF signal which is the input signal, jitter is added to the oscillation frequencies of the ripple component R and VCO5, and the clock supplied to the signal processing circuit 7 is modulated. Therefore, the result is that the signal processing operation in the signal processing circuit is adversely affected.

[Problems to be Solved by the Invention]

According to the conventional PLL circuit described above, the width of the phase comparison pulse has to be as narrow as possible in order to prevent the clock given to the signal processing circuit from being adversely affected by jitter and the like.

However, if the width of the phase comparison pulse is narrowed, the PLL
There will be conflicting problems that the lock-in time will become longer and longer.

The present invention was made in order to eliminate the contradictory problems of the above-mentioned conventional ones, and the lock-in time of the PLL is short, and unnecessary modulation is applied to the clock given to the signal processing circuit. It is intended to provide a non-PLL circuit.

[Means for Solving the Problems]

A first PLL circuit of the present invention made to achieve the object detects a phase difference between an input signal and a phase comparison pulse obtained from a pulse generator, and generates an output signal according to the phase difference. The phase comparator and the VCO that produces the oscillation output based on the output signal according to the phase difference obtained from the phase comparator, and V
An n-ary counter that divides an oscillation output obtained from CO by n, supplies the divided output to a pulse generator, and generates at least two first and second outputs having different generation timings, and a first output The position detector that sets the start of counting of the n-ary counter based on the change in the phase of the input signal at the generation timing of the second output and the phase of the input signal at the generation timing of the second output.

The second PLL circuit of the present invention detects the phase difference between the input signal and the phase comparison pulse obtained from the pulse generator,
A phase comparator that generates an output signal according to the phase difference, a VCO that provides an oscillation output based on the output signal according to the phase difference obtained from the phase comparator, and the oscillation output obtained from the VCO are divided by n. At least two n-ary counters that generate first and second outputs having different generation timings, and a phase comparison pulse output from the pulse generator according to the phase difference between the first and second outputs and the input signal. And a pulse width adjusting circuit for changing the pulse width.

[Action]

In the PLL circuit according to the first aspect, at least two first and second outputs having different generation timings are generated by the n-ary counter, and the phase state of the input signal is detected at different timings. Then, the trigger signal is sent from the n-ary counter to the pulse generator so as to match the timing when the phase of the input signal rises, so that the PLL circuit is locked in very quickly.

Further, in the PLL circuit according to claim 2, at least two generation timings different from those of the n-ary counter are used.
And the second output is generated, and the pulse width of the pulse signal output from the pulse generator is changed so as to cover the timing at which the phase of the input signal rises. Therefore, the lock-in of the PLL circuit can be achieved very quickly as well.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of the first embodiment of the present invention. Note that the same reference numerals as those in FIG. 10 shown in FIG. 1 denote the same parts, and therefore the description thereof will be omitted.

The n-ary counter 6 in this embodiment repeatedly counts the output from the VCO 5 from 0 to n, and further generates an output at two time points of a count value of 0 and a count value of 1/4 · n. It has a function. The first output generated when the count value is 0 is applied to the first DFF state detector 9. The second output generated when the count value is 1/4 · n is applied to the second DFF state detector 10.

The DFF signal is applied to the first and second DFF state detectors 9 and 10, respectively, and the DF in the state where the count value is 0 is displayed.
The state of the F signal (“H” or “L”) is detected by the first DFF state detector 9, and the state of the DFF signal (“H” or “L”) in the state where the count value is 1/4 · n Are detected by the second DFF state detector 10.

Therefore, the combination of the state detections obtained by the first and second DFF state detectors 9 and 10 is (“L” “H”) ... 1st state (“L” “L”) ... 2nd state (“H "" L ") ... 3rd state (" H "" H ") ... 4th state.

This detection output is applied to the DFF position detector 11, the phase state of the DFF signal is identified, and the output based on the identification result is input to the counter set terminal of the n-ary counter 6.

Then, in the n-ary counter 6, the count value is set to any of 0, 1/4 · n, 2/4 · n · 3/4 · n depending on the first to fourth states.

FIG. 2 is a timing chart showing the operation.
In addition, in this FIG. 2, (A)-(C), (D)-
The operation timing of each of the four blocks (F), (G) to (I), and (J) to (L) is shown.
The upper stage in each block shows the operation of the n-ary counter 6, the middle stage shows the output timing of the DFF signal, and the lower stage shows the generation timing of the phase comparison pulse from the pulse generator 3.

First, in FIGS. 2A to 2C, the n-ary counter 6
When the first signal outputted by the second signal is represented by the second signal, the timings of and of the DFF signal at the time when the operation is started are "L" and "H", that is, the first state. In this state, the phase difference between the rising edge of the DFF signal and the phase comparison pulse output from the pulse generator 3 when the count value of the n-ary counter 6 reaches a predetermined value is within the range of 0 ° and 90 °. Yes, after that, it is locked so that the rising edge of the DFF signal and the position of the phase comparison pulse are the same, and thereafter, phase comparison is performed in this state.

Next, in FIGS. 2D to 2E, the timings of and of the DFF signal are "L" and "L", that is, the second state. In this state, the rising edge of the DFF signal is 1/4 that of the counter
・ Because it is between n and 2/4 ・ n, 1/4 ・ n of the counter is set to 0.
By setting to, the phase difference between the rising edge of the DFF signal and the phase comparison pulse is within 90 °.

The DFF signal becomes "L" and "H" at the new 0, 1/4, and n, and after that, the operation is the same as that of the first state, and locks.

Further, in FIGS. 2G to 2I, the timings at and of the DFF signal are "H" and "L", that is, the third state. In this state, the rising edge of the DFF signal is 2/4 that of the counter
・ Because it is between n and 3/4 ・ n, 1/4 ・ n of the counter is 3 /
By setting to 4 · n, the phase difference between the rising edge of the DFF signal and the phase comparison pulse is within 90 °.

The DFF signal becomes "L" and "H" at the new 0, 1/4, and n, and after that, the operation is the same as that of the first state and locks.

Finally, in FIGS. 2 (J) to (L), the timings at and of the DFF signal are "H", "H", that is, the fourth state. In this state, the rising edge of DFF signal is 3/4
・ Because it is between n and 0, 1/4 ・ n of the counter becomes 2/4 ・ n
By setting to the rising edge of the DFF signal,
The phase difference of the phase comparison pulse is within 90 °.

The DFF signal becomes "L" and "H" at the new 0, 1/4, and n, and after that, the operation is the same as that of the first state, and locks.

As described above, according to the above-described embodiment, the phase comparison pulse and the rising position of the DFF signal always have a phase difference of 90 ° or less after one cycle of the DFF signal. If the maximum time for moving is 1/4 and the width of the phase comparison pulse is the same, the lock-in time of the PLL is also 1/4.

FIG. 3 is a block diagram showing a second embodiment of the present invention. Note that the same reference numerals as those in FIG. 1 shown in FIG. 3 denote the same parts, and therefore the description thereof will be omitted.

The n-ary counter 6 in this embodiment repeatedly counts the output from the VCO 5 from 0 to n, and further has two time points with a count value of 0 and a count value of (l / m) n (where l < It differs from the embodiment shown in FIG. 1 only in that it has a function of generating an output in m).

The first output generated when the count value is 0 is applied to the first DFF state detector 9, and the second output generated when the count value is (l / m) n is the second output.
Is applied to the DFF state detector 10 of.

FIG. 4 is a timing chart showing the operation.
(A) shows the operation of the n-ary counter 6, (B) shows the output timing of the DFF signal, and (C) shows the generation timing of the phase comparison pulse from the pulse generator 3.

As described above, the state of the operation start point of the n-ary counter 6 and the position of the DFF signal at that time are decided by chance.

In the state of FIG. 4, the state of the n-ary counter 6 is 0 and the state of the DFF signal at the time of (l / m) n is (“H” “H”).
When in any of the three states of "(H""L")("L""L"), the n-ary counter is set to 0 (counter is reset).

That is, in the state of (“L” “H”), the rising edge of the DFF signal and the position of the phase comparison pulse are (l /
Since it is in the range of m) n, the n-ary counter 6 is not reset but is counted up to n as it is, and thereafter this is repeated.

In this embodiment, since the position of the DFF signal is detected during the period of 1 / m of one cycle of the DFF signal, assuming that the pulse width for phase comparison is the same as the conventional one, the PLL lock-in is performed. Time can be shortened to l / m.

FIG. 5 is a block diagram showing a third embodiment of the present invention. Note that the same reference numerals as those in FIG. 1 shown in FIG. 5 denote the same parts, and therefore the description thereof will be omitted.

In the embodiment shown in FIG. 5, the n-ary counter 6 produces first and second outputs having a specific relationship with each other.

In FIG. 6, the first output is shown as (B) and the second output is shown as (C). Where (A)
Is the DFF signal, and the "H" time at the first output is D
It is set shorter than the "H" time of the FF signal. The second
The output of is delayed with respect to the first output for a time corresponding to the width of the conventional phase comparison pulse, that is, the pulse width shown in FIG. 10 (B). Then, the first and second outputs are made "L" at the same timing.

Returning to FIG. 5, the first output is applied to one input terminal of the OR circuit 12. The second output is applied to one input terminal of the AND circuit 13.

The DFF signal is applied to the other input terminals of the OR circuit 12 and the AND circuit 13, respectively.

The output of the OR circuit 12 is the first D-type flip-flop.
The clock input terminal of 14 and the output of the AND circuit 13 are applied to the clock input terminal of the second D-type flip-flop 15.

The signal output from the OR circuit 12 is shown as (E) in FIG. 6, and the signal output from the AND circuit 13 is shown as (F).

The first flip-flop 14 has its D input terminal set to "H", and therefore the signal (E) provided from the OR circuit 12
The Q output is made "H" by the rising edge of.

Next, the signal (E) provided from the AND circuit 13 is applied to the second flip-flop 15. At this time, the D input terminal of the second flip-flop 15 is set to "H",
The Q output of the first flip-flop 14 becomes "L" because the Q output thereof becomes "H" due to the rising of the signal (F) and this "H" output is applied to the R terminal of the first flip-flop 14. Becomes

As a result, the phase comparison pulse shown in FIG. 6D is applied to the phase comparator 2.

The operation shown in FIG. 6 shows the state where the PLL is phase locked.

Next, FIG. 7 shows the case where the phase of the output of VCO5 is advanced. In FIG. 7, (A) to (F) are the same as those shown in FIG.

In the case of FIG. 7, the Q output of the flip-flop 14 is made "H" at the rise of the signal (E) obtained from the OR circuit 12. Then, the Q output of the flip-flop 15 becomes "H" due to the rise of the signal (F) obtained from the AND circuit 13, and the "H" output resets the flip-flop 14, so that the Q output of the flip-flop 14 becomes "L". Made in.

Therefore, as shown in FIG.
A wide phase comparison pulse (D) including the rising edge of the F signal (A) at the trailing edge is generated. Therefore, the PLL is locked in immediately.

When the PLL locks in in this way, the 6th error occurs due to the DC error signal output from the low-pass filter 4.
The width of the phase comparison pulse (D) is reduced by converging on the phase relationship of the state shown in the figure.

Further, FIG. 8 shows the case where the phase of the output of VCO5 is delayed. In FIG. 8, (A) to (F) are the same as those shown in FIG.

In the case of FIG. 8, the Q output of the flip-flop 14 is made "H" at the rising edge of the signal (E) obtained from the OR circuit 12. When the signal (F) obtained from the AND circuit 13 rises, the Q output of the flip-flop 15 becomes "H", and the "H" output resets the flip-flop 14. Therefore, the Q output of the flip-flop 14 becomes "L".

Therefore, in the phase comparator 2, as shown in FIG.
A wide phase comparison pulse (D) having a leading edge including the rising edge of the DFF signal (A) is generated, and the PLL is locked in by this pulse (D).

Note that, when the PLL locks in, the phase relationship shown in FIG. 6 is converged, which is the same as in the case of FIG.

According to the third embodiment of the present invention as described above, the width of the phase comparison pulse is continuously expanded to include the rising portion of the DFF signal in the phase lock operation.
PLL is locked in in a short time.

Further, when the PLL is locked in, the width of the phase comparison pulse is narrowed, so that the disadvantage that the VCO oscillation frequency is modulated does not occur. This third embodiment is based on the first
Alternatively, it can be combined with the second embodiment, and the lock-in time can be further shortened.

FIG. 9 shows a configuration of a fourth embodiment which is a combination of the first embodiment and the third embodiment.

In this embodiment, as in the case of the first embodiment,
The level of the DFF signal when the count value of the n-ary counter 6 is 0 or 1/4 · n is detected, and the n-ary counter 6 is reset according to the state.

Further, as in the case of the third embodiment, the phase comparison pulse adjusted to have a predetermined width is phase-compared from the two signals output from the n-ary counter 6 having a predetermined phase relationship and the DFF signal. Is supplied to the container 2.

According to the fourth embodiment, for example, a phase comparator that detects the phase difference between the input signal and the phase comparison pulse obtained from the pulse generator, and generates an output signal according to the phase difference,
A VCO that provides an oscillation output based on an output signal corresponding to the phase difference obtained from the phase comparator, and the oscillation output obtained from the VCO is divided by n, and at least two first and second outputs with different generation timings. And an n-ary counter that generates at least two third and fourth outputs having different generation timings, and an n-ary counter corresponding to the change in the phase of the input signal at the generation timings of the first and second outputs. Position detector for controlling the counting operation of the
It is possible to configure a PLL circuit that includes a pulse width adjustment circuit that changes the pulse width of the phase comparison pulse output from the pulse generator according to the phase difference between the output of the pulse generator and the input signal.

〔The invention's effect〕

As is clear from the above description, according to the PLL circuit of claim 1, in the initial state such as when the power is turned on, when the signal input is started, or when the drum rotation is started, the phase of the DFF signal rises according to the timing. Since the counter is set so that the trigger signal is sent from the n-ary counter to the pulse generator, the PLL is locked in very quickly.

Moreover, unlike the conventional case, it is not necessary to widen the width of the phase comparison pulse. Therefore, even when the VCO oscillation frequency is high with respect to the input signal, it is possible to prevent the inconvenience of giving harmful modulation to the clock. .

Further, according to the PLL circuit of claim 2, the pulse width of the pulse signal output from the pulse generator is changed so as to cover the timing when the phase of the DFF signal rises. Therefore, in the case of claim 1, Similarly, the lock-in time of the PLL can be shortened.

Also, when the PLL locks, the pulse width for phase comparison is controlled to be automatically narrowed, so even if the VCO oscillation frequency is high with respect to the input signal, there is no harmful modulation to the clock. It is also possible to prevent the inconvenience of giving.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a PLL circuit of the present invention, FIG. 2 is a timing chart diagram for explaining the operation of the PLL circuit of FIG. 1, and FIG. 3 is a PLL circuit of the present invention. FIG. 4 is a block diagram showing a second embodiment, FIG. 4 is a timing chart diagram for explaining the operation of FIG. 3, and FIG. 5 is a block diagram showing a third embodiment of the PLL circuit of the present invention. 6 to 8 are timing charts for explaining the operation of the one shown in FIG. 5, FIG. 9 is a block diagram showing the configuration of the fourth embodiment of the PLL circuit of the present invention, and FIG. FIG. 11 is a block diagram showing a conventional example, and FIG. 11 is a timing chart for explaining the operation of the conventional one. 1 ... Input terminal, 2 ... Phase comparator, 3 ... Pulse generator, 4 ... Low-pass filter, 5 ... VCO, 6 ... n
Progressive counter, 7 ... Signal processing circuit, 8 ... Head, 9,
10 …… DFF status detector, 11 …… DFF position detector.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 9182-5J H03L 7/08 C

Claims (2)

[Claims] 1. A phase comparator for detecting a phase difference between an input signal and a phase comparison pulse obtained from a pulse generator and generating an output signal according to the phase difference, and a position obtained by the phase comparator. A VCO that produces an oscillation output based on an output signal according to a phase difference, an oscillation output obtained from the VCO is divided by n, and the divided output is supplied to the pulse generator, and at least two generation timings differ from each other. An n-ary counter for generating the first and second outputs, the phase of the input signal at the generation timing of the first output, and the n based on the change of the phase of the input signal at the generation timing of the second output. A position detector for setting the start of counting of a binary counter
circuit. 2. A phase comparator that detects a phase difference between an input signal and a phase comparison pulse obtained from a pulse generator and generates an output signal according to the phase difference, and a position obtained by the phase comparator. A VCO that provides an oscillation output based on an output signal according to the phase difference, and an n-ary counter that divides the oscillation output obtained from the VCO by n to generate at least two first and second outputs with different generation timings. And a pulse width adjusting circuit for changing the pulse width of the phase comparison pulse output from the pulse generator according to the phase difference between the first and second outputs and the input signal. circuit.