KR100196834B1 - Apparatus for distinguishing the video signal in pdp in tv - Google Patents
Apparatus for distinguishing the video signal in pdp in tv Download PDFInfo
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- KR100196834B1 KR100196834B1 KR1019950055670A KR19950055670A KR100196834B1 KR 100196834 B1 KR100196834 B1 KR 100196834B1 KR 1019950055670 A KR1019950055670 A KR 1019950055670A KR 19950055670 A KR19950055670 A KR 19950055670A KR 100196834 B1 KR100196834 B1 KR 100196834B1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/38—Starting, stopping or resetting the counter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
본 발명은 피디피 티브이(PDP TV)의 영상신호 판별장치에 관한 것으로, 외부로부터의 선택신호에 의거하여 선택된 채널의 영상신호가 유신호인 경우, PLL로부터 동기분리부에서 분리된 수평동기신호(Hs)에 동기되는 클럭이 카운터로 제공되고, 외부로부터 제공되는 기준클럭 내에서 설정된 소정갯수(예를 들면, 1024개)가 카운터를 통해 계수되어, 기준클럭 내에서 설정된 소정갯수가 계수되면 D플립플롭으로부터 하이레벨신호, 즉 선택된 채널의 영상신호가 유신호라는 판별신호가 발생되며, 기준클럭 내에서 설정된 소정갯수가 계수되지 않으면 D플립플롭으로부터 로우레벨신호, 즉 선택된 채널의 영상신호가 무신호라는 판별신호가 각각 발생되므로써, 선택된 채널의 유무판별신호에 의거하여 신호처리과정을 다르게 지정할 수 있으므로, 선택된 채널이 무신호인 경우에 발생되는 PDP TV의 오동작을 사전에 방지할 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal discrimination apparatus of a PDP TV. When the video signal of a channel selected on the basis of an external selection signal is an oil signal, a horizontal synchronous signal (Hs) separated from the PLL by a synchronization separator. A clock synchronized to the clock is provided to the counter, and a predetermined number (for example, 1024) set in the reference clock provided from the outside is counted through the counter, and when the predetermined number set in the reference clock is counted, the D flip-flop is counted. A discrimination signal is generated that the high level signal, that is, the video signal of the selected channel is a valid signal, and if the predetermined number set in the reference clock is not counted, a low level signal from the D flip-flop, that is, the discrimination signal that the video signal of the selected channel is no signal. Are generated separately, so that the signal processing process can be specified differently based on the presence or absence discrimination signal of the selected channel. This is to prevent the malfunction of the PDP TV generated in the case of no signal.
Description
제1도는 본 발명의 바람직한 실시예에 따른 피디피 티브이(PDP TV)의 영상신호 판별장치의 개략적인 블록구성도.1 is a schematic block diagram of an apparatus for determining a video signal of a PDP TV according to a preferred embodiment of the present invention.
제2도는 본 발명에 따른 판별결과로서, 영상신호가 유신호인 경우를 설명하기 위한 도면.2 is a diagram for explaining a case where a video signal is a flow signal as a result of discrimination according to the present invention.
제3도는 본 발명에 따른 판별결과로서, 영상신호가 무신호인 경우를 설명하기 위한 도면.3 is a view for explaining a case where a video signal is no signal as a result of discrimination according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
110 : 동기분리부 120 : PLL110: sync separation unit 120: PLL
130 : 카운터 140 : D플립플롭130: counter 140: D flip-flop
본 발명은 PDP TV(PLASMA DISPLAY PANEL TELEVISION: 이하 PDP TV라고 약칭함)에 관한 것으로, 보다 상세하게는 외부로부터의 선택신호에 의거하여 선택된 채널에 대한 영상신호의 존재유무를 판별하여 그에 따른 판별신호를 출력할 수 있도록 한 피디피 티브이(PDP TV)의 영상신호 판별장치에 관한 것이다.The present invention relates to a PDP TV (abbreviated as PDPMA TELEVISION), and more particularly, to determine the presence or absence of a video signal for a channel selected on the basis of a selection signal from an external source. The present invention relates to a video signal discrimination apparatus of a PDP TV.
최근에, 표시면적이 크고 용적이 작은, 이른바 평면형 표시장치에 관한 많은 연구가 그와 관련된 여러 분야에서 지속적으로 연구되고 있다.In recent years, many studies on so-called flat display devices having large display areas and small volumes have been continuously conducted in various fields related thereto.
상기한 평면형 표시장치에는 일렉트로 루미네센스(ELECTRO LUMINESCENCE), 발광 다이오드(LIGHT EMITTING DIODE), PDP 등의 능동소자와 액정표시장치(LIQUID CRYSTAL DISPLAY) 일렉트로 크로믹 표시장치(ELECTRO CHROMIC DISPLAY)등의 수동소자가 있으며, 본 발명은 실질적으로 능동소자 중의 하나인 PDP에 관련된다.The flat display device includes an active element such as ELECTRO LUMINESCENCE, a light emitting diode, and a PDP, and a passive device such as an LIQUID CRYSTAL DISPLAY and an ELECTRO CHROMIC DISPLAY. There is a device, and the present invention relates to a PDP that is substantially one of the active devices.
한편, PDP TV는 방송국으로부터 전송되는 영상신호를 설정된 소정갯수(예를 들면, 480 라인)의 수평라인 영상신호를 선택한 다음, 수평라인 영상신호 중에서도 버스트신호와 휘도신호를 제외한 실질적인 영상신호가 존재하는 구간만을 샘플링하여 PDP TV의 화면으로 디스플레이한다.On the other hand, the PDP TV selects a predetermined number of horizontal line video signals (e.g., 480 lines) from which a video signal transmitted from a broadcasting station is set, and then, among the horizontal line video signals, substantial video signals other than burst signals and luminance signals exist. Only the section is sampled and displayed on the screen of the PDP TV.
이때, 영상신호를 샘플링하는데 있어서, 기준이 되는 신호는 수평동기신호와 수직동기신호이다.At this time, in sampling the video signal, a reference signal is a horizontal synchronization signal and a vertical synchronization signal.
그러나, 외부로부터의 선택신호에 의거하여 선택된 채널의 영상신호가 유신호이면 수평동기신호와 수직동기신호가 존재하지만, 선택된 채널의 영상신호가 무신호, 즉 노이즈인 경우 수평동기신호와 수직동기신호가 존재하지 않기 때문에, 신호처리과정에서 PDP TV의 오동작을 발생시킬 수 있는 문제점이 있다.However, if the video signal of the channel selected based on the selection signal from the outside is a valid signal, there is a horizontal sync signal and a vertical sync signal. However, if the video signal of the selected channel is no signal, that is, a noise, the horizontal sync signal and the vertical sync signal are Since it does not exist, there is a problem that may cause a malfunction of the PDP TV in the signal processing.
따라서, 본 발명은 상기한 바와 같은 문제점을 감안하여 안출한 것으로, 외부로부터의 선택신호에 의거하여 선택된 채널에 대해 영상신호의 유무판별신호를 발생하는 피디피 티브이(PDP TV)의 영상신호 판별장치를 제공하는데 그 목적이 있다.Accordingly, the present invention has been made in view of the above-described problems, and an apparatus for discriminating a video signal of a PDP TV which generates a discrimination signal with or without a video signal on a channel selected based on a selection signal from the outside is provided. The purpose is to provide.
상기 목적을 달성하기 위하여 본 발명은, 외부로부터의 선택신호에 의거하여 선택된 채널의 영상신호를 판별하는 피디피 티브이(PDP TV)장치에 있어서, 상기 영상신호 중에 포함되어 있는 수평동기신호를 분리하기 위한 동기분리수단과, 상기 동기분리수단에서 분리된 수평동기신호에 동기되는 클럭을 발생하는 PLL과, 외부로부터 제공되는 기준클럭 내에서상기 PLL을 통해 동기되어 발생되는 클럭갯수를 계수하여 그에 따른 카운트신호를 발생하는 카운터와, 외부로부터의 뮤트신호에 의거하여 리셋되며, 상기 카운터로부터의 카운트신호에 의거하여 그에 상응하는 상기 선택된 채널에 대한 영상신호의 유무판별신호를 출력하는 D플립플롭으로 구성된 것을 특징으로 하는 피디피 티브이(PEP TV)의 영상신호 판별장치를 제공한다.In order to achieve the above object, the present invention, in the PDP TV device for determining the video signal of the selected channel based on the selection signal from the outside, for separating the horizontal synchronization signal included in the video signal A counting signal according to the synchronous separation means, a PLL generating a clock synchronized with the horizontal synchronous signal separated by the synchronous separation means, and the number of clocks generated synchronously through the PLL in a reference clock provided from the outside. And a D flip-flop which is reset based on a mute signal from the outside, and outputs a presence / absence determination signal of a video signal corresponding to the selected channel based on the count signal from the counter. Provided is a video signal discrimination apparatus for a PDP TV.
본 발명의 상기 및 기타 목적과 여러 가지 장점은 이 기술분야의 숙련된 사람들에 의해 첨부된 도면을 참조하여 하기에 기술되는 본 발명의 바람직한 실시예로부터 더욱 명확하게 될 것이다.The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대하여 상세하게 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제1도는 본 발명의 바람직한 실시예에 따른 피디피 티브이(PDP TV)의 영상신호 판별장치의 개략적인 블록구성도로서, 동기분리부(110), PLL (PHASE LOCKED LOOP : 이하 PLL 이라 약칭함, 120), 카운터(130) 및 D플립플롭(140)로 구성된다.FIG. 1 is a schematic block diagram of an apparatus for discriminating a video signal of a PDP TV according to a preferred embodiment of the present invention. ), A counter 130 and a D flip-flop 140.
제1도에 있어서, 동기 분리부(110)는 외부로부터의 선택신호에 의거하여 선택된 채널의 복합영상신호 중에 포함되어 있는 수평동기신호(Hs)를 분리하여 PLL(120)로 제공하고, PLL(120)은 동기분리부(110)에서 분리된 수평동기신호(Hs)에 위상이 동기되는 설정된 소정주파수를 갖는 클럭을 출력한다.In FIG. 1, the sync separating unit 110 separates the horizontal sync signal Hs included in the composite video signal of the selected channel based on the selection signal from the outside and provides the PLL 120 to the PLL 120. 120 outputs a clock having a predetermined frequency at which the phase is synchronized with the horizontal synchronization signal Hs separated by the synchronization separator 110.
그리고, 카운터(130)는 외부로부터 제공되는 기준클럭의 라이징에지(RISING EDGE) 또는 폴링에지(FALLING EDGE)에서 리셋되며, 라이징에지 또는 폴링에지부터 PLL(120)에서 제공되는 클럭의 갯수를 계수하여 설정된 소정갯수 이후부터 기준클럭의 폴링에지 또는 라이징에지까지 하이레벨신호를 발생한다.The counter 130 is reset at a rising edge or falling edge of a reference clock provided from the outside, and counts the number of clocks provided from the rising edge or falling edge to the PLL 120. The high level signal is generated from the set number of times up to the falling edge or rising edge of the reference clock.
또한, D플립플롭(140)은 카운터(130)로부터의 출력신호가 하이레벨신호의 라이징에지부터 하이레벨신호를 계속적으로 발생하는데, D플립플롭(140)으로부터 발생되는 신호가 하이레벨신호이면 선택된 채널의 영상신호가 유신호이고, D플립플롭(140)으로부터 발생되는 신호가 로우레벨신호이면 선택된 채널의 영상신호가 무신호이다.In addition, the D flip-flop 140 continuously generates a high level signal from the rising edge of the high level signal, and the output signal from the counter 130 is selected if the signal generated from the D flip flop 140 is a high level signal. If the video signal of the channel is a valid signal and the signal generated from the D flip-flop 140 is a low level signal, the video signal of the selected channel is no signal.
이때, D플립플롭(140)은 외부로부터의 뮤트신호, 즉 채널변환신호에 의거하여 리셋된다.At this time, the D flip-flop 140 is reset based on the mute signal from the outside, that is, the channel conversion signal.
상기한 바와 같은 구성부재로 이루어진 본 발명의 피디피 티브이(PDP TV)의 영상신호 판별장치의 동작과정에 대하여 제1도와 제2도 및 제3도를 참조하여 보다 상세하게 설명하기로 한다.An operation process of the apparatus for discriminating a video signal of a PDP TV of the present invention comprising the above-described constituent members will be described in more detail with reference to FIGS. 1, 2, and 3.
먼저, 외부로부터 소정주파수, 예를 들면 23kHz를 갖는 기준출력이 카운터(130)로 제공되는 것으로 가정하면, 이러한 기준클럭의 주기는 43.48㎲이므로, 기준클럭이 하이레벨 또는 로우레벨인 구간은 제2(a)도에 도시된 바와 같이, 각각 21.74㎲가 된다.First, assuming that a reference output having a predetermined frequency, for example, 23 kHz, from the outside is provided to the counter 130, the period of the reference clock is 43.48 ms, so that the section in which the reference clock is high or low level is second. As shown in (a), each is 21.74 ms.
첫째로, 외부로부터의 선택신호에 의거하여 선택된 채널의 영상신호가 유신호인 경우, 동기분리부(110)에서 분리된 수평동기신호(Hs)가 PLL(120)을 통해 동기되어 카운터(130)로 제공되는 클럭의 주파수는 25.1748MHz이며, 이러한 클럭주파수를 시간적으로 다시 표현하여 하이레벨 구간 동안 카운터(130)를 통해 1024개가 계수되면, 제2(b)도에 도시된 바와 같이, 20.34㎲가 된다.First, when the video signal of the channel selected based on the selection signal from the outside is a flow signal, the horizontal synchronization signal Hs separated by the synchronization separator 110 is synchronized to the counter 130 by the PLL 120. The frequency of the provided clock is 25.1748 MHz. When the clock frequency is re-expressed in time and 1024 counted through the counter 130 during the high level period, as shown in FIG. 2 (b), the frequency is 20.34 kHz. .
따라서, 카운터(130)로부터 20.34 ㎲이후부터 기준클럭의 폴링에지까지의 1.4㎲동안 하이레벨신호가 발생되고, 카운터(130)로부터 발생되는 하이레벨신호의 라이징에지에서 D플립플롭(140)으로부터 하이레벨신호가 발생되어 도시생략된 수평포지션 또는 수직포지션 설정수단으로 선택된 채널의 영상신호가 유신호라는 판별신호가 제공된다(제2(c)도).Accordingly, a high level signal is generated during the 1.4 s from the counter 130 to the falling edge of the reference clock, and from the D flip-flop 140 at the rising edge of the high level signal generated from the counter 130. A discrimination signal is provided in which the level signal is generated and the video signal of the channel selected by the horizontal position or vertical position setting means, not shown, is a valid signal (Fig. 2 (c)).
둘째로, 외부로부터의 선택신호에 의거하여 선택된 채널의 영상신호가 무신호인 경우, 동기분리부(110)로부터 수평동기신호(Hs)가 PLL(120)로 제공되지 않으므로, 카운터(130)로부터 로우레벨신호가 계속적으로 발생된다(제3(b)도).Second, when the video signal of the channel selected based on the selection signal from the outside is no signal, since the horizontal synchronization signal Hs is not provided from the synchronization separating unit 110 to the PLL 120, it is low from the counter 130. The level signal is continuously generated (figure 3 (b)).
따라서, 카운터(130)로부터의 로우레벨신호에 의거하여 D플립플롭(140)으로부터 로우레벨신호, 즉 선택된 채널의 영상신호가 무신호라는 판별신호가 도시생략된 수평포지션 또는 수직포지션 설정수단으로 제공된다(제3(c)도).Therefore, based on the low level signal from the counter 130, the D flip-flop 140 provides the low level signal, that is, the discrimination signal indicating that the video signal of the selected channel is no signal, to the horizontal position or vertical position setting means, not shown. (Figure 3 (c)).
다음에, D플립플롭(140)으로부터의 판별신호에 의거하여 선택된 채널의 영상신호가 유신호인 경우, 영상신호 중에 포함되어 있는 수평 및 수직 동기신호에 의거하여 영상신호가 샘플링되고, 선택된 채널의 영상신호가 무신호인 경우, 도시 생략된 제너레이터(GENERATOR)로부터 발생되는 펄스에 의거하여 영상신호가 샘플링된다.Next, when the video signal of the channel selected based on the discrimination signal from the D flip-flop 140 is a valid signal, the video signal is sampled based on the horizontal and vertical synchronization signals included in the video signal, and the video of the selected channel is obtained. When the signal is no signal, the video signal is sampled based on a pulse generated from a generator (not shown).
상술한 바와 같이, 외부로부터의 선택신호에 의거하여 선택된 채널의 영상신호가 유신호인 경우, PLL(120)로부터 동기분리부(110)에서 분리된 수평동기신호(Hs)에 동기되는 클럭이 카운터(130)로 제공되고, 외부로부터 제공되는 기준클럭 내에서 설정된 소정갯수(예를 들면, 1024개)가 카운터(130)를 통해 계수되어, 기준클럭 내에서 설정된 소정갯수가 계수되면 D플립플롭(140)으로부터 하이레벨신호, 즉 선택된 채널의 영상신호가 유신호라는 판별신호가 발생되며, 기준클럭 내에서 설정된 소정갯수가 계수되지 않으면 D플립플롭(140)으로부터 로우레벨신호, 즉 선택된 채널의 영상신호가 무신호라는 판별신호가 각각 발생된다.As described above, when the video signal of the channel selected based on the selection signal from the outside is a flow signal, the clock synchronized with the horizontal synchronization signal Hs separated from the PLL 120 by the synchronization separating unit 110 is counted. 130, and a predetermined number (for example, 1024) set in the reference clock provided from the outside is counted through the counter 130, and when the predetermined number set in the reference clock is counted, the D flip-flop 140 A high level signal, i.e., a determination signal indicating that the video signal of the selected channel is a valid signal, is generated.If the predetermined number set within the reference clock is not counted, the low level signal, i.e., the video signal of the selected channel, is generated from the D flip-flop 140. A discrimination signal is generated that is no signal.
따라서, 본 발명을 이용하면, 선택된 채널의 유무판별신호에 의거하여 신호처리과정을 다르게 지정할 수 있으므로, 선택된 채널이 무신호인 경우에 발생되는 PDP TV 의 오동작을 사전에 방지할 수 있는 효과가 있다.Therefore, according to the present invention, since the signal processing process can be specified differently based on the presence / absence determination signal of the selected channel, there is an effect that the malfunction of the PDP TV generated when the selected channel is no signal can be prevented in advance.
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| KR1019950055670A KR100196834B1 (en) | 1995-12-23 | 1995-12-23 | Apparatus for distinguishing the video signal in pdp in tv |
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| KR1019950055670A KR100196834B1 (en) | 1995-12-23 | 1995-12-23 | Apparatus for distinguishing the video signal in pdp in tv |
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