KR100197380B1 - Apparatus for directing the generation of data as channel transfer in pdp tv - Google Patents

Abstract

The present invention relates to an apparatus for indicating data generation during channel switching in a PDP TV, wherein a channel is switched from a current signal to a next signal from a current signal, and a current channel is from a no signal to a next signal. When the channel is switched, the horizontal synchronizing signal and the vertical synchronizing signal are separated from the composite video signal of the next channel by the synchronizing separator, and the horizontal synchronizing signal of the next channel generated from the PLL based on the discriminating signal from the presence / absence signal discrimination unit The synchronized clock is input to the AND gate one-side input terminal, and the horizontal synchronizing signal and the vertical synchronizing signal separated by the synchronizing separator are provided to the frame generator based on the discrimination signal from the presence / absence signal discriminator, and then the frame discrimination signal from the frame generator. Is generated. At this time, the number of complete frames is counted in the counter after the channel switching time, and a high level pulse is generated after the predetermined number of frames, input to the other input terminal of the AND gate, and then logically multiplied through the AND gate. The generation instruction pulse is provided to the A / D converter, and the analog RGB signal is converted to the digital RGB signal by the A / D converter and processed according to the data generation instruction pulse provided from the AND gate, and then displayed on the PDP TV screen. Therefore, since the analog RGB signal is not converted into the digital RGB signal by the A / D converter until the clock generated from the PLL is stabilized during channel switching, it is possible to prevent an unstable image from being displayed on the PDP TV screen. will be.

Description

Data generation indicating device during channel switching in PDTV

1 is a schematic block diagram of an apparatus for indicating data generation when switching channels in a PDP TV according to a preferred embodiment of the present invention.

2 is a diagram showing each pulse waveform generated in each block in the data generation indicating device according to the present invention.

* Explanation of symbols for main parts of the drawings

110: sync separation unit 120: presence signal determination unit

130: PLL 140: clock generator

150: synchronization generating unit 160: selection unit

170: frame generator 180: counter

190: D flip-flop 200: AND gate

210: A / D converter

The present invention relates to a PDP TV (PLASMA DISPLAY PANEL TELEVISION, hereinafter abbreviated as TV to P), and more particularly to a PDP TV suitable for generating data after the image signal is stabilized during channel switching. The present invention relates to an apparatus for indicating data generation during channel switching in.

As is well known, flat display devices include active elements such as ELECTROL LUMINESCENCE, LIGHT EMITTING DIODE, and PDP, and LIQUID CRYSTAL DISPLAY, ELECTRO CHROMIC. DISPLAY) and the like, and the present invention is substantially related to PDP which is one of the active devices. On the other hand, in PDP TV, analog video signals transmitted from broadcasting stations are converted into digital video signals using a sampling clock (analog to digital conversion; hereinafter referred to as A / D conversion), and the signals are processed to process the PDP TV screen. Display in phase.

However, when switching the channel, the channel whose sampling clock cycle is switched becomes unstable until it is synchronized with the horizontal synchronizing signal, which causes an error in A / D conversion. There is a problem that an unstable image, for example, a crushed image or a broken image is displayed.

Accordingly, the present invention is to solve the problems of the prior art as described above, it is possible to generate data by A / D conversion from the frame after skipping a predetermined frame for the video signal of the switched channel at the time of channel switching An object of the present invention is to provide an apparatus for indicating data generation during channel switching in a PDP TV.

In order to achieve the above object, the present invention provides a PDP TV device that generates data for a composite video signal at the time of channel switching, and is displayed on the PDP TV screen based on an operation signal from the outside. Synchronization separation means for separating horizontal and vertical synchronization signals from the composite video signal for the switching channel when the current channel is switched to any other channel; Discriminating means for discriminating whether a switching channel is present or not based on a detection result of the horizontal synchronizing signal and the vertical synchronizing signal separated by the synchronizing separating means; A PLL for generating a clock synchronized with the horizontal synchronizing signal separated by the synchronizing separation means; Clock generation means for itself generating a clock synchronized with the clock generated in the PLL; Synchronization generating means for generating the horizontal and vertical synchronizing signals corresponding to the horizontal and vertical synchronizing signals included in the separated composite video signal by itself; On the basis of the discrimination signal from the discriminating means, the synchronizing signal from the synchronizing separation means and the synchronizing signal from the synchronizing generating means are selectively output, and the clock from the PLL and the clock from the clock generating means are selectively selected. Selecting means for outputting; A data generation instruction for generating a data generation instruction clock for delaying the A / D conversion output of the input image data for a predetermined time based on the selected horizontal and vertical synchronizing signal and the clock output from the selection means 160; Way; And an A / D conversion means for converting the analog RGB signal of the switching channel into digital after a predetermined time delay based on the data generation instruction clock provided from the data generation instruction means. Provided is an apparatus for instructing data generation during channel switching in a (PDP TV).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of an apparatus for indicating data generation when switching channels in a PDP TV according to a preferred embodiment of the present invention, and includes a synchronization separator 11, a presence / absence signal discrimination unit 120, and a PLL. (PHASE LOCKED LOOP, 130), clock generator 140, sync generator 150, selector 160, frame generator 170, counter 180, D flip-flop 190, AND gate ( 200 and the A / D converter 210.

In FIG. 1, the sync separator 110 separates the horizontal sync signal Hs and the vertical sync signal Vs included in the composite video signal as shown in FIG. Here, the separated horizontal synchronizing signal (Hs) is provided to the presence signal determination unit 120 and the selection unit 160, respectively, and the vertical synchronizing signal (Vs) is the presence signal determination unit 120, PLL (130) And the selector 160, respectively.

In addition, the presence or absence signal determination unit 120 determines the presence or absence of the composite video signal using the separated horizontal synchronization signal (Hs) and the vertical synchronization signal (Vs) provided from the synchronization separation unit (110), and accordingly the determination signal (Eg, a high or low level discrimination signal) is generated and provided to the selector 160. At this time, the presence / absence signal determination unit 120 is cleared based on the mute signal from the outside, where the mute signal is generated, for example, when switching channels.

Next, the PLL 130 generates a clock signal A_CLK, which is synchronized with the separated horizontal synchronization signal Hs provided from the synchronization separator 110, and provides the generated clock signal to the selection unit 160. ) Generates its own clock B_CLK corresponding to (or synchronizing) the clock A_CLK generated in the PLL 130 described later, that is, its own clock for use when the clock A_CLK is not generated in the PLL 130. (B_CLK) is generated and provided to the selector 160.

In addition, the synchronization generating unit 150 receives the horizontal synchronizing signal B_Hsync and the vertical synchronizing signal B_Vsync corresponding to the horizontal synchronizing signal Hs and the vertical synchronizing signal Vs separated by the sync separating unit 110 described above. Each of the self-generated horizontal synchronization signal B_Hsync and the vertical synchronization signal B_Vsync does not detect the horizontal synchronization signal Hs and the vertical synchronization signal Vs. When used to generate a data generation indication pulse in accordance with the present invention.

On the other hand, the selector 160 selects and outputs either A_CLK or B_CLK based on the high or low level discrimination signal provided from the presence / absence determination unit 120 described above (FIG. 2B). And selects any one of the separated A_Hsync and A_Vsync provided from the synchronization separating unit 110 or the self-generated B_Hsync and B_VSync provided from the synchronization generating unit 150 (FIG. 2 (c) and (d)). )do.

That is, the selector 160 outputs A_CLK to one input terminal of the AND gate 200 when the broadcast signal is a valid signal (for example, when the discrimination signal is high level), and simultaneously outputs A_Hsync and A_VSync to the frame generator. And outputs B_CLK to one input terminal of the AND gate 200 when the broadcast signal is no signal (e.g., when the discrimination signal is low level) and outputs B_Hsync and B_Vsync to the frame generator 170 )

Next, the frame generation unit 170 generates a frame division signal for classifying frames based on the horizontal synchronization signal A_Hsync or B_Hsync and the vertical synchronization signal A_Vsync or B_Vsync provided from the selection unit 160. That is, as an example, a frame classification signal as shown in FIG. 2E is generated and provided to the next counter 180.

In addition, the counter 180 counts the total number of frames based on the frame discrimination signal provided from the frame generator 170, and the number of the counted frames becomes a predetermined number (for example, two, etc.). When a high level signal is generated through its output terminal, it is provided to the D flip-flop 190 of the next stage. Next, when the high level signal is applied from the counter 180, the D flip-flop 190 generates a high level signal (FIG. 2f) through its output terminal Q to generate the AND gate 200. Provided to the other input terminal. At this time, the D flip-flop 190 is cleared based on the mute signal for muting while the composite video signal of the channel switched from the micom (not shown) is stabilized.

On the other hand, the AND gate 200 logically multiplies the CLK signal provided from the selector 160 to the one input terminal and the output signal provided from the D flip-flop 190 to the other input terminal, and as the result of the logical product. The obtained output signal is generated as a data generation instruction pulse (for example, a pulse as shown in FIG. 2 (g)) and provided to the A / D converter 210 of the next stage.

For example, assuming that the counter 180 is set to count two frames, when the channel switching occurs at the time A as shown in FIG. Since the high level signal is generated after counting the frame (a frame, b frame), the output terminal Q of the D flip-flop 190 is shown in FIG. The pulse waveform is output. As a result, at the output terminal of the AND gate 200, a data generation instruction pulse (i.e., a clock signal required for A / D conversion of the R.G.B signal), as shown in Fig. 2G, will be output.

Accordingly, the A / D converter 210 adaptively A / D converts the input analog RGB signal in response to the data generation instruction pulse provided from the AND gate 200 to output a digital RGB signal. For example, an A / D converted digital RGB signal is output when a data generation instruction pulse is provided, and an A / D converted digital RGB signal is not output when a data generation instruction pulse is provided.

Next, an operation process of the data generation instructing device according to the present invention composed of the above-described constituent members will be described in more detail with reference to FIGS.

In general, it is possible to consider four cases that can occur when the current channel being viewed is switched to any other channel, i.e., when there is no signal, no signal, no signal, and no signal, and no signal. Here, the apparatus for generating data according to the present invention relates to a technique for effectively preventing an image from becoming unstable on a screen of a PDP TV, particularly when calling from a signal to a signal and switching from a signal to a signal. .

In other words, when a channel is switched from a flowed signal or a no signal to a flowed signal, an error occurs in the A / D conversion of the RGB signal because the clock generated until the synchronization with the horizontal synchronization signal of the switched channel is not stable. In order to prevent this, the data generation instruction device of the present invention generates a data generation instruction pulse only when switching from a signal to a signal and a signal to a signal, i.e., skipping a predetermined delay time (e.g., skipping about two frames). After generating the signal, the data generation instruction pulse is generated to perform A / D conversion of the video signal.

First, when the current channel is a valid signal and the channel to be switched is a non-signal, a stable clock (generated by the clock generator 140 itself in the clock generator 140 based on the discrimination signal from the presence / absence signal determination unit 120). The B_CLK and the sync generator 150 output vertical and horizontal sync signals B_Hsync and B_Vsync to one input terminal and the frame generator 170 of the AND gate 200, respectively.

Therefore, a high level output signal is output after a predetermined delay time at the output side of the D flip-flop 190 whose output value is determined by the output of the counter 180, as shown in FIG. When the user switches the channel at time A, after skipping the two frames (a and b frames) according to the count result in the counter 180, as shown in FIG. , the output signal of high level at the rising edge of the frame c) is output to the other input terminal of the AND gate 200, and as a result, in the AND gate 200, data as shown in FIG. The generation instruction pulse is output and provided to the A / D converter 210.

As a result, the A / D converter 210 stabilizes the output by suppressing the output for a predetermined delay time (for example, two frame times), and then performs an A / D conversion operation on the input image signal RGB. Done. However, since the selected channel is a no-signal channel, the A / D converter 210 does not actually output digital image data.

Next, in the case where the current channel is no signal and the channel to be switched is no signal, each component performs the same processing as in the case of the presence / no signal described above to generate the same data generation instruction pulse.

Therefore, the A / D converter 210 attempts to stabilize the output by suppressing the output for a predetermined delay time (for example, two frame times), and then performs an A / D conversion operation on the input image signal RGB. do. However, as described above, since the switched-selected channel is a no-signal channel, the A / D converter 210 does not actually output digital image data.

On the other hand, when the current channel is the presence or absence of the signal, and the channel to be switched is the presence or absence, the selection unit 160 provides the horizontal synchronization signal provided from the PLL 130 based on the determination signal from the presence / absence signal determination unit 120. The clock A_CLK synchronized to Hs and the separate vertical and horizontal sync signals A_Hsync and A_Vsync provided from the sync separator 110 are output to the one-side input terminal and the frame generator 170 of the AND gate 200, respectively. do.

Accordingly, a high level output signal is output after a predetermined delay time at the output side of the D flip-flop 190 whose output value is determined by the output of the counter 180, as shown in FIG. When the user switches channels at the time A, the high-level output signal (i.e., as shown in FIG. 2) after skipping two frames (a and b frames) according to the count result in the counter 180 is used. , the output signal of high level at the rising edge of the frame c) is output to the other input terminal of the AND gate 200, and as a result, in the AND gate 200, data as shown in FIG. The generation instruction pulse is output and provided to the A / D converter 210.

As a result, the A / D converter 210 attempts to stabilize the output by suppressing the output for a predetermined delay time (e.g., two frame times), and then the input image signal RGB (e.g., FIG. A / D conversion operation for frame c) of e) is performed. Therefore, the A / D converter 210 converts the R.G.B data from the c frame into digital data and outputs the digital data to the display side of the PDP TV (not shown).

That is, in the present invention, when the switched selected channel is a signal channel, the output is stabilized for a predetermined time (for example, two complete frames, etc.), and then the stabilized image output is provided thereafter.

As described above, according to the present invention, when the channel is switched from the signal-signal channel to the signal-signal channel or the no-signal channel to the signal-signal channel, by outputting a video from a subsequent frame after blocking the image output by a predetermined number of frames, It is possible to reliably prevent the screen of the PDP TV from becoming unstable when switching channels.

Claims (3)

In a PDP TV device that generates data on a composite video signal at the time of channel switching, when the current channel being displayed on the PDP TV screen is switched to any other channel based on an operation signal from the outside. Sync separation means (110) for separating horizontal and vertical sync signals from the composite video signal for the switching channel; Discriminating means (120) for discriminating the presence / absence signal of the switching channel based on the detection result of the horizontal synchronizing signal and the vertical synchronizing signal separated by the synchronizing separating means (110); A PLL (130) for generating a clock synchronized with the horizontal synchronizing signal separated by the synchronizing separation means (110); Clock generating means (140) for generating a clock in synchronism with the clock generated in the PLL (130); Synchronization generating means (150) which itself generates another horizontal synchronization signal and a vertical synchronization signal corresponding to the horizontal and vertical synchronization signals included in the separated composite video signal; On the basis of the discrimination signal from the discriminating means 120, the synchronizing signal from the synchronizing separation means 110 and the synchronizing signal from the synchronizing generating means 150 are selectively output and simultaneously from the PLL 130. Selecting means (160) for selectively outputting a clock and a clock from the clock generating means (140); A data generation instruction for generating a data generation instruction clock for delaying the A / D conversion output of the input image data for a predetermined time based on the selected horizontal and vertical synchronizing signal and the clock output from the selection means 160; Means 170, 180, 190, 200; And A / D conversion for converting the analog RGB signal of the switching channel into digital after the predetermined time delay based on the data generation instruction clock provided from the data generation instruction means 170, 180, 190, and 200. Means 210 means for generating data when switching channels in the PDP TV (PDP TV). 2. The apparatus according to claim 1, wherein the data generation indicating means; Frame generation means for generating a frame division signal for frame division based on the synchronization signal selected and output by the selection means; Data generation clock generation means for generating a data generation clock by counting the frame division signal generated from the frame generation means; A logic means configured to input a clock selected by the selection means to one input terminal and input a clock generated by the data generation clock generation means to the other input terminal to generate the data generation instruction clock. An apparatus for indicating data generation during channel switching in a television (PDP TV). 3. The apparatus of claim 2, wherein the data generation clock generation means; A counter for counting frame division signals from the frame generating means; And a D flip-flop for generating the data generation clock when the number of the frame division signals counted by the counter is set to a predetermined number.