JP2001285669A - Synchronizing signal processing circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a conventional synchronizing signal processing circuit has caused disturbance in synchronization of a video image due to switching noise or the like of a diversity antenna. SOLUTION: The synchronizing signal processing circuit, which separates (101, 102) a composite synchronizing signal into a horizontal synchronizing period and a vertical synchronizing period and provides outputs of a horizontal synchronizing signal and a vertical synchronizing signal, is provided with a mask means that masks (107, 108) the vertical synchronizing period discriminated again so as not to provide any output for periods 103, 105, 106 corresponding to preset number of horizontal lines even when the vertical synchronizing signal is outputted through the discrimination of the vertical synchronizing period and vertical synchronizing period is again discriminated within a prescribed time after its output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal processing circuit and a display device, and more particularly to a horizontal synchronization signal (HSYNC) from a composite synchronization signal (CSYNC) included in a video signal from a television broadcast or a video device (VTR). ) And a vertical synchronizing signal (VSYNC).

In recent years, for example, a car television system or a car navigation system with a television for displaying a television broadcast on a liquid crystal display device or the like in a vehicle using a diversity antenna has been used. In such a car navigation device with a television using such a diversity antenna, for example, video synchronization is disturbed due to switching noise of the diversity antenna or the like. Further, for example, when the tape is fast-forwarded while reproducing the image on the VTR, there is a problem that the image is disturbed due to lack of synchronization. Therefore, there is a demand for a synchronization signal processing circuit and a display device that can prevent disturbance of video synchronization due to switching noise of a diversity antenna, fast-forward operation during VTR image reproduction, and the like.

[0003]

2. Description of the Related Art FIG. 1 is a block diagram schematically showing an example of a liquid crystal display system to which a synchronous signal processing circuit is applied, for example, showing an example of a car television system mounted on a car. In FIG. 1, reference numeral 1 denotes a TV tuner, 2 denotes an RGB decoder, 3 denotes a liquid crystal display unit, 4 denotes an on-screen control circuit, 5 denotes a video signal synthesizing circuit, 10 denotes a VTR, and 11 denotes an antenna (diversity antenna). Is shown. Here, the liquid crystal display unit 3 includes a liquid crystal display unit (image display unit) 31 and a synchronization signal processing and liquid crystal control unit 32. The synchronization signal processing circuit to which the present invention is applied is included in the synchronization signal processing and liquid crystal control unit 32.

As shown in FIG. 1, a TV tuner 1
Alternatively, a video signal (composite synchronization signal + video signal) from the VTR 10 is supplied to the RGB decoder 2 and separated into a video signal (RGB) and a composite synchronization signal (CSYNC). The video signal RGB from the RGB decoder 2 is supplied to the video signal synthesizing circuit 5 and the on-screen control circuit 4
The video signal RG is synthesized with the video signal for on-screen from
B ′ is supplied to the liquid crystal display section 31 of the liquid crystal display unit 3. Then, on the display screen (LCD) of the liquid crystal display unit 31, an on-screen image (312) by the on-screen control circuit 4 is displayed together with the video (311) from the TV tuner 1 or the like.

The composite synchronizing signal CS from the RGB decoder 2
The YNC is supplied to the synchronizing signal processing and liquid crystal control unit 32 of the liquid crystal display unit 3, and the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VS synchronized with the composite synchronizing signal CSYNC.
YNC is output. Here, the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC output from the synchronizing signal processing and liquid crystal control unit 32 are supplied to, for example, an on-screen control circuit 4 for on-screen synchronizing with the video signal from the RGB decoder 2. Video signal is generated,
The video signal is synthesized in the video signal synthesizing circuit 5 while maintaining synchronization.

The synchronizing signal processing and liquid crystal control section 32 outputs various control signals for driving the liquid crystal display section 31, and causes the liquid crystal display section 31 to display an image corresponding to the output RGB 'of the video signal synthesizing circuit 5. Here, for example, an image (311) corresponding to the output of the TV tuner 1 is displayed on the liquid crystal display unit 31.
At the same time, an on-screen image (312) is also displayed.

[0007]

FIGS. 2 and 3 are timing charts for explaining the problems in the conventional synchronous signal processing circuit. FIG. 3 is a diagram showing a vertical counter reset signal (VD2H) obtained by shortening FIG. 2 in the time direction. ). As shown in FIGS. 2 and 3, for example, the vertical synchronization signal VSYNC (VSYNC0) is
It is obtained by integrating 3H (3 horizontal synchronization periods) in SYNC. However, for example, T
When the diversity antenna 11 is switched while the V tuner 1 is receiving a television broadcast, the switching noise of this antenna is reduced by the vertical synchronization signal VSYNC (VSC).
YNC1) may be erroneously recognized. That is, two vertical synchronization signals VSYNC (VSYNC0, VSYNC1) within one vertical synchronization period (1V: one frame).
And two vertical counter reset pulses V-RS
T (V-RST0, V-RST1) is output, and as a result, the vertical counter is reset twice within one vertical synchronization period 1V (that is, the vertical counter reset pulse V-RST).
Falling timing (vertical counter reset VD
2H).

FIG. 4 is a diagram for explaining a problem in the conventional synchronous signal processing circuit. In FIG. 4, reference numeral 331 indicates a switch provided outside the liquid crystal display unit 31. Here, the on-screen image 312 of the liquid crystal display unit 31 corresponds to the switch 331, and displays the function of each switch, for example. However, as described above, for example, one vertical synchronization period (1
V), a plurality (for example, two) of vertical synchronization signals (VSY)
When NC0, VSYNC1) is detected, the on-screen image 312 may fluctuate up and down on the liquid crystal display unit 31, for example, causing the switch 331 and the on-screen image 312 on the liquid crystal display unit 31 to be displaced or disturbed. Was. Alternatively, even when a tape is fast-forwarded while an image is being reproduced by the VTR 10, a plurality of vertical synchronizing signals are detected within one vertical synchronizing period, and the video on the liquid crystal display unit 31 may be out of synchronization.

As described above, in the conventional car television system and the car navigation apparatus with a television, the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are used.
Is simply obtained separately from the composite synchronization signal CSYNC. For example, if noise due to switching of a diversity antenna or a fast-forward operation at the time of VTR image reproduction is mixed into the composite synchronization signal CSYNC, the composite synchronization signal In some cases, it is erroneously determined that one frame of CSYNC includes a plurality of vertical synchronizations.
As a result, normal / horizontal synchronization cannot be determined or separated and output in a normal cycle, and synchronization is disturbed and a normal video cannot be displayed.

The present invention has been made in view of the above-mentioned problems in the prior art, and even when an unnecessary pulse or the like is mixed in a composite synchronizing signal, the horizontal and vertical synchronizing signals are separated and output without being affected by the mixed pulse. It is an object of the present invention to provide a synchronization signal processing circuit and a display device that can prevent synchronization disturbance.

[0011]

A synchronizing signal processing circuit according to the present invention separates a composite synchronizing signal into horizontal and vertical synchronizing signals and outputs a horizontal synchronizing signal and a vertical synchronizing signal. I have. This mask means outputs the vertical synchronization signal after judging the vertical synchronization, and then determines the vertical synchronization again within a predetermined time, even if the period corresponding to the preset number of horizontal lines is determined again. Vertical sync is not masked and output.

A display device according to the present invention includes the above-described synchronization signal processing circuit and an image display unit (for example, a liquid crystal display unit).
It has. The synchronization signal processing circuit further includes a sampling holding unit and a switching unit. The sampling and holding means samples whether or not vertical synchronization exists in the composite synchronization signal during a mask period after outputting the vertical synchronization signal, and holds the value. The switching means sets n to be an integer of 2 or more, and when vertical synchronization exists in the composite synchronization signal for n consecutive frames during the mask period,
In the (n + 1) th frame, the vertical synchronizing signal separated from the composite synchronizing signal is output without masking.

That is, according to the present invention, a composite sync signal is digitally integrated, and a vertical sync separation pulse (vertical sync signal V
SYNC) is obtained a plurality of times during one frame (one field, one vertical synchronization period 1V), the first pulse is used as the vertical synchronization part. Further, when the first pulse is not the vertical synchronization portion of the composite synchronization signal due to erroneous discrimination, the number of lines is stored in an internal register with the vertical synchronization pulse obtained within the mask period, and the vertical synchronization pulse is similarly generated in the second frame. If the values coincide with each other, the phase of the external vertical synchronizing signal with respect to the composite synchronizing signal is changed in the third frame.

Thus, for example, while using the car navigation device with a television, the TV is used between buildings or in mountainous areas.
Noise frequently occurs when the signal receiving state is weakened and the diversity antenna switches to one of a plurality of stronger radio waves during the vertical synchronization period, or when the tape is fast-forwarded while reproducing the image on the VTR. By masking the output of the discrimination signal even in the case of being mixed in the composite synchronization signal, the noise portion is not erroneously determined to be a vertical synchronization signal.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a synchronization signal processing circuit and a display device according to the present invention will be described below in detail with reference to the drawings. FIG. 5 is a block diagram showing an embodiment of the synchronization signal processing circuit according to the present invention, and FIGS. 6 to 8 are timing charts for explaining the operation of the synchronization signal processing circuit of FIG.

In FIG. 5, reference numeral 100 is a synchronization signal processing circuit, 101 is a horizontal synchronization signal separation circuit, 102 is a vertical synchronization signal separation circuit, 103 is a line counter, 104
Is a waveform shaper, 105 is a memory register, 106 is a comparator, 107 is a line mask signal generation circuit, and 10
Reference numeral 8 denotes a logic gate (AND gate). Here, the synchronization signal processing circuit 100 performs the synchronization signal processing and the liquid crystal control unit 32 in the liquid crystal display system of FIG.
include.

As shown in FIG. 5, a synchronization signal processing circuit 100 of the present embodiment includes a line counter in addition to a horizontal synchronization signal separation circuit 101 and a vertical synchronization signal separation circuit 102 provided in a conventional synchronization signal processing circuit. 103, a waveform shaper 104, a memory register 105, a comparator 106, a line mask signal generation circuit 107, and an AND gate 108.

The horizontal synchronizing signal separating circuit 101 receives the composite synchronizing signal CSYNC from the RGB decoder (2), separates and outputs a signal S1 (horizontal synchronizing signal HSYNC),
Further, the vertical synchronizing signal separating circuit 102 outputs the composite synchronizing signal C
SYNC is received and the signal S2 (vertical synchronization signal VSYNC
C) is separated and output. The line counter 103 receives the output signal S1 (vertical counter pulses CS1 and CS2) of the horizontal synchronization signal separation circuit 101, counts the number of pulses, and supplies the count value (S3) to the line mask signal generation circuit 107. Line mask signal generation circuit 10
7 is a pulse (output S) from the vertical sync separation circuit 102.
The output (S2) of the vertical sync separation circuit 102 is input to the waveform shaper 104 (S2) during the number of lines (period corresponding to the horizontal line) that is set such that 2) passes once in one frame.
8) to prevent the resetting of the line counter 103 and the malfunction of the setting of the waveform shaper 104.
Here, the line counter 103 is reset by an output signal S2 (line counter reset pulse RST) of the vertical synchronization signal separation circuit 102.

The operation of the synchronizing signal processing circuit according to the present embodiment will be briefly described. First, as shown in FIGS. 5 and 6, the output S3 of the line counter 103 (count value: the horizontal synchronizing signal HSYNC is counted. The obtained vertical synchronization signal VSYNC) is output to the line mask signal generation circuit 107.
And the output S2 of the vertical synchronization signal separation circuit 102
(Vertical synchronization signal V obtained from composite synchronization signal CSYNC
SYNC) passes once in one frame (one field: one vertical synchronization period), and the output of the vertical synchronization signal separation circuit 102 is output from the waveform shaper 104 during the number of lines (for example, 190 horizontal synchronization periods: 190H). Is suppressed (masked).

That is, when the vertical synchronizing signal separating circuit 102 separates and outputs the vertical synchronizing signal VSYNC from the composite synchronizing signal CSYNC, for example, a malfunction such as resetting of the line counter 103 due to an erroneous vertical synchronizing signal due to diversity antenna switching noise or the like may occur. To prevent this, the output signal S2 of the vertical synchronization signal separation circuit 102 is masked by the AND gate 108 for a predetermined period thereafter (for example, a period of 190H). Specifically, during a period of 190H after the vertical synchronization signal separation circuit 102 separates and outputs the vertical synchronization signal VSYNC, the negative logic input S7 of the AND gate 108 (the output VD of the line mask signal generation circuit 107).
2H) becomes high level “H”, and the output S2 of the vertical synchronization signal separation circuit 102 is masked.

Next, as shown in FIGS. 5 and 7,
For example, the vertical synchronizing signal separation circuit 102
If the vertical synchronization signal VSYNC cannot be separated and output from the SYNC (in the case of missing), the line counter 103 counts the horizontal synchronization signal HSYNC by a predetermined number (for example, 522 times), and obtains the obtained vertical synchronization signal. The synchronization signal VSYNC (S3) is shaped and output. At this time, the signal S2 (vertical synchronization signal VSYNC) separated and output from the composite synchronization signal CSYNC by the vertical synchronization signal separation circuit 102 is also monitored at the same time. For example, the monitored vertical synchronization signal VSYNC ( When the output signal S2)) of the vertical synchronization signal separation circuit 102 is correctly output continuously for three frames, the output S3 (VSYNC) obtained by counting the number of pulses of the horizontal synchronization signal HSYNC by the line counter 103 is output. ) Is switched to the vertical synchronization signal VSYNC separated from the composite synchronization signal.

That is, if the vertical synchronizing signal VSYNC (S2) separated and output from the composite synchronizing signal CSYNC is missing, the vertical counter reset pulse V-RST0 is not output, so that the horizontal synchronizing signal HSYNC is counted by a predetermined number. Vertical synchronization signal VSYNC obtained by
Vertical counter reset signal VD2H based on (S3)
STR0, VD2HSTR1,... Are used. At this time, the vertical synchronizing signal VSYNC (vertical counter reset pulse VR) which is separately output from the composite synchronizing signal CSYNC is output.
ST) are also monitored, and for example, the vertical counter reset pulses V-RST1 to V-RS are successively provided for three frames.
When T3 is output, the vertical counter reset signal VD2HSTR based on the internal vertical synchronization signal up to that time is output.
From 3, the switching to the vertical counter reset pulse V-RST4 based on the vertical synchronization signal separated and output from the composite synchronization signal is performed.

Further, as shown in FIGS. 5 and 8, for example, the vertical synchronizing signal VSYNC separated and output from the composite synchronizing signal CSYNC by the vertical synchronizing signal separating circuit 102.
In the case where the horizontal synchronization signal HSYNC is shifted by a predetermined number by the line counter 103, the vertical synchronization is obtained by using the internal vertical synchronization signal VSYNC (S3) obtained, for example.

That is, if the vertical synchronizing signal VSYNC from the composite synchronizing signal CSYNC is output at a shifted position, the vertical counter reset pulse V-RST0 is not output. A vertical counter reset signal VD based on an internal vertical synchronization signal obtained by counting HSYNC by a predetermined number.
2HSTR0, VD2HSTR1,... Are used. At this time, the vertical synchronizing signal VSYNC (vertical counter reset pulse V-RST), which is output separately from the composite synchronizing signal CSYNC, is monitored. For example, the vertical counter reset pulses V-RST1 to V-RST1 to V-RST1 are continuously output for three frames.
When RST3 is output, the vertical counter reset signal VD2H based on the internal vertical synchronization signal up to that time is output.
From STR3, a vertical counter reset pulse V-RS based on a vertical synchronization signal separated and output from the composite synchronization signal.
It will be switched to T4. Here, the number of frames in which the vertical counter reset pulses (V-RST1 to V-RST3) are continuously output is not limited to three, but may be set to, for example, two or more various numbers of frames. Can be.

A display device according to the present invention includes the above-described synchronization signal processing circuit and an image display unit (for example, a liquid crystal display unit 31). Hereinafter, each configuration and operation of the synchronization signal processing circuit of the present embodiment will be described in detail. FIG. 9 is a block diagram showing an example of the horizontal synchronizing signal separating circuit 101 in the synchronizing signal processing circuit of FIG. 5, and FIG. 10 is a timing chart for explaining the operation of the horizontal synchronizing signal separating circuit of FIG.

As shown in FIG. 9, the horizontal synchronizing signal separating circuit 101 includes a phase detector 111, a voltage controlled oscillator (V
CO) 112, horizontal counters 113 and 114, and
The apparatus is provided with a waveform shaper 115. As shown in FIG. 10, the horizontal counter 113 outputs an output CS1 having one pulse in one horizontal synchronization period 1H, and the horizontal counter 114 has two pulses in one horizontal synchronization period 1H. The output CS2 is output. The output CS of these horizontal counters 113 and 114
1, CS2 (vertical counter pulse) is supplied to the line counter 103. Here, the output CS1 of the horizontal counter 113 is waveform-shaped by the waveform shaper 115,
It will be output to the outside as the horizontal synchronization signal HSYNC.

FIG. 11 is a block diagram showing an example of the vertical synchronizing signal separating circuit 102 in the synchronizing signal processing circuit of FIG. 5, and FIG. 12 is a timing chart for explaining the operation of the vertical synchronizing signal separating circuit of FIG. is there. As shown in FIG. 11, the vertical synchronization signal separation circuit 102 is configured as, for example, an integration circuit, and includes an up / down counter (UP / D
An OWN counter 121 and a counter 122 are provided. The UP / DOWN counter 121 is a counter 12
2 separates and outputs the vertical synchronization signal VSYNC,
It is to be reset. The vertical synchronization signal separation circuit 102 detects the vertical synchronization signal portion (3H) of the composite synchronization signal CSYNC and separates and outputs the vertical synchronization signal VSYNC (line counter reset pulse RST). The output of the UP / DOWN counter 121 The CS3 and the line counter reset pulse RST have waveforms as shown in FIG. Note that the vertical synchronization signal separation circuit 1
02 is supplied to the line counter 103, the memory register 105, and the line mask signal generation circuit 107, as shown in FIG.
The signal is supplied to the waveform shaper 104 via the D gate 108. Here, even when the line mask signal (S7) is output and line masking is being performed, the composite synchronization signal CSYNC is input to the UP / DOWN counter 121 and the counter 122 is moved to determine vertical synchronization. .

FIG. 13 is a block diagram showing an example of the line counter 103, the memory register 105 and the comparator 106 in the synchronous signal processing circuit of FIG. 5, and FIG. 14 is an operation of the line counter, memory register and comparator of FIG. FIG. 6 is a timing chart for explaining the operation of FIG. As shown in FIG. 13, the line counter 103 includes a vertical direction control line counter 131 and a memory line counter 132. Line counter 1 for vertical control
31 includes an output CS1 of the horizontal counter 113 in the horizontal synchronization signal separation circuit 101 and a line counter reset pulse RST (S
2) is supplied, and the memory line counter 132
Is supplied with the output CS2 of the horizontal counter 114 in the horizontal synchronization signal separation circuit 101 and the line counter reset pulse RST. Accordingly, the line counter 131 for vertical direction control is set to 1 during one horizontal synchronization period (1H).
Counts up and the memory line counter 1
32 counts up twice in one horizontal synchronization period.

The memory register 105 includes a preset D flip-flop 151, a selector 152, and a set D flip-flop 153. The output S30 of the memory line counter 132 is supplied to the D input of the D flip-flop 151, and the start pulse V-RSTS supplied to its enable input (output at the rising timing of the vertical counter reset pulse V-RST in FIG. 6) The pulse is taken in and held in response to the pulse. The selector 152 receives the control signal SS
For example, the fixed value (522) is selected when the switch is turned on and during the first vertical synchronization period, and in other cases, the output of the flip-flop 151 is selected and output. The output of the selector 152 is supplied to the D input of the D flip-flop 153, and the line counter reset pulse RST supplied to its enable input is provided.
According to (S2), it is taken in and held. Note that ten flip-flops 151 and 153 are provided, for example, for processing 10-bit values, respectively.

The comparator 106 is constituted by, for example, a magnitude comparator. When the input S30 (output of the memory line counter 132) and the input S5 (output of the flip-flop 153) are equal (S30 = S5),
Output pulse. The output S5 of the memory register 105 is the output (count value) of the memory line counter 132 captured in response to the start pulse V-RSTS and the line counter reset pulse RST, or a fixed value (522). .

Thus, as shown in FIG. 14, for example, when the memory line counter 132 counts up to 522, a suspected UP / DOWN count output CS3 'is output, and a suspected line counter reset pulse R
ST ′ will be output. Note that the suspect line counter reset pulse RST ′ is output at a timing later than the normal line counter reset pulse RST.

Here, when it is determined that a vertical synchronizing signal exists in the composite synchronizing signal CSYNC, the vertical synchronizing separation circuit (1
02), a pulse is constantly output, and the position (the number of line counters 103) where the pulse was output is stored in the memory register 105. The frame in which the value is stored is the first
In the case of a frame, it is determined that the vertical synchronization signal is present within the line mask period also in the second frame, and the value of the line counter 103 to which the pulse is output from the vertical synchronization separation circuit (102) and the memory register 105 in the first frame. Are compared by the comparator 106, and when they match, the operation of the line mask signal S7 is suppressed in the third frame,
Each time a pulse is output from the vertical synchronization separation when the vertical synchronization can be determined, the line counter 103 is reset to output the vertical synchronization signal VSYNC.

FIG. 15 is a block diagram showing an example of the line mask signal generation circuit 107 in the synchronization signal processing circuit of FIG. As shown in FIG. 15, the line mask signal generation circuit 107 includes an AND gate 171 and a JK flip-flop 172. The output S6 of the comparator 106 and the output S2 of the vertical synchronizing signal separation circuit 102 are supplied to the AND gate 171. The output of the AND gate 171 is supplied to the J input of the flip-flop 172. The output S3 of the line counter is supplied to the K input of the flip-flop 172, and a clock signal is supplied to the clock input CK. Here, the output S3 of the line counter supplied to the K input is, for example, a signal obtained by counting 190H, and the output S7 of the flip-flop 172 is a 190H mask signal (see VD2H in FIG. 6).

The output S7 of the flip-flop 172 is A
The output S2 of the vertical synchronizing signal separation circuit 102 supplied to the negative logic input of the ND gate 108 and supplied to the positive logic input of the AND gate 108 during the high level "H" (190H) is masked. I have. In the above,
The mask period is not limited to 190H, but can be various values, and the fixed value (522) set in the selector 152 can be appropriately changed. Further, for example, the line counter 103, the waveform shaper 104, the memory register 105, the comparator 106, and the like shown in FIG.
Line mask signal generation circuit 107 and logic gate 10
It goes without saying that the configuration such as 8 can be variously modified.

As described above, according to each embodiment of the synchronization signal processing circuit of the present invention, unnecessary pulses generated at the time of antenna switching which frequently occur in the environment of a moving body such as a car, and unnecessary signals generated at the time of VTR reproduction are obtained. The conventional problem that the synchronous signal processing circuit malfunctions due to unnecessary pulses generated at the time of fast-forward or the like can be solved, and the accuracy of the synchronous signal processing circuit can be improved.

[0036]

As described in detail above, according to the present invention, even when an unnecessary pulse or the like is mixed in a composite synchronizing signal, the horizontal and vertical synchronizing signals can be separated and output without being affected by the pulse. And a display device.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically illustrating an example of a liquid crystal display system to which a synchronization signal processing circuit is applied.

FIG. 2 is a timing chart (part 1) for describing a problem in a conventional synchronization signal processing circuit.

FIG. 3 is a timing chart (part 2) for describing a problem in the conventional synchronization signal processing circuit.

FIG. 4 is a diagram for explaining a problem in a conventional synchronization signal processing circuit.

FIG. 5 is a block diagram showing one embodiment of a synchronization signal processing circuit according to the present invention.

6 is a timing chart (part 1) for explaining the operation of the synchronization signal processing circuit of FIG. 5;

FIG. 7 is a timing chart (part 2) for explaining the operation of the synchronization signal processing circuit of FIG. 5;

8 is a timing chart (part 3) for explaining the operation of the synchronization signal processing circuit of FIG. 5;

9 is a block diagram illustrating an example of a horizontal synchronization signal separation circuit in the synchronization signal processing circuit of FIG.

FIG. 10 is a timing chart for explaining the operation of the horizontal synchronizing signal separation circuit of FIG. 9;

11 is a block diagram illustrating an example of a vertical synchronization signal separation circuit in the synchronization signal processing circuit of FIG.

FIG. 12 is a timing chart for explaining the operation of the vertical synchronization signal separation circuit of FIG. 11;

13 is a block diagram illustrating an example of a line counter, a memory register, and a comparator in the synchronization signal processing circuit of FIG.

FIG. 14 is a timing chart for explaining operations of a line counter, a memory register, and a comparator in FIG. 13;

FIG. 15 is a block diagram illustrating an example of a line mask signal generation circuit in the synchronization signal processing circuit of FIG. 5;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 TV tuner 2 RGB decoder 3 Liquid crystal display unit 4 On-screen control circuit 5 Video signal synthesizing circuit 10 VTR 11 Antenna (diversity antenna) 31 Liquid crystal display unit 32 Synchronous signal processing and liquid crystal control unit 100 ... Synchronization signal processing circuit 101 ... Horizontal synchronization signal separation circuit 102 ... Vertical synchronization signal separation circuit 103 ... Line counter 104 ... Waveform shaper 105 ... Memory register 106 ... Comparator 107 ... Line mask signal generation circuit 108 ... Logic gate (AND gate) ) CSYNC: composite synchronization signal HSYNC: horizontal synchronization signal VSYNC: vertical synchronization signal

Claims (5)

[Claims] 1. A synchronizing signal processing circuit for separating a composite synchronizing signal into horizontal and vertical synchronizing signals and outputting a horizontal synchronizing signal and a vertical synchronizing signal. After that, even if vertical synchronization is determined again within a predetermined time, masking means for masking and not outputting the vertical synchronization determined again for a period corresponding to the preset number of horizontal lines is provided. Signal processing circuit. 2. The synchronizing signal processing circuit according to claim 1, wherein the synchronizing signal processing circuit further comprises: a mask period after outputting the vertical synchronizing signal.
Sampling means for sampling whether or not vertical synchronization exists in the composite synchronization signal, and holding the sampled value; switching means for switching to the vertical synchronization signal synchronized with the vertical synchronization portion of the composite synchronization signal; A synchronization signal processing circuit comprising: 3. A horizontal synchronizing signal separating unit for separating a horizontal synchronizing signal from a composite synchronizing signal; a vertical synchronizing signal separating unit for separating a vertical synchronizing signal from the composite synchronizing signal; And a masking means for masking the output of the vertical synchronizing signal separating means for a preset mask period after separating and outputting the synchronizing signal. 4. A horizontal synchronizing signal separating unit for separating a horizontal synchronizing signal from a composite synchronizing signal, a vertical synchronizing signal separating unit for separating a vertical synchronizing signal from the composite synchronizing signal, and a vertical synchronizing signal by the vertical synchronizing signal separating unit. A detecting means for detecting a case where the vertical synchronization signal is not separated within a predetermined period,
An internal vertical synchronizing signal generating means for generating an internal vertical synchronizing signal by counting a predetermined number of one horizontal synchronizing period by the horizontal synchronizing signal separating means, and the vertical synchronizing signal even when the vertical synchronizing signal is not separated within a predetermined period. Monitoring means for monitoring the output of the signal separation means; and selecting and outputting the internal vertical synchronization signal if the vertical synchronization signal is not separated within a predetermined period, and selecting the internal vertical synchronization signal. And selecting means for selecting and outputting the output of the vertical synchronizing signal separating means when the output of the vertical synchronizing signal separating means is continuously detected by the monitoring means for a predetermined number of frames. A synchronizing signal processing circuit characterized by the above-mentioned. 5. A display device comprising: the synchronization signal processing circuit according to claim 1; and an image display unit.