JP3911862B2 - Pixel clock signal generation device and synchronization signal generation device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a pixel clock signal generation device and a synchronization signal generation device.
[0002]
[Prior art]
For example, a display device that displays character data and image data generated by a computer or the like on a display incorporates a synchronization signal generation device that generates various synchronization signals necessary for display display.
By the way, the frequency of such a synchronization signal is different from each other of television systems such as NTSC (National Television System Committee) system and PAL (Phase Alternation by Line) system and VESA (Video Electronics Standards Association) system based on personal computer monitor standards. The display methods are different from each other.
Therefore, conventionally, as described below, each display method generates a synchronization signal using a unique synchronization signal generation device.
The synchronization signal is the composite synchronization signal CSync and the color subcarrier reference signal Fsc in the case of the NTSC system and the PAL system, and in the case of the VESA system, the horizontal synchronization signal HSync, the horizontal blank signal HB1ank, the vertical synchronization signal VSync, and the vertical horizontal blank signal. VBlank and field signal Field.
[0003]
FIG. 8 is a configuration diagram of a conventional NTSC synchronization signal generating apparatus 1.
The synchronization signal generation device 1 includes an original oscillation circuit 2 and a synchronization signal generation circuit 3.
The original oscillation circuit 2 generates a 14.31818 MHz original oscillation signal S2 for NTSC, for example, and outputs the original oscillation signal S2 to the synchronization signal generation circuit 3.
The synchronization signal generation circuit 3 generates a synchronization signal S3 based on the original oscillation signal S2. In the synchronization signal generation circuit 3, for example, a built-in horizontal synchronization signal generation counter generates a horizontal synchronization signal HSync that generates one pulse when 910 pulses included in the original oscillation signal S2 are counted.
The conventional PAL synchronous signal generator shown in FIG. 8 except that the original oscillation circuit 2 shown in FIG. 8 uses the one that outputs the PAL 17.7345 MHz original oscillation signal S2. This is the same as the synchronization signal generating device 1.
In the case of the PAL system, the synchronization signal generation circuit 3 generates, for example, a horizontal synchronization signal that generates one pulse when the built-in horizontal synchronization signal generation counter counts 908 pulses included in the original oscillation signal S2. A signal HSync is generated.
[0004]
FIG. 9 is a configuration diagram of a conventional VESA method synchronization signal generation apparatus 11, and FIG. 10 is a practical vertical synchronization signal frequency (V frequency), horizontal synchronization signal frequency (H frequency), and resolution that can be selected by the VESA method. It is a figure which shows the correspondence of the frequency of a pixel clock signal.
In the VESA method, as shown in FIG. 10, various pixel clock signals having different frequencies are used, and the synchronization signal generator 11 selects an arbitrary frequency from these frequencies as the frequency of the pixel clock signal. it can.
Here, the pixel clock signal is a signal that is used to generate a synchronization signal that serves as a reference when a pixel display is performed on a computer display.
[0005]
The synchronization signal generation device 11 includes a PLL circuit 5 and a synchronization signal generation circuit 3. For example, the PLL circuit 5 generates a pixel clock signal S5 by synchronizing the phase of the system clock signal S6 of the personal computer with a frequency corresponding to the frequency division ratio indicated by the frequency division ratio selection signal S12 input from the outside. The clock signal S5 is output to the synchronization signal generation circuit 7.
The synchronization signal generation circuit 7 generates the synchronization signal S7 using the pixel clock signal S5.
[0006]
[Problems to be solved by the invention]
However, since the NTSC and PAL synchronous signal generators 1 shown in FIG. 8 described above use the original oscillation circuit 2, it is difficult to determine the frequency, and there is a problem that the scale is large and the price is high.
Further, in the VESA synchronous signal generator 11 shown in FIG. 9 described above, the system clock signal S6 cannot be drawn into the pixel clock signal S5 having a practical frequency shown in FIG. 10 with high accuracy by using only the PLL circuit. There is a problem.
[0007]
The present invention has been made in view of the above-described problems of the prior art, and is a pixel clock signal generation apparatus and synchronization that can generate pixel clock signals of various frequencies that are practically used with high accuracy in a small-scale and low-cost apparatus configuration. An object is to provide a signal generation device.
[0008]
[Means for Solving the Problems]
  In order to solve the above-described problems of the prior art and achieve the above-described object, the pixel clock signal generation apparatus of the present invention generates a pixel clock signal used to generate a synchronization signal for display display. A signal generation device, a first frequency dividing circuit that divides a reference clock signal by a frequency division ratio indicated by a first frequency division ratio instruction signal to generate a first clock signal, and the first clock A phase comparison circuit that performs phase comparison between the signal and the second clock signal, a voltage-controlled oscillation circuit that generates a third clock signal oscillated according to the result of the phase comparison, and a third clock signal A PLL circuit having a second frequency dividing circuit that divides by a frequency dividing ratio indicated by a frequency dividing ratio indicating signal of 2 and generates the second clock signal;A plurality of serially connected frequency dividing circuits for inputting the second clock signal to a first-stage frequency dividing circuit; and a plurality of clock signals respectively output from the plurality of frequency dividing circuits; A selection circuit that selects one of the signals based on a third division ratio instruction signal and outputs the selected clock signal as the pixel clock signal;And a third frequency dividing circuit for generating the pixel clock signal by dividing the second clock signal by a frequency dividing ratio indicated by a third frequency dividing instruction signal.
[0009]
In the pixel clock signal generation device of the present invention, the first frequency division ratio instruction signal, the second frequency division ratio instruction signal, and the second frequency division ratio instruction signal are respectively supplied to the first frequency division circuit, the PLL circuit, and the first frequency division circuit. 3 is input to the frequency divider circuit 3.
Then, in the first frequency dividing circuit, the reference clock signal is frequency-divided by the frequency dividing ratio indicated by the first frequency dividing ratio instruction signal to generate the first clock signal.
The first clock signal is output to the PLL circuit, and in the voltage-controlled oscillation circuit of the PLL circuit, a second frequency obtained by multiplying the frequency of the first clock signal by the division ratio indicated by the second division ratio instruction signal. Clock signals are generated.
Next, in the third frequency dividing circuit, the second clock signal is frequency-divided by the frequency dividing ratio indicated by the third frequency dividing ratio instruction signal to generate a pixel clock signal.
[0010]
The pixel clock signal generation device of the present invention preferably combines the frequency division ratios indicated by the first frequency division ratio instruction signal, the second frequency division ratio instruction signal, and the third frequency division ratio instruction signal. Thus, one pixel clock signal is selected and generated from the pixel clock signal used for display display for a computer and the pixel clock signal used for display display for a television.
[0011]
The synchronization signal generation device of the present invention is a synchronization signal generation device that generates a pixel clock signal by a pixel clock signal generation circuit and generates a synchronization signal for display display by the synchronization signal generation circuit using the pixel clock signal. The pixel clock signal generation circuit divides a reference clock signal by a division ratio indicated by a first division ratio instruction signal to generate a first clock signal; A phase comparison circuit that performs phase comparison between a first clock signal and a second clock signal, a voltage-controlled oscillation circuit that generates a third clock signal oscillated in accordance with a result of the phase comparison, A PLL circuit having a second frequency dividing circuit for generating the second clock signal by dividing the clock signal by the frequency dividing ratio indicated by the second frequency dividing ratio indicating signal; and a third frequency dividing ratio indicating Signal Said at to divide ratio second clock signal by dividing a third divider for generating the pixel clock signal. The synchronization signal generation circuit includes a horizontal synchronization signal generation circuit that generates a horizontal synchronization signal and a horizontal blank signal based on the pixel clock signal, and a vertical synchronization signal based on the pixel clock signal and the horizontal synchronization signal. And a vertical synchronizing signal generating circuit for generating a vertical blank signal, and a composite synchronizing signal generating circuit for generating a composite synchronizing signal based on the horizontal synchronizing signal and the vertical synchronizing signal.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a pixel clock signal generation circuit and a synchronization signal generation device according to embodiments of the present invention will be described.
FIG. 1 is a block diagram of the synchronization signal generator 31 of this embodiment, and FIGS. 2 and 3 are the system clock signal frequency, display method, and division ratio instruction signals S60, S61, and S62 shown in FIG. It is a figure which shows the relationship between the circumference ratio, the frequency of the clock signal output from the VCO 43, the frequency of the pixel clock signal S32, and the error between the pixel clock signal S32 and a predetermined practical value.
The synchronization signal generation device 31 includes a pixel clock signal generation circuit 32, a synchronization signal generation circuit 33, and a count value storage memory 37.
The synchronization signal generator 31 is provided in, for example, a personal computer, generates a synchronization signal S33 used when displaying an image signal generated by the personal computer on a display, and outputs the synchronization signal S33 to the display. The synchronization signal generating device 31 can support any display of the NTSC system, the PAL system, and the VESA system.
[0013]
The synchronization signal generation device 31 generates the pixel clock signal S32 using the division ratio instruction signals S60, S61, S62 and the system clock signal S63 in the pixel clock signal generation circuit 32, and the synchronization signal generation circuit 33 stores the count value. A synchronization signal S33 is generated using the count value signal S37 and the pixel clock signal S32 read from the memory 37.
[0014]
Pixel clock signal generation circuit 32
As shown in FIG. 1, the pixel clock signal generation circuit 32 includes a frequency dividing circuit 34 as a first frequency dividing circuit, a PLL circuit 35, and a frequency dividing circuit 36 as a third frequency dividing circuit.
[Divider 34]
The frequency divider 34 receives a frequency division ratio instruction signal S60 from the outside, and uses the frequency division ratio R indicated by the frequency division ratio instruction signal S60 to multiply the frequency of the system clock signal S63 as a reference clock signal by 1 / R times. The generated clock signal S34 is generated, and the clock signal S34 is output to the PLL circuit 35.
Here, the frequency division ratio instruction signal S60 is, for example, 8 bits, and can specify a frequency division ratio R of “0” to “255”.
The frequency division ratio R indicated by the frequency division ratio instruction signal S60 is determined as shown in FIGS. 2 and 3 according to the system clock signal S63 and the pixel clock signal S32.
The system clock signal S43 is generated in the personal computer.
The frequency divider 34 is used to divide the system clock signal S63 into a clock signal S34 having a frequency that can be processed with high precision in the PLL circuit 35.
[0015]
[PLL circuit 35]
The PLL circuit 35 includes a phase comparison circuit 40, a charge pump 41, a loop filter 42, a VCO (Voltage Controlled 0scillator) 43 as a voltage controlled oscillation circuit, and a frequency dividing circuit 44 as a second frequency dividing circuit.
In the PLL circuit 35, a frequency dividing circuit 44 that performs L frequency division is provided between the VCO 43 and the phase comparison circuit 40. Therefore, the clock signal S43 output from the VCO 43 has a frequency L times that of the clock signal S34. Then, the clock signal S34 and the clock signal S44 are locked in phase with each other.
[0016]
The phase comparison circuit 40 performs phase comparison between the clock signal S34 from the frequency divider circuit 34 and the clock signal S44 from the frequency divider circuit 44, and generates a signal S40 having an amplitude proportional to the phase difference as a result of the phase comparison. The signal S40 is output to the charge pump 41.
[0017]
For example, the charge pump 41 detects whether the level of the signal S40 is positive or negative, and switches between inflow of current into the capacitor and outflow of current from the capacitor according to the detection result, and according to the charge accumulated in the capacitor. A signal S41 indicating the voltage is output to the loop filter.
[0018]
The loop filter 42 performs a low-pass filter process on the signal S41 from the charge pump 41, and outputs the DC voltage signal S42 subjected to the low-pass filter process to the VCO 43.
[0019]
The VCO 43 oscillates at a frequency corresponding to the DC voltage of the DC voltage signal S42, and outputs a clock signal S43 having the number of cycles to the frequency dividing circuit 44 and the frequency dividing circuit 36.
[0020]
The frequency divider 44 receives the clock signal S43 from the VCO 43, and divides the clock signal S43 by L using the frequency division ratio L indicated by the frequency division ratio instruction signal S61, thereby 1 / L of the clock signal S43. A clock signal S44 having a double frequency is generated, and the clock signal S44 is output to the phase comparison circuit 40.
Here, the frequency division ratio instruction signal S61 is, for example, 13 bits, and can specify a frequency division ratio L of “0” to “8191”.
The frequency division ratio L indicated by the frequency division ratio instruction signal S61 is determined as shown in FIGS. 2 and 3 according to the system clock signal S63 and the pixel clock signal S32.
[0021]
[Divider 36]
The frequency dividing circuit 36 includes frequency dividing circuits 50, 51, 52 that perform frequency division by 2 and a multiplexer 53.
The multiplexer 53 receives a 2-bit frequency division ratio instruction signal S62, receives a clock signal S43 from the VCO 43, a clock signal S50 from the frequency divider circuit 50, a clock signal S51 from the frequency divider circuit 51, and a frequency signal from the frequency divider circuit 52. One of the clock signals S52 is selected, and the selected clock signal is output to the synchronization signal generation circuit 33 as the pixel clock signal S32.
Specifically, the multiplexer 53 selects the clock signals S43, S50, S51, and S52, respectively, when the division ratio instruction signal S62 indicates “1”, “2”, “4”, and “8”. .
The value indicated by the frequency division ratio instruction signal S62 is determined as shown in FIGS. 2 and 3 according to the system clock signal S63 and the pixel clock signal S32.
The frequency divider 36 also has a role of generating a highly accurate pixel clock signal S32 that has been subjected to waveform shaping by removing jitter and the like included in the clock signal S43 output from the PLL circuit 35.
[0022]
Count value storage memory 37
The count value storage memory 37 stores various count values used when the synchronization signal generation circuit 33 generates the synchronization signal S33.
The count values stored in the count value storage memory 37 include HFP, HS, HBP, HF, HB, VFP, VFPE, VS, VBFE, VBP, VDP, HS, HSEQ, HSVS and the like which will be described later.
[0023]
Synchronization signal generation circuit 33
FIG. 4 is a configuration diagram of the synchronization signal generation circuit 33.
As shown in FIG. 4, the synchronization signal generation circuit 33 includes an H counter 70 as a horizontal synchronization signal generation circuit, a V counter 71 as a vertical synchronization signal generation circuit, an FSC generation circuit 72 as a color subcarrier signal generation circuit, and a composite. It has a composite counter 73 as a synchronizing signal circuit.
[H counter 70]
The H counter 70 generates a horizontal blank signal HBlank, a horizontal synchronization signal HSync, and a half horizontal synchronization signal HalfH as shown below.
The H counter 70 outputs the horizontal blank signal HBlank and the horizontal synchronization signal HSync to the outside of the synchronization signal generation circuit 33.
The H counter 70 outputs both the horizontal synchronization signal HSync and the half horizontal synchronization signal HalfH to the V counter 71 and the composite counter 73.
[0024]
As shown in FIGS. 5A and 5C, the H counter 70 counts pulses included in the pixel clock signal S32 by a count value corresponding to the sum of the count value HFP, the count value HS, and the count value HBP. The horizontal blank signal that holds the low level during the period until the high level is held during the period until the pulse included in the pixel clock signal S32 is counted by the count value corresponding to the sum of the count value HF and the count value HB. Generate HBlank.
[0025]
Further, as shown in FIG. 5B, the H counter 70 counts the pulse included in the pixel clock signal S32 by the count value HFP from the rising edge of the horizontal blank signal HBlank, and then counts the pulse by the count value HS. Until then, the horizontal synchronization signal HSync is generated that maintains the low level and maintains the high level in other periods.
[0026]
Further, as shown in FIG. 5D, the H counter 70 rises at the rising timing of the horizontal blank signal HBlank, and counts the pulse included in the pixel clock signal S32 by the count value HF from the falling timing of the horizontal blank signal HBlank. Until then, the high level is held, and then the low level is held until the pulse included in the pixel clock signal S32 is counted by the count value HB, and then the rising half horizontal synchronization signal Half is generated.
[0027]
[V counter 71]
As shown below, the V counter 71 generates a vertical blank signal VBlank, a vertical synchronization signal VSync, a field signal Field, a VFPE signal, and a VBPE signal.
The V counter 71 receives the pixel clock signal S32, the horizontal synchronization signal HSync, the half horizontal synchronization signal HalfH, and the count values VFP, VFPE, VS, VBFE, VBP, and VDP, and receives the vertical blank signal VBlank, the vertical synchronization signal VSync, and the field signal. The Field is output to the outside of the synchronization signal generation circuit 33.
The V counter 71 outputs a vertical synchronization signal VSync, a field signal Field, a VFPE signal, and a VBPE signal to the composite counter 73.
[0028]
The V counter 71 counts pulses included in the pixel clock signal S32 and switches the level according to the horizontal synchronization signal HSync, the half horizontal synchronization signal HalfH, and the count values VFP, VFPE, VS, VBFE, VBP, and VDP. Vertical blank signal VBlank shown in FIGS. 6A and 6D, vertical synchronization signal VSync shown in FIGS. 6B, 7B, and E, and fields shown in FIGS. 7C and 7F. A signal Field is generated.
[0029]
At this time, the blank signal VBlank is determined by the count values VFP, VFPE, VS, VBFE, and VBP as shown in FIG. 6A, and the low level width is counted as shown in FIG. 6D. Determined by the value VDP.
Further, the blank signal VBlank is generated in synchronization with the horizontal synchronization signal HSync.
Further, as shown in FIG. 6B, the falling timing of the vertical synchronizing signal VSync is determined by the rising timing of the blank signal VBlank and the count values VFP and VFPE, and the rising timing is determined by the falling timing and the count value. And VS. Further, as shown in FIGS. 7B and 7E, the timing at which the vertical synchronization signal VSync falls is shifted by ½ horizontal period (H / 2) between the odd field and the even field. The shift is adjusted by using the half horizontal synchronization signal HalfH.
[0030]
The V counter 71 generates a field signal Field that switches the level at the falling timing of the vertical synchronization signal VSync.
[0031]
Further, the V counter 71 uses the count values VFPE and VBFE to generate a VFPE signal and a VBFE signal that hold a high level only for a period corresponding to VFPE and VBPE shown in FIG.
[0032]
[Composite counter 73]
The composite counter 73 receives the pixel clock signal S32, the horizontal synchronization signal HSync, the half horizontal synchronization signal HalfH, the vertical synchronization signal VSync, the VFPE signal, the VBFE signal, the count values HS, HSEQ, and HSVS, and generates a composite signal CSSync.
As shown in FIG. 6C, the composite counter 73 generates a pulse using the count value HSEQ during a period when the VFPE signal is at a high level, and sets the count value HSVS during a period when the vertical synchronization signal VSync is at a low level. Are used to generate a pulse, and during a period when the VBFE signal is at a high level, a pulse is generated using the count value HSEQ to generate a composite signal CSync. Further, as shown in FIG. 6C, the composite counter 73 generates a pulse based on the horizontal synchronization signal HSync during a period other than the VFPE, VS, and VBFE periods of the composite signal CSync.
[0033]
[FSC generation circuit 72]
When the display system signal from the count value storage memory 37 indicates NTSC, the FSC generation circuit 72 outputs a color subcarrier reference signal FSC having a frequency of 3.579545 MHz synchronized with the horizontal synchronization signal HSync, and the display system signal is When PAL is indicated, a color subcarrier reference signal FSC having a frequency of 4.433618 MHz synchronized with the horizontal synchronization signal HSync is output.
[0034]
Hereinafter, the operation of the synchronization signal generation device 31 will be described.
First operation example
In this example, the operation of the synchronization signal generation device 31 when generating the NTSC synchronization signal S33 using the system clock signal S63 having a frequency of 13.5 MHz shown in FIG. 3 will be described.
In this case, as shown in FIG. 3, a frequency division ratio instruction signal S60 indicating a frequency division ratio “198” is input to the frequency divider circuit 34, and a frequency division ratio instruction signal S61 indicating a frequency division ratio “1575” is input. A frequency division ratio instruction signal S62 that is input to the PLL circuit 35 and indicates the frequency division ratio “2” is input to the frequency divider circuit 36.
[0035]
Then, the system clock signal S63 is frequency-divided by the frequency divider 34 shown in FIG. 1, and a clock signal S34 is generated by multiplying the frequency of the system clock signal S63 by “1/198”. The clock signal S34 is generated by the PLL circuit 35. Is output.
Next, the clock signal S34 is subjected to PLL processing in the PLL circuit 35 shown in FIG. 1, and a clock signal S43 having a frequency 107.386364 MHz, which is obtained by multiplying the frequency of the clock signal S34 by “1575”, is generated by the VCO 43. It is output to the frequency dividing circuit 36.
Next, the clock signal S43 is frequency-divided sequentially by “½” times in the frequency dividing circuits 50, 51 and 52 of the frequency dividing circuit 36 shown in FIG. 1, and the frequency dividing ratio “2” is set. Based on the frequency division ratio instruction signal S62 shown, the clock signal S50 output from the frequency dividing circuit 50 is selected by the multiplexer 53 and output to the synchronization signal generating circuit 33 as the pixel clock signal S32. At this time, the frequency of the pixel clock signal S32 is 53.693182 MHz for the NTSC system.
[0036]
Then, in the synchronization signal generation circuit 33 shown in FIG. 4, the composite signal CSync and the color subcarrier reference signal FSC are generated based on the pixel clock signal S32 using the count value S37 stored in the count value storage memory 37. These are generated and output to a subsequent NTSC display.
In the subsequent display, an NTSC display signal is generated using the composite signal CSync and the color subcarrier reference signal FSC.
At this time, in the NTSC display, display is performed in units of subpixels.
[0037]
Second operation example
In this example, the operation of the synchronization signal generation device 31 when generating the PAL synchronization signal S33 using the system clock signal S63 having a frequency of 13.5 MHz shown in FIG. 3 will be described.
In this case, as shown in FIG. 3, a frequency division ratio instruction signal S60 indicating the frequency division ratio “161” is input to the frequency divider circuit 34, and a frequency division ratio instruction signal S61 indicating the frequency division ratio “1269” is input. A frequency division ratio instruction signal S62 that is input to the PLL circuit 35 and indicates the frequency division ratio “2” is input to the frequency divider circuit 36.
[0038]
Then, the system clock signal S63 is frequency-divided by the frequency dividing circuit 34 shown in FIG. 1, and a clock signal S34 is generated by multiplying the frequency of the system clock signal S63 by “1/161”. The clock signal S34 is generated by the PLL circuit 35. Is output.
Next, the clock signal S34 is subjected to PLL processing in the PLL circuit 35 shown in FIG. 1, and the clock signal S43 having a frequency 106.40632 MHz, which is obtained by multiplying the frequency of the clock signal S34 by “1269”, is generated by the VCO 43. It is output to the frequency dividing circuit 36.
Next, the clock signal S43 is frequency-divided sequentially by “½” times in the frequency dividing circuits 50, 51 and 52 of the frequency dividing circuit 36 shown in FIG. 1, and the frequency dividing ratio “2” is set. Based on the frequency division ratio instruction signal S62 shown, the clock signal S50 output from the frequency dividing circuit 50 is selected by the multiplexer 53 and output to the synchronization signal generating circuit 33 as the pixel clock signal S32. At this time, the frequency of the pixel clock signal S32 is 53.203416 MHz for the PAL system.
[0039]
Then, in the synchronization signal generation circuit 33 shown in FIG. 4, the composite signal CSync and the color subcarrier reference signal FSC are generated based on the pixel clock signal S32 using the count value S37 stored in the count value storage memory 37. These are generated and output to the PAL display at the subsequent stage.
In the subsequent display, a PAL display signal is generated using the composite signal CSync and the color subcarrier reference signal FSC.
At this time, in the PAL system display, display is performed in units of subpixels.
[0040]
Third operation example
In this example, the operation of the synchronization signal generation device 31 when generating the VESA synchronization signal S33 using the system clock signal S63 having a frequency of 13.5 MHz shown in FIG. 3 will be described.
In this case, as shown in FIG. 3, a frequency division ratio instruction signal S60 indicating a frequency division ratio “3” is input to the frequency dividing circuit 34, and a frequency division ratio instruction signal S61 indicating a frequency division ratio “1007” is generated. A frequency division ratio instruction signal S62 that is input to the PLL circuit 35 and indicates the frequency division ratio “4” is input to the frequency divider circuit 36.
[0041]
Then, the system clock signal S63 is frequency-divided by the frequency divider circuit 34 shown in FIG. 1, and a clock signal S34 is generated by multiplying the frequency of the system clock signal S63 by “1/3”, and the clock signal S34 is generated by the PLL circuit 35. Is output.
Next, the clock signal S34 is subjected to PLL processing by the PLL circuit 35 shown in FIG. It is output to the frequency dividing circuit 36.
Next, the clock signal S43 is frequency-divided sequentially by "1/2" times in the frequency dividing circuits 50, 51, 52 of the frequency dividing circuit 36 shown in FIG. Based on the frequency division ratio instruction signal S62 shown, the clock signal S50 output from the frequency divider circuit 51 is selected by the multiplexer 53 and output to the synchronization signal generation circuit 33 as the pixel clock signal S32. At this time, the frequency of the pixel clock signal S32 is 25.175000 MHz for the VESA method.
[0042]
Then, in the synchronization signal generation circuit 33 shown in FIG. 4, the horizontal blank signal HBlank, the horizontal synchronization signal HSync, the vertical, using the count value S37 stored in the count value storage memory 37 based on the pixel clock signal S32. A blank signal VBlank, a vertical synchronization signal VSync, and a field signal Field are generated and output to a VESA display at the subsequent stage.
In the subsequent display, a VESA display signal is generated by using the horizontal blank signal HBlank, the horizontal synchronization signal HSync, the vertical blank signal VBlank, the vertical synchronization signal VSync, and the field signal Field.
At this time, in the VESA display, display is performed in units of pixels.
[0043]
As described above, the pixel clock signal generator 32 can generate an arbitrary pixel clock signal S32 of the NTSC system, the PAL system, and the VESA system on the basis of the frequency division ratio instruction signals S60, S61, and S62.
Further, as can be seen from the item of “error” shown in FIGS. 2 and 3, it is possible to generate the pixel clock signal S32 having a highly accurate frequency with almost no error from a predetermined practical frequency.
That is, according to the pixel clock signal generator 32, the clock signal S34 generated by dividing the system clock signal S63 by the frequency divider 34 is supplied to the PLL circuit 35, so that it matches the characteristic (capability) of the PLL circuit 35. The clock signal S34 having a different frequency can be supplied to the PLL circuit 35, and the accuracy of the PLL processing in the PLL circuit 35 can be improved. Further, according to the pixel clock signal generator 32, the clock signal S43, which is the output of the PLL circuit 35, is further divided by the frequency divider 36 to generate the pixel clock signal S32, so that the PLL processing in the PLL circuit 35 is generated. The jitter can be removed by the frequency divider 36, and a highly accurate pixel clock signal S32 can be generated.
[0044]
Further, according to the synchronization signal generation device 31, an arbitrary synchronization signal S33 of the NTSC system, the PAL system, and the VESA system can be generated with high accuracy based on the frequency division ratio instruction signals S60, S61, and S62.
As a result, when an arbitrary pixel clock signal of the NTSC system, the PAL system, or the VESA system is generated, a single synchronization signal generation device 31 may be provided, and a reduction in size and price can be achieved.
[0045]
The present invention is not limited to the embodiment described above.
In the operation example of the above-described embodiment, the case where the system clock signal S63 having the frequency of 3.579545 MHz shown in FIG. 2 is used is exemplified. However, the frequency of the system clock signal S63 is arbitrary. As shown, a system clock signal S63 having a frequency of 4.43361875 MHz, 13.5 MHz, or 33.0 MHz may be used. In that case, as shown in FIGS. 2 and 3, it is necessary to change the frequency division ratio of the frequency division ratio instruction signals S60, S61, and S62.
Also, the VESA pixel clock signal S32 having various frequencies can be selected.
[0046]
【The invention's effect】
As described above, according to the pixel clock signal generation device of the present invention, various pixel clock signals corresponding to a plurality of display methods can be generated with high accuracy with a small and inexpensive configuration.
In addition, according to the synchronization signal generating device of the present invention, a synchronization signal for display display corresponding to a plurality of display methods can be generated with high accuracy with a small-scale and inexpensive configuration.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a synchronization signal generation device according to an embodiment of the present invention.
2 shows the frequency of the system clock signal shown in FIG. 1, the display method, the division ratio specified by the division ratio instruction signal, the frequency of the clock signal output from the VCO, and the pixel clock signal generation circuit 32. FIG. It is a figure which shows the relationship between the frequency of the pixel clock signal output, and the error of the said pixel clock signal and a practical value.
3 shows the frequency of the system clock signal shown in FIG. 1, the display method, the division ratio specified by the division ratio instruction signal, the frequency of the clock signal output from the VCO, and the pixel clock signal generation circuit 32. FIG. It is a figure which shows the relationship between the frequency of the pixel clock signal output, and the error of the said pixel clock signal and a practical value.
FIG. 4 is a configuration diagram of the synchronization signal generation circuit shown in FIG. 1;
FIG. 5 is a waveform diagram of the horizontal blank signal HBlank, the horizontal synchronization signal HSync, and the half horizontal synchronization signal HalfH shown in FIG. 4;
FIG. 5 is a waveform diagram of the vertical blank signal VBlank, the vertical synchronization signal VSync, and the composite synchronization signal CSync shown in FIG. 4;
7 is a waveform diagram of composite synchronization signal CSync, vertical synchronization signal VSync, and field signal Field shown in FIG. 4 in odd and even fields.
FIG. 8 is a block diagram of a conventional NTSC / PAL synchronous signal generator.
FIG. 9 is a block diagram of a conventional VESA synchronization signal generating apparatus.
FIG. 10 is a diagram showing a correspondence relationship between the frequency of the vertical synchronizing signal (V frequency), the frequency of the horizontal synchronizing signal (H frequency), the resolution, and the frequency of the pixel clock signal that can be selected by the VESA method. is there.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 31 ... Synchronous signal production | generation apparatus, 32 ... Pixel clock signal generation circuit, 33 ... Synchronization signal generation circuit, 34, 44, 50, 51, 37 ... Memory for count value storage, 52 ... Frequency division circuit, 40 ... Phase comparison circuit, 41 ... charge pump, 42 ... loop filter, 43 ... VCO, 53 ... multiplexer, 70 ... H counter, 71 ... V counter, 72 ... FSC generation circuit, 73 ... composite counter

Claims (10)

In a synchronization signal generator for generating a pixel clock signal used for generating a synchronization signal for display display,
A first frequency dividing circuit for generating a first clock signal by dividing the reference clock signal by a frequency dividing ratio indicated by the first frequency dividing ratio indicating signal;
A phase comparison circuit that performs phase comparison between the first clock signal and the second clock signal; a voltage-controlled oscillation circuit that generates a third clock signal that oscillates according to a result of the phase comparison; A PLL circuit having a second frequency dividing circuit that divides the clock signal by a frequency dividing ratio indicated by the second frequency dividing ratio instruction signal to generate the second clock signal;
A plurality of serially connected frequency dividing circuits for inputting the second clock signal to a first-stage frequency dividing circuit; and a plurality of clock signals respectively output from the plurality of frequency dividing circuits; A selection circuit that selects one of the signals based on a third division ratio instruction signal and outputs the selected clock signal as the pixel clock signal, and the frequency division indicated by the third division ratio instruction signal And a third frequency dividing circuit for generating the pixel clock signal by dividing the second clock signal by a ratio. A pixel clock signal used for display display for a computer by combining the frequency division ratios indicated by the first frequency division ratio instruction signal, the second frequency division ratio instruction signal, and the third frequency division ratio instruction signal. The pixel clock signal generation device according to claim 1, wherein one pixel clock signal is selected and generated from among pixel clock signals used for display display for television. By combining the frequency division ratios indicated by the first frequency division ratio instruction signal, the second frequency division ratio instruction signal, and the third frequency division ratio instruction signal, they are mutually used for display display for the computer. The pixel clock signal generation apparatus according to claim 1, wherein one pixel clock signal is selected and generated from among a plurality of pixel clock signals having different frequencies. The pixel clock signal generation device according to claim 1, wherein the reference clock signal is a clock signal generated inside a computer. In a synchronization signal generation device that generates a pixel clock signal by a pixel clock signal generation circuit and generates a synchronization signal for display display by the synchronization signal generation circuit using the pixel clock signal,
The pixel clock signal generation circuit includes:
A first frequency dividing circuit for generating a first clock signal by dividing the reference clock signal by a frequency dividing ratio indicated by the first frequency dividing ratio indicating signal;
A phase comparison circuit for performing phase comparison between the first clock signal and the second clock signal, a voltage controlled oscillation circuit for generating a third clock signal oscillated according to a result of the phase comparison, and the third clock signal A PLL circuit having a second frequency dividing circuit that divides the clock signal by a frequency dividing ratio indicated by the second frequency dividing instruction signal to generate the second clock signal;
A third frequency divider that divides the second clock signal by a frequency division ratio indicated by a third frequency division ratio instruction signal to generate the pixel clock signal;
The synchronization signal generation circuit includes:
A horizontal synchronization signal generating circuit that generates a horizontal synchronization signal and a horizontal blank signal based on the pixel clock signal;
A vertical synchronization signal generation circuit that generates a vertical synchronization signal and a vertical blank signal based on the pixel clock signal and the horizontal synchronization signal;
A synchronization signal generation device comprising: a composite synchronization signal generation circuit that generates a composite synchronization signal based on the horizontal synchronization signal and the vertical synchronization signal. The synchronization signal generation device according to claim 5 , further comprising: a color subcarrier signal generation circuit that generates a color subcarrier reference signal based on the horizontal synchronization signal and the horizontal blank signal . The third frequency divider circuit includes:
A plurality of frequency dividers connected in series for inputting the second clock signal to a first frequency divider;
A plurality of clock signals respectively output from the plurality of frequency dividing circuits are input, and one clock signal among the plurality of clock signals is selected based on the third frequency division ratio instruction signal, and the pixel clock is selected. The synchronization signal generation device according to claim 5 , further comprising: a selection circuit that outputs the signal. The pixel clock signal generation circuit includes:
A pixel clock signal used for display display for a computer by combining the frequency division ratios indicated by the first frequency division ratio instruction signal, the second frequency division ratio instruction signal, and the third frequency division ratio instruction signal. 6. The synchronization signal generation device according to claim 5 , wherein one of the pixel clock signals used for display display for television and a pixel clock signal used for display display is selected and generated. The pixel clock signal generation circuit includes:
By combining the frequency division ratios indicated by the first frequency division ratio instruction signal, the second frequency division ratio instruction signal, and the third frequency division ratio instruction signal, they are mutually used for display display for the computer. The synchronization signal generation device according to claim 5 , wherein one of the plurality of pixel clock signals having different frequencies is selected and generated. The synchronization signal generation device according to claim 5 , wherein the reference clock signal is a clock signal generated inside a computer.

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