JPH10153989A - Dot clock circuit - Google Patents

Dot clock circuit

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Publication number
JPH10153989A
JPH10153989A JP8312273A JP31227396A JPH10153989A JP H10153989 A JPH10153989 A JP H10153989A JP 8312273 A JP8312273 A JP 8312273A JP 31227396 A JP31227396 A JP 31227396A JP H10153989 A JPH10153989 A JP H10153989A
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Japan
Prior art keywords
means
image data
period
dot clock
frequency
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP8312273A
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Japanese (ja)
Inventor
Hisato Kokubo
寿人 小久保
Original Assignee
Nec Home Electron Ltd
日本電気ホームエレクトロニクス株式会社
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Application filed by Nec Home Electron Ltd, 日本電気ホームエレクトロニクス株式会社 filed Critical Nec Home Electron Ltd
Priority to JP8312273A priority Critical patent/JPH10153989A/en
Publication of JPH10153989A publication Critical patent/JPH10153989A/en
Application status is Pending legal-status Critical

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Abstract

PROBLEM TO BE SOLVED: To provide a dot clock circuit generating automatically a dot clock having a frequency being coincident with a dot period.
SOLUTION: Dot clocks CLK outputted from a PLL means 2 are counted and calculated by a calculating means 5 in a period in which a detecting signal 3X is made first a high level from a rising edge of a horizontal synchronizing signal H, and in a period in which the signal is made last a high level, difference between a display period and the result of calculation is repeatedly calculated after finish of calculation of one vertical scanning period, and the maximum value of a display period is obtained. After that, when a control means outputs a frequency division ratio to the PLL means 2, a programmable frequency divider 22 frequency-divides the dot clock CLK, horizontal resolution outputted by a discriminating means 4 is compared with a display period outputted by the calculating means 5, it is performed until horizontal resolution is equalized to a display period.
COPYRIGHT: (C)1998,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、ドットクロック回路に係り、特に、複数の同期信号に対応して画像データを表示するマトリクス表示装置等のドットクロック回路に関する。 The present invention relates to relates to a dot clock circuit, particularly to a dot clock circuit of a matrix display device for displaying the image data corresponding to a plurality of synchronizing signals.

【0002】 [0002]

【従来の技術】従来(図示せず)のドットクロック回路は、ホストシステムからの画像データの水平同期信号をPLL手段で分周して生成され、このPLL手段へ水平同期信号の何分の1のクロックを生成するかの情報をユーザが与えている。 Dot clock circuit of a conventional (not shown) is generating a horizontal synchronizing signal of the image data from the host system by dividing a PLL means, a fraction of the horizontal synchronizing signal to the PLL means It has given of how the information to generate a clock by the user.

【0003】また、予め設定されたホストシステムの信号タイミングを選択する方法では、表示できるホストシステムの信号タイミングに制限ができてしまう。 [0003] In the method of selecting the signal timing of the host system that is set in advance, you can restrict the signal timing of the host system available.

【0004】 [0004]

【発明が解決しようとする課題】従って、従来のドットクロック回路は、信号タイミングをユーザが手動で調整したり、特定なパターンが入力されていることをホストシステムに伝える必要があり、予め設定されたホストシステムの信号タイミングを選択する方法では、表示できるホストシステムの信号タイミングに制限ができてしまった。 [SUMMARY OF THE INVENTION Accordingly, the conventional dot clock circuit, to adjust the signal timing user manually, it is necessary to tell that a particular pattern is input to the host system, preset in the method of selecting the signal timing of the host system, it had made the limited signal timing of the host system available.

【0005】そこで、本発明の目的は、ドット周期に一致した周波数のドットクロックを自動的に生成するドットクロック回路を提供することにある。 An object of the present invention is to provide a dot clock circuit for automatically generating a dot clock of a frequency that matches the dot cycle.

【0006】 [0006]

【課題を解決するための手段】上述の課題を解決するために、本発明のドットクロック回路は、異なる水平同期信号及び垂直同期信号に基づいて入力された複数の画像データから解像度を判別する判別手段と、この判別手段で判別された画像データから黒以外の画像データの有無を検出する検出手段と、上記水平同期信号の周波数を逓倍するPLL手段と、上記画像データの水平走査期間の最初に入力される黒以外の画像データ及び、最後に入力される黒以外の画像データの期間が上記画像データのドットクロックの何周期かを演算する演算手段と、この演算手段で演算された周期値が上記判別手段で判別された解像度と等しくなるように上記PLL手段を制御する制御手段とで構成されたことを特徴とする。 Means for Solving the Problems] To solve the problems described above, the dot clock circuit of the present invention, determination for determining the resolution of a plurality of image data input based on the different horizontal and vertical synchronization signals means and a detecting means for detecting the presence or absence of the image data other than black from the image data discriminated by the discrimination means, a PLL means for multiplying a frequency of said horizontal synchronizing signal, the first horizontal scanning period of the image data image data and other than black to be input, a calculating means for the period of the image data other than black to be finally input to calculate what period of the dot clock of the image data, the calculated period value at the calculation means characterized in that it consists of a control means for controlling the PLL unit so as to be equal to the determined resolution by the discrimination means.

【0007】また、上述の課題を解決するために、本発明のドットクロック回路は、上記水平同期信号及び垂直同期信号の周波数が同じ画像データを受信した時のみ、 [0007] In order to solve the problems described above, the dot clock circuit of the present invention, only when the frequency of the horizontal synchronizing signal and a vertical synchronizing signal is received the same image data,
上記ドットクロックの周波数の低減制御を行わない上記制御手段で構成されたことを特徴とする。 Characterized in that it consists of the control means does not perform control of reducing the frequency of the dot clock.

【0008】さらに、上述の課題を解決するために、本発明のドットクロック回路は、上記異なる水平同期信号及び垂直同期信号に基づいて入力された複数の画像データの分周比を予め記憶した記憶手段で構成されたことを特徴とする。 Furthermore, in order to solve the problems described above, the dot clock circuit of the present invention, the different horizontal synchronizing signal and the division ratio previously stored stores the plurality of image data input on the basis of the vertical synchronization signal characterized in that it consists of means.

【0009】 [0009]

【発明の実施の形態】次に、本発明の一実施の形態によるドットクロック回路を図面を参照して説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Next, a dot clock circuit according to an embodiment of the present invention with reference to the drawings.

【0010】図1は、本発明の一実施の形態によるドットクロック回路のブロック構成図である。 [0010] Figure 1 is a block diagram of a dot clock circuit according to an embodiment of the present invention.

【0011】図2は、本発明の一実施の形態によるドットクロック回路の各部波形図である。 [0011] Figure 2 is a respective sections waveform diagram of dot clock circuit according to an embodiment of the present invention.

【0012】図3は、本発明の一実施の形態によるドットクロック回路の画像表示例(A),(B)である。 [0012] Figure 3 is an image display example of the dot clock circuit according to an embodiment of the present invention (A), a (B).

【0013】本発明の一実施の形態によるドットクロック回路は、図1に示すように、異なる水平同期信号H及び垂直同期信号Vに基づいて入力された複数の画像データ1から解像度を判別する判別手段4と、この判別手段4で判別された画像データ1から黒以外の画像データ1 [0013] dot clock circuit according to an embodiment of the present invention, as shown in FIG. 1, determines that determine the resolution of a plurality of image data 1 that has been input based on different horizontal synchronizing signal H and vertical synchronizing signal V a means 4, the image data 1 from the image data 1 is determined by the determining means 4 other than black
の有無を検出する検出手段3と、水平同期信号Hの周波数を逓倍するPLL手段2と、画像データ1の水平走査期間の最初に入力される黒以外の画像データ1及び、最後に入力される黒以外の画像データ1の期間が画像データ1のドットクロックCLKの何周期かを演算する演算手段5と、この演算手段5で演算された周期値が判別手段4で判別された解像度と等しくなるようにPLL手段2を制御する制御手段7と、異なる水平同期信号及び垂直同期信号で形成される複数の画像データの分周比を予め記憶した記憶手段とで構成される。 Detecting means 3 for detecting the presence or absence of, the PLL unit 2 for multiplying a frequency of the horizontal synchronizing signal H, the black non-image data 1 and the inputted first horizontal scanning period of the image data 1, is finally input and arithmetic means 5 for the period of the image data 1 except black calculates what period of the dot clock CLK of the image data 1, the calculated period value at the calculation unit 5 becomes equal to the determined resolution discrimination means 4 and a control unit 7 for controlling the PLL unit 2, a different horizontal synchronizing signal and the division ratio previously stored storage means of the plurality of image data to be formed by the vertical synchronizing signal as.

【0014】また、PLL手段2は、制御手段7からの出力信号を分周するプログラマブル分周器22と、このプログラマブル分周器22で分周された出力信号と水平同期信号Hとを位相比較するコンパレータ21と、この位相差の結果を出力するローパスフィルタ23と、このローパスフィルタ23から出力された位相差の結果を電圧変換して演算手段5にフィードバックするVCO24 Furthermore, PLL unit 2 includes a programmable frequency divider 22 for dividing an output signal from the control means 7, the phase comparison frequency-divided output signal with the programmable frequency divider 22 and the horizontal synchronizing signal H a comparator 21, a low-pass filter 23 for outputting a result of the phase difference and feeds back the result of the output phase difference from the low-pass filter 23 to the arithmetic unit 5 and the voltage converting VCO24
で構成される。 In constructed.

【0015】次に、本発明の一実施の形態によるドットクロック回路の動作を図面を参照して説明する。 [0015] Next, the operation of the dot clock circuit according to an embodiment of the present invention with reference to the drawings.

【0016】本発明の一実施の形態によるドットクロック回路の動作は、図1及び図2に示すように、入力画像データDが基準信号である黒レベルの電圧より高い電圧の時に検出信号3Xがハイレベルとなり、演算手段5が水平同期信号Hの立ち上がりエッジから検出信号3Xが最初にハイレベルになるまでの期間を、PLL手段2から出力されるドットクロックCLKをカウントして表示期間n1を演算し、同様に検出信号3Xが最後にハイレベルとなる期間を表示期間n2として演算手段5に演算させ、この演算が垂直走査期間の全ての水平走査期間で行われ、表示期間n1が最小に、かつ表示期間n2が最大となるように更新される。 [0016] Operation of the dot clock circuit according to an embodiment of the present invention, as shown in FIGS. 1 and 2, the detection signal 3X when higher than the voltage of the black level input image data D is reference signal voltage becomes high level, the operation detection signal 3X from the rising edge of the operation unit 5 is a horizontal synchronizing signal H and the period until the first high level, the display period n1 counts the dot clock CLK output from the PLL unit 2 was similarly detected signal 3X allowed is calculated in the calculation unit 5 finally as the display periods of the high-level period n2, the calculation is performed on all horizontal scanning period of the vertical scanning period, the display period n1 is the minimum, and display period n2 is updated so as to maximize.

【0017】その後、1垂直走査期間の演算を終了して表示期間n1と表示期間n2との差を表示期間n3として演算し、この表示期間n3の演算が次の垂直走査期間でも繰り返し行われ、表示期間n3の最大値を求めることができ、この表示期間n3の演算は水平同期信号の立ち下がりエッジを使用しても同様に行なえる。 [0017] Then, 1 calculates the difference between the display period n1 to end the operation of the vertical scanning period and the display period n2 as the display period n3, calculation of the display period n3 is repeated in the next vertical scanning period, it is possible to obtain the maximum value of the display period n3, operations performed in the same manner by using the falling edge of the horizontal synchronizing signal of the display period n3.

【0018】また、近年のマルチタスクマルチウインドウ環境が一般的な状況下では、図3の(A)に示すように、1垂直走査期間のいずれかに画面の左端または右端となる画像データDがあるため、表示期間n1の最小値が画面左端及び表示期間n2の最大値が画面右端の各々画像データDとなり、表示期間n3が画像データDの水平表示期間となる。 [0018] In recent years multitasking multi-window environment under general circumstances, as shown in (A) of FIG. 3, the image data D to be the left or right edge of the screen to one of the one vertical scanning period some reason, each image data D next to the maximum right end of the screen of the minimum left end of the screen and the display period n2 of the display period n1, the display period n3 a horizontal display period of the image data D.

【0019】従って、制御手段7が分周比データm1をPLL手段2のプログラマブル分周器22に出力すると、プログラマブル分周器22がドットクロックCLK [0019] Therefore, when the control unit 7 outputs a frequency division ratio data m1 to the programmable frequency divider 22 of the PLL unit 2, the programmable frequency divider 22 is a dot clock CLK
を1/(m1)分周し、制御手段7は、判別手段4の出力する水平解像度h1と演算手段5の出力する表示期間n3との比較を行い、水平解像度h1が画像データDを等倍表示または拡大表示した時の水平解像度で、例えば水平1024/垂直768の解像度を持つ画像データD The 1 / (m1) divides, the control unit 7 performs a comparison between the horizontal resolution h1 for outputting the discrimination means 4 and the display period n3 output by the arithmetic means 5, magnification horizontal resolution h1 is the image data D image data D having a horizontal resolution when the display view or enlarged, for example, a resolution of horizontal 1024 / vertical 768
を等倍表示するのであれば1024であり、水平800 If for magnification display is 1024, horizontal 800
/垂直600の解像度を持つ画像データDを1.25倍表示するのであれば800×1.25=1000で10 / Images if the data D of displaying 1.25 800 × 1.25 = 1000 having a resolution of 600 vertical at 10
00となり、制御手段7がh1<n3の時に分周比m1 00, and the frequency division ratio at the time of the control unit 7 is h1 <n3 m1
を小さくし、h1>n3の時に分周比m1を大きくさせて水平解像度h1と表示期間n3が等しくなるまで続ける。 The small, h1> horizontal resolution h1 and display period n3 by increasing the frequency division ratio m1 when n3 is continued until it equals.

【0020】さらに、記憶手段6は、不揮発性メモリまたはバッテリーバックアップされたメモリで構成され、 Furthermore, the storage unit 6 is composed of a nonvolatile memory or a battery backed up memory,
各種の水平同期信号H及び垂直同期信号Vの周波数に対応する分周比が格納され、図3の(A)に示すように、 Dividing ratio corresponding to the frequency of the various horizontal sync signal H and vertical synchronizing signal V is stored, as shown in FIG. 3 (A),
画面左端及び右端に画像データDのある状態と、図3の(B)に示すように、画面左端または右端に画像データDのない画面状態の発生が考えられるため、判別手段4 A state in which the image data D on the screen left and right edges, as shown in FIG. 3 (B), since the generation of free screen state of the image data D to the screen left or right edge is considered, the determination means 4
で判別された水平同期信号H及び垂直同期信号Vの周波数に対応する分周比m2を制御手段7が記憶手段6から読み出し、かつ分周比m2を小さくする制御は行わずに分周比m2の初期値を水平解像度h1として分周比m2 In the determined horizontal synchronizing signal H and a read from the frequency division ratio m2 control means 7 is storage means 6 which corresponds to the frequency of the vertical synchronizing signal V, and the frequency division ratio division ratio control is not performed to reduce the m2 m2 division ratio of the initial value as the horizontal resolution h1 m @ 2
へ加算操作のみで容易に実現できる。 It can be easily realized only by the addition operation to.

【0021】 [0021]

【発明の効果】以上説明したように、本発明のドットクロック回路によれば、入力した画像データの仕様に合わせて自動的にドットクロックを生成するため、ユーザが行なうドットクロック再生の調整処理を削減し、かつ安価に実現できる効果がある。 As described in the foregoing, according to the dot clock circuit of the present invention, in order to automatically generate the dot clock according to the specifications of the input image data, the process of adjusting the dot clock reproducing the user performs reduction was, and there is a low cost can be effectively.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施の形態によるドットクロック回路のブロック構成図である。 1 is a block diagram of a dot clock circuit according to an embodiment of the present invention.

【図2】本発明の一実施の形態によるドットクロック回路の各部波形図である。 2 is a respective sections waveform diagram of dot clock circuit according to an embodiment of the present invention.

【図3】本発明の一実施の形態によるドットクロック回路の画像表示例(A),(B)である。 Image display example of the dot clock circuit according to an embodiment of the present invention; FIG (A), a (B).

【符号の説明】 DESCRIPTION OF SYMBOLS

1,D 画像データ 2 PLL手段 3 検出手段 4 判別手段 5 演算手段 6 記憶手段 7 制御手段 21 コンパレータ 22 プログラマブル分周器 23 ローパスフィルタ 24 VCO 3X 検出信号 H 水平同期信号 V 垂直同期信号 CLK ドットクロック 1, D image data 2 PLL unit 3 detecting means 4 judging means 5 calculating means 6 storage means 7 the control means 21 the comparator 22 programmable divider 23 the low-pass filter 24 VCO 3X detection signal H horizontal synchronizing signal V vertical synchronizing signal CLK dot clock

Claims (3)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 異なる水平同期信号及び垂直同期信号に基づいて入力された複数の画像データから解像度を判別する判別手段と、この判別手段で判別された画像データから黒以外の画像データの有無を検出する検出手段と、 From 1. A different horizontal synchronizing signal and a plurality of image data input based on the vertical synchronizing signal and a determining means for determining the resolution, the presence or absence of the image data other than black from the image data discriminated by the discrimination means and detection means to be detected,
    上記水平同期信号の周波数を逓倍するPLL手段と、上記画像データの水平走査期間の最初に入力される黒以外の画像データ及び、最後に入力される黒以外の画像データの期間が上記画像データのドットクロックの何周期かを演算する演算手段と、この演算手段で演算された周期値が上記判別手段で判別された解像度と等しくなるように上記PLL手段を制御する制御手段とで構成されたことを特徴とするドットクロック回路。 A PLL means for multiplying a frequency of said horizontal synchronizing signal, the first image data and other than black to be input to the period of the image data other than black to be the last to the input of the horizontal scanning period of the image data of the image data calculating means for calculating what period of the dot clock, the calculated period value at the calculation means is constituted by a control means for controlling the PLL unit so as to be equal to the determined resolution by the discrimination means dot clock circuit according to claim.
  2. 【請求項2】 上記水平同期信号及び垂直同期信号の周波数が同じ画像データを受信した時のみ、上記ドットクロックの周波数の低減制御を行わない上記制御手段で構成されたことを特徴とする請求項1記載のドットクロック回路。 2. A method according to claim, wherein said horizontal synchronizing signal and only when the frequency of the vertical synchronization signal has been received the same image data, which is constituted by the control means does not perform the reduction control of the frequency of the dot clock dot clock circuit of 1, wherein the.
  3. 【請求項3】 上記異なる水平同期信号及び垂直同期信号に基づいて入力された複数の画像データの分周比を予め記憶した記憶手段で構成されたことを特徴とする請求項1記載のドットクロック回路。 3. A dot clock of the different horizontal synchronizing signal and according to claim 1, characterized in that it is constituted by a pre-stored memory means the frequency division ratio of the plurality of image data input on the basis of the vertical synchronization signal circuit.
JP8312273A 1996-11-22 1996-11-22 Dot clock circuit Pending JPH10153989A (en)

Priority Applications (1)

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