GB2085257A - Apparatus and methods for varying the format of a raster scan display - Google Patents

Abstract

The invention is concerned with varying the widths and heights of characters in a raster scan display. Width is controlled by varying the pixel frequency but problems occur unless the pixel frequency is an integral multiple of the line frequency. Variable pixel frequencies which satisfy this condition are provided by a voltage controlled oscillator 14 which forms part of a phase- locked loop including variable dividers 15 and 18 and a phase-sensitive detector 12 which compares the output of the divider 15 with a line frequency determined by an oscillator 10. Height is controlled by varying the number of times each line of a number of lines making up a character is read out in each display of that character. <IMAGE>

Description

SPECIFICATION Apparatus and methods for varying the format of a raster scan display This present invention relates to apparatus for varying the widths and heights of items, particularly characters, in an electronic raster scan display.

In displaying information using the raster scan technique (for example on a TV monitor) the characters displayed are represented by a series of horizontal lines. For digital character generation it is convenient to generate these lines using a sequence of adjacent equal length horizontal dots, referred to as picture elements (pixels). The horizontal picture resolution is then determined by the width of these pixels. To change the width of a character, either the pixel width can be changed or the positions of pixels selected within a matrix making up the character might be changed. If character width is to be variable it is preferable to change the pixel width since varying the dots selected in the character matrix changes the shape of the characters, this being especially noticeable with characters having diagonal lines.

In known raster scan displays the highestfrequen- cy which is usually employed is the pixel frequency (that is the reciprocal of the period of the pixel) and this frequency is determined by a crystal oscillator.

Characters are all of the same width and therefore a character frequency is derived for use in controlling the display by a divider circuit which divides the pixel frequency by the number of pixels across the width of each character plus, for example, two pixels to space the characters from each other.

Having decided upon the number of the characters to appear in a line a further divider circuit is used to derive the line frequency from the pixel frequency or the character frequency. The line frequency is fixed for any given display standard, for example under British standards the line frequency has a period of 64 microseconds. Since this frequency is fixed the two dividers determining the character and line frequencies from the pixel frequency must be such that the apprcpriate line frequency is achieved.

Further division of the line frequency provides the frame frequency which for example in British standards has a period of 20 milliseconds.

In order to prevent various spurious items such as horizontally progressing bars or the effects of beat signals appearing on the display it is necessary to lock the pixel frequency to the line frequency, but this is a problem where it is required to vary character width, and particularly where a large number of different character widths are required.

According to the present invention there is provided apparatus for controlling the width of items in a raster scan display, comprising referencefrequency means for generating an oscillatory signal determining the line frequency of a raster scan display, a variable-frequency pixel oscillator for determining the duration of picture elements in the display, the oscillator having a terminal for the application of a control signal for controlling its oscillation frequency, a frequency-divider circuit having a variable division ratio, and a phasesensitive detector with inputs coupled to receive respective input signals from the referencefrequency means and the frequency-divider circuit and with output coupled to the oscillator by way of a filter to provide the said control signal, the phasesensitive detector, the oscillator, the filter and the frequency-divider circuit forming a phase-locked loop.

The items in the raster display may, for example, be characters generated using a character generator integrated circuit but there may also be display items generated from information held in a store in which each location corresponds to a respective pixel in the display.

Incorporating the frequency-divider circuit in a phase-locked loop which also includes the pixel oscillator has the advantage that the line frequency and pixel frequency are locked as required. Additionally the phases of the line and character signals are locked in a fixed relationship with reduced likelihood of character distortion.

A major advantage of the present invention is that a large number of character widths, usually as many as are required, can be provided by using a programmable divider as the frequency-divider circuit.

Such programmable dividers are commercially available in integrated circuit form. Meansforsup- plying digital signals to the programmable divider as required are then included in apparatus according to the invention to control the divider and allow varying character widths to be selected. Integrated circuit programmable dividers have outputs at which both line and frame frequencies appear.

The filter is provided in order to remove high frequency noise from the signal applied to control the oscillator frequency. The frequency response of the filter controls the locking speed and response of the phase-locked loop.

Apparatus according to the invention may be used with raster scan display apparatus having a rowcounter circuit which is coupled to receive the line frequency and which provides a signal controlling either a character generator or read-out from a memory storing information relating to characters to be displayed. For example, the first output from the row counter causes the character generator to output signals corresponding to pixels required in the top, or first row of a character. The second output from the row counter then causes pixels corresponding to the second row of a character to be read out.

Where such a row counter is provided the height of characters may be controlled by coupling heightcontrol means between the row counter and the character generator or memory, the height control means causing each row of the character to be displayed to be repeated a number of times depending on the required character height. The height control means may then be connected to a control which allows automatic or manual control of the number of repetitions of each character row.

Certain embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of apparatus according to the invention, and Figure 2 is a block diagram of an addition to the circuit of Figure 1 which allows the height of characters to be varied.

In Figure 1 a crystal oscillator 10 is coupled to a divider circuit 11 such that the frequency of the output from the divider 11 is the line frequency for a raster scan display. This signal is applied to conventional laster scan display apparatus in which the usual signals are derived and used for controlling the display (such as line and frame synchronising pulses and frame frequency).

The output of the divider 11 is also applied to one input of a phase-sensitive detector 12, the output of which is coupled by way of a low-pass filter 13 to a voltage controlled oscillator 14. The pixel frequency which is applied to the raster scan circuits is the output from the voltage controlled oscillator (VCO) 14 and this output is also fed back to the other input of the phase-sensitive detector 12 by means of programmable divider circuits 15 and 18 to complete a phase-locked loop. In this embodiment, the divider circuit 15 is part of a cathod ray tube controller (CRTC) integrated circuit 16. The divider circuit 18 derives the character frequency.

Information, discussed in more detail below, is supplied by a width control circuit 17 to the divider circuits 15 and 18 of the CRTC 16 to set division ratios as required to achieve a pixel frequency ieading to a desired character width.

In operation the phase-sensitive detector provides zero output only when the frequencies of its inputs are equal and they are in phase. As a result the output frequency of the VCO 14 is equal to an integral multiple of the line frequency and this multiple depends on the division carried out by the divider circuits 15 and 18. Thus by changing the divisor the output frequency of the VCO 14 is in effect multiplied by the divisor. Theoretically an infinite number of pixel frequencies and therefore pixel widths are available by changing the divisor.

In implementing the circuit of Figure 1 the CRTC 16 may be a Motorola integrated circuit type No. MC 6845 and the phase-locked loop may comprise a Motorola integrated circuit type No. MC 4044 as the phase detector and a type No. MC 4024 as the voltage controlled oscillator. The design of the filter 13 is according to well established techniques such as are described in the data sheet for the MC 4044 and in the Motorola applications note AN-535 "Phase locked loop design fundamentals". Typically, the loop has a natural frequency often thousand radians per second with a damping factor of 0.8, and the division ratio in the loop is variable between 256 and 704.

The Motorola MC 6845 data sheet appearing in the Motorola microcomputer components data book 1979 (pages 1-193 to 1-211) outlines a known typical raster scan display circuit which includes the MC 6845 circuit. The MC 6845 is also discussed in "Simplify video-display design by using a versatile IC controller", Electronic Design 13, June 1979 (pages 94 - 102), and raster scan displays are also described in "Mate microprocessors with CRT displays", Electronic Design 19, September 1977 (pages 68 - 74). The MC 6845 also contains counters for blanking, synchronising and other pulses and registers to program these counters. Registers 19 and 20 control the divider circuits 15 and 18 respectively and are, in operation, supplied with 8-bit words determining the divisors, and supplied from the width control circuit 17.Conveniently, such a width control may form part of a microcomputer which is itself part of the raster scan display apparatus.

In an alternative arrangementwhich provides finer control of the character width, the divider circuit 18 is not part of the phase-locked loop, the output of the VCO 14 being supplied in parallel to the divider circuits 15 and 18, and the character frequency being, as before, derived by the divider circuit 18. In such an arrangement the divider circuit 15 is such that in operation it divides from the pixel frequency to a frequency (near or equal to the line frequency) suitable as an input to the phase sensitive detector 12.

In order to explain how the height of characters in the display is controlled it is first necessary to mention brieflythe usual scheme for character generation.

A memory 20 in Figure 2 is supplied, by way of connection 31, with words whose bits indicate characters to be displayed. Loading the memory 20 may be carried out in a known way, for example from a microprocessor controlling the content of the display. When the display of a selected character is to take place the appropriate code is applied by means of connections 21 to a character generator circuit 22 which is a commercially available integrated circuit. As has been mentioned each character to be displayed is made up of groups of adjacent pixels in successive lines of the display. Thus the character generator also receives an input specifying which row of the character is to be read out from the character generator. This input is applied from a row counter 24 by way of a selector 25 and connections 28 and 29.Read-out is by means of connections 26 to a shift register 27 from which the appropriate signals are clocked by the pixel frequency. The output of the divider circuit 18 at the character frequency is used to load the register 27 with new data from the character generator 22 at the end of each row of a character Since in this type of display each pixel is either illuminated or not the output from the shift register 27 can be regarded as equivalent to the video signal of the display. The row counter 24 counts up to the number of pixels making up the height of each character plus an appropriate line spacing before returning to zero.

In the operation of the arrangement of Figure 2 - when a new line of characters is to be displayed an output signal from the first output of a row counter 24 is applied by way of the selector 25 to the first row input of the character generator 22. At the same time a character line counter 30 which counts the number of lines of characters and is connected at the output of the row counter 24 addresses the memory 20 and together with an address transferred from suitable stages of the counter 15, which represents the position of a required character in a line, selects a memory location which holds the code of the character required. This code is supplied to the character generator 22 to indicate to the generator which character is to be displayed. The appropriate signals then appear in the shift register 27 where they are clocked out by the pixel frequency.When the next line of the display appears the row counter 24 provides an output on its seond output connection by way of the selector 25 to the generator 22 and thus the second row of pixels making up a character appear in the shift register 27 (appropriate addresses also being supplied by the counters 15 and 30 to provide the appropriate code from the memory 20 to the generator 22).

The selector 25 allows the signals applied through the connections 28 to the character generator 22 to be different from those at the output of the row counter 24 passing by way of the connections 29. For a "normal" or "unit" height character the selector 25 has a one to one correspondence between its inputs and outputs but for other character heights the correspondence is varied. For example, if it is required to double the height of the character, this can be achived by one repetition of each character row. Conveniently in a binary system such repetition is obtained by omitting the least significant output from the row counter and the selector 25 can be arranged to operate in this way when enabled, for example by a manual control.In such an arrangement the second output from the counter 24 is connected to the first character generator input, the third character output is connected to the second character generator input and so on. A similar arrangement in which the two least significant outputs from the counter 24 are omitted allows multiplication of a character height by four but for most other multiplying factors a simple way of providing the selector 25 is to use a programmable read only memory (PROM) containing a look-up table in which the outputs of the row counter 24 form, together with a character height selection bit, addresses in the table. Appropriate outputs from the PROM are then applied to the character generator.

For example for multiplication by three the first three row counter outputs provide an input on the first character generator input, the second three row counter outputs provide an input on the second character input and soon.

It will be appararent that the invention can be put into practice in many ways in addition to the ways specifically described above. For example, the invention can be applied to raster scan graphics where items to be displayed are held in a memory store which has a location for each pixel making up a display, this storage taking the place of the character generator 22 of Figure 2. Although the bits making up the display are held in one large store, this store is organised into "characters" so that it can be conveniently read out. Thus a character frequency similar to that derived in Figure 1 is derived for such a display and hence the circuit of Figure 1 can be used to control pixel width. In addition the memory is organised so that the "characters" are read out vertically in a similar way to that shown in Figure 2 and thus character height can also be controlled in the way described above. Since variable format visual display units (VDUs) are a form of raster scan graphics in which various formats of character are available, the invention can also be applied to such displays. The invention is also useful with any other form of display in which pixel frequency has to be locked to a line frequency.

Claims (6)

1. Apparatus for controlling the width of items in a raster scan display, comprising referencefrequency means for generating an oscillatory signal determining the line frequency of a raster scan display, a variable-frequency pixel oscillator for determining the duration of picture elements in the display, the oscillator having a terminal for the application of a control signal for controlling its oscillation frequency, a frequency-divider circuit having a variable division ratio, and a phasesensitive detector with inputs coupled to receive respective input signals from the reference frequency means and the frequency-divider circuit and with output coupled to the oscillator by way of a filter to provide the said control signal, the phase-sensitive detector, the oscillator, the filter and the frequencydivider circuit forming a phase-locked loop.

2. Apparatus to Claim 1 wherein the frequencydivider circuit is divided into first and second portions in cascade, the output signal of the first portion being at a character frequency for controlling the instants in each scan line when portions of characters are to be displayed, and the frequency of the output signal of the second portion being equal to the line frequency.

3. Apparatus according to Claim 1 wherein the output signal of the frequency-divider circuit is equal to the line frequency, and a further frequency-divider circuit having a variable division ratio is provided, the further frequency-divider circuit being connected to the output of the said oscillator, but not being connected in the phase-locked loop, and having an output signal at the character frequency for controlling the instants in each scan line when portions of characters are to be displayed.

4. Raster scan display apparatus including apparatus according to any preceding claim, a character generator or a memory circuit storing information relating to character to be displayed, a row counter coupled to address the character generator or the memory to read out those portions of characters to be displayed which are to appear in a line of the raster scan display, and character-height control means coupled to the row counter to determine the number of times each said character portion is displayed in each display of a character.

5. Apparatus for controlling the width of items in a raster scan display substantially as herein before described and as shown in Figure 1 of the accompanying drawings.

6. Apparatus for controlling the width of items in a raster scan display substantially as hereinbefore described and as shown in Figures 1 and 2 of the accompanying drawings.