JPH0541813A - Clock signal generating circuit - Google Patents

Abstract

PURPOSE:To provide a clock signal generating circuit in which a dot clock used to control a system with a simple digital circuit without employing a complicated analog circuit technology and making the system expensive in the system superimposing a picture generated from the graphic system onto a video signal. CONSTITUTION:The circuit generating a clock signal 7 by frequency-dividing a reference clock signal 4 starts the generation of the clock signal 7 by using an external control signal 11 as a trigger and is provided with another frequency divider circuit 3 starting the generation of the clock signal 7 by using an external control signal 11 and frequency-dividing the generated clock signal 7, and when the frequency divider circuit 3 generates the clocks by a prescribed clock number, the application of the reference clock 4 to the clock frequency divider circuit 2 is controlled to stop the clock output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generating circuit for controlling generation of a clock signal based on a control signal, and more particularly to a video source (for example, a video output from a laser disk or a VTR). Clock signal generation to generate a dot clock signal (clock corresponding to one pixel unit) in a system that attempts to superimpose an image generated by a graphics system controlled by a microprocessor or a display controller etc. Regarding the circuit.

[0002]

2. Description of the Related Art When a system for superimposing an image generated by a graphic system on a video signal output from a laser disk or VTR is to be constructed, a graphic system is added to the video signal generated from the laser disk. It is necessary to synchronize the image signals generated by. Conventionally, when attempting to realize such a system, the dot clock signal, which is the basic clock for image generation in the graphic system, extracts the horizontal synchronizing signal of the video signal (composite signal),
From this horizontal synchronizing signal, a clock signal synchronized with the video signal is obtained by generating it by a PLL (phase locked loop) circuit using a VCO (voltage controlled oscillator).

[0003]

However, in the method using the PLL as in the above-mentioned conventional example, analog circuits such as phase comparison, low-pass filter, and VCO control are required, and the system becomes complicated. Moreover, not only does it require advanced technology, but it also raises the price of the system. Therefore, the present invention solves such a problem, and an object of the present invention is to provide a graphic system that realizes a superimposing method with a simple digital system without causing the system to become complicated or expensive. It is an object to provide a clock signal generation circuit that can be realized by a circuit.

[0004]

The clock signal generating circuit of the present invention is a clock signal generating circuit for generating a clock signal based on a control signal input from the outside,
An oscillator circuit that oscillates at a reference cycle, a first divider circuit that divides the oscillation output of the oscillator circuit to generate a clock signal, and a clock signal that is output from the first divider circuit. A second frequency dividing circuit, and gate means for controlling the supply of the oscillation output of the oscillation circuit to the first frequency dividing circuit in response to the control signal output from the second frequency dividing circuit.
A pulse signal generating circuit that generates a pulse signal synchronized with an oscillation output of the oscillation circuit according to a control signal input from the outside, wherein the first frequency dividing circuit and the second frequency dividing circuit include: The control signal output which is initialized by the pulse signal generated by the pulse signal generating circuit and is output from the second frequency dividing circuit to the gate means is predetermined after the second frequency dividing circuit is initialized. During the period until the number of clocks is divided, a level for supplying the oscillation output of the oscillation circuit to the first frequency divider is output, and the second frequency divider divides the predetermined number of clocks. After that, a level for stopping the supply of the oscillation output of the oscillation circuit to the first frequency dividing circuit is output.

[0005]

FIG. 1 is a block diagram showing an embodiment of the present invention. An oscillating circuit 1 oscillates at a predetermined cycle to generate a reference clock of the clock signal generating circuit of the present invention. Reference numeral 4 is a reference clock signal. Reference numeral 2 is a first frequency dividing circuit, which is supplied with a clock signal 6 from a transmitting circuit 1 through a logical OR gate 5 and generates a clock signal 7 for dividing the frequency and supplying the frequency to the outside. There is. Reference numeral 8 is a clock signal output terminal. A second frequency dividing circuit 3 divides the frequency of the clock signal 7 generated by the second frequency dividing circuit. Three
The clock supply control signal 9 to the OR gate 5 is output from the frequency divider circuit. In the clock supply control signal 9, the reference clock signal 4 is supplied to the frequency dividing circuit 2 for 5 OR gates from the initialization of the frequency dividing circuit 3 to the frequency division of a predetermined number of clocks. A low level is output as supplied. After that, when the frequency dividing circuit 3 divides a predetermined number of clocks, the clock supply control signal 9 has an O
Reference clock signal 4 to frequency divider 3 for R gate
High level is output so as to stop the supply of. 1
Reference numeral 2 is a flip-flop circuit, 13 is a logical NOR gate, and these two flip-flop circuits and the NOR gate constitute a pulse generation circuit. Reference numeral 11 is an input terminal for a control signal from the outside. The reference clock signal of 4 is input to the clock input of the flip-flop circuit 12, and the rising edge of the input signal to the control input terminal of 11 is detected to output the reference clock 4 from the NOR gate of 13.
A pulse for one cycle of the reference clock signal synchronized with is output. Pulse signal 1 output from NOR gate 13
0 is input to the reset inputs of the frequency dividing circuits 2 and 3.

Next, the operation of the embodiment circuit of FIG. 1 will be described with reference to FIGS.
Also, description will be made with reference to the timing chart of FIG.

FIG. 3 is a timing chart showing the operation when the frequency dividing circuit 2 and the frequency dividing circuit 3 are reset (initialized) by an input to the external control input terminal 11 of the clock signal generating circuit of FIG. is there. (A) is a reference clock signal, which is the signal 4 in FIG. When a signal such as (b) is input to the external control input terminal 11 of FIG. 1, a pulse for one cycle of the reference clock signal synchronized with the reference clock signal such as (c) is output to 10 of FIG. To be done. The frequency divider circuits 2 and 3 in FIG. 1 are reset by this pulse signal.
(F) is the clock supply control signal 9 of FIG. 1, and when the frequency dividing circuit 3 is reset, a low level is output. (G) is the signal 6 in FIG. 1 and is the clock supply control signal 9
Becomes low level, a clock is supplied to the frequency dividing circuit 2 as shown in the figure. 1D shows the output of the frequency dividing circuit 2 in FIG. 1 and the signal 7 in FIG. 1, and FIG. 7E shows the frequency dividing state of the frequency dividing circuit 3 in FIG. In this way, after the reset is applied by the pulse of (C), the clock of (g) is supplied to 6 of FIG. 1 and the frequency dividing circuit 2 divides this signal to generate the clock signal of (d). Is generated, and the frequency dividing circuit 3 divides the frequency to produce a frequency division state as shown in (e). It is assumed that the clock signal generation circuit of this embodiment divides the reference clock 4 output from the oscillation circuit by 4 to generate the clock signal 7 to the outside.

FIG. 4 is a timing chart showing the operation when the frequency dividing circuit 3 of FIG. 1 divides the frequency by a predetermined number of clocks N. (H) is the reference clock signal 4 of FIG. 1, (i)
Is a clock signal 7, which is the output of the frequency divider circuit 2 in FIG.
1 (j) is the frequency division state of the frequency divider circuit 3 in FIG. 1, (k) is the clock supply control signal 9 in FIG. 1, and (l) is the clock signal to the frequency divider circuit 2 in FIG. As shown in FIGS. 4 (j) and 4 (k), the frequency dividing circuit 3 of FIG. 1 outputs a high level to the clock supply control signal 9 of FIG. When a high level is output to the clock supply control signal 9, the clock signal 6 to the frequency dividing circuit 2 in FIG. 1 stops as shown in (l).
Since the clock signal 6 is stopped, the frequency dividing circuit 2 of FIG.
And the frequency dividing circuit 3 stops the frequency division.

FIG. 5 is a timing chart showing the operation when a control signal of a certain fixed cycle is input to the external control signal input 11 of the clock signal generation circuit of FIG. A signal like (m) in FIG. 5 is used as an input to the external control signal input 11 of the clock signal generating circuit in FIG. 1, and the frequency dividing circuit 3 performs a predetermined period during a period shorter than one cycle of the external control signal in (m). Assuming that N is set to divide the number N of clocks of, the clock supply control signal 9 output from the frequency dividing circuit 3 becomes low level from the rising edge of the external control signal as shown in (o). Before the next rising edge of the external control signal arrives, the frequency dividing circuit 3 divides the frequency by a predetermined number of clocks N, and the level becomes high again. (N) is the clock signal 7 output from the frequency dividing circuit 2 in FIG. 1, and as shown in the figure, the clock signal starts to be output from the rising edge of the external control signal (m) and a predetermined number N of clocks are generated. When the output is completed, the output of the clock is once stopped and the output of the clock is restarted at the next rising edge of the external control signal.

FIG. 2 is a block diagram showing an example in which the circuit of the embodiment shown in FIG. 1 is applied to a graphic system for superimposing. FIG. 2 is an example of a system for superimposing an image generated by a graphics system on an externally supplied video signal. A video signal input terminal 20 is supplied with a video signal (composite signal) from a laser disk or the like. Reference numeral 21 denotes a sync separation circuit, which separates the horizontal sync signal and the vertical sync signal from the video signal input from 20. Reference numeral 24 is a clock signal generation circuit that is an embodiment of the present invention. The horizontal sync signal 22 and the vertical sync signal 23 separated by the sync separation circuit 21 are supplied to the graphic system 26 as a sync signal for image generation. Further, 22 horizontal synchronizing signals are also supplied to the external control signal input terminal (terminal corresponding to 11 in FIG. 1) of the 24 clock signal generating circuit. 24 clock signal generating circuits generate clocks of a predetermined number N of clocks from the rising edge of the horizontal synchronizing signal 22 and output the clocks to 25. It is assumed that the frequency dividing circuit (frequency dividing circuit 3 in FIG. 1) in 24 clock signal generating circuits is set so as to generate a predetermined number N of clocks in a period shorter than one cycle of the horizontal synchronizing signal. Then, the relationship between the horizontal synchronizing signal and the clock signal 25 generated by the clock generation circuit 24 is as shown in (m) and (n) of FIG. This clock signal is supplied to the 26 graphic systems as a dot clock signal which is a clock signal corresponding to one pixel unit. Again 2
2 horizontal sync signals and 23 vertical sync signals are 32 C
It is supplied to the RT display as a synchronizing signal for display. Reference numeral 29 is an RGB signal which is an image signal generated by the graphic system. 27 is composite / R
It is a GB converter and converts a video signal (composite signal) input from 20 into an RGB signal 31.
28 is an RG converted from the video signal input from 20.
An RGB switch circuit that switches between the B signal 31 and the RGB signal 29 generated by the graphic system 26. The RGB switch control signal 30 supplied from the graphic system 26 switches between the two RGB signals to the CRT display 32. The signal 33 is output. With such a configuration, the horizontal and vertical sync signals are supplied to the graphic system 26,
Since the clock signal synchronized with the horizontal synchronizing signal output from the clock signal generating circuit according to the embodiment of the present invention is supplied, the graphic system 26 can generate an image synchronized with the video signal. By switching the image generated by the graphic system, the image of the graphic system can be superimposed on the video signal. The phase relationship between the horizontal synchronizing signal 22 and the dot clock signal 25 output from the clock generation circuit 24 is deviated within the range of one cycle of the oscillation output (reference clock) of the oscillation circuit in the clock generation circuit, resulting in a display screen. The image appears as "shift" or "blurring" of the image generated by the graphic system with respect to the video signal above. However, if the configuration uses an oscillation circuit with a frequency of about 21 MHz, "shift" on the display screen will occur.
Alternatively, the “blurring” is slight, and there is no particular problem.

[0011]

As described above, by using the clock signal generating circuit according to the present invention, a graphic system that realizes superimposing becomes more complicated or more expensive than a normal graphic system. It has an effect that it can be realized by a simple digital circuit without incurring the problem and without using the advanced analog circuit technology which has been used conventionally.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a graphic system using the clock generation circuit according to the embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of the clock signal generation circuit of FIG.

FIG. 4 is a timing chart showing the operation of the clock signal generation circuit of FIG.

5 is a timing chart showing the operation of the clock signal generation circuit of FIG.

[Explanation of symbols]

 1 oscillation circuit 2 frequency dividing circuit 3 frequency dividing circuit 4 reference clock signal 5 logical OR gate 6 clock signal 7 frequency dividing clock signal 8 clock signal output terminal 9 clock supply control signal 10 frequency dividing circuit reset signal 11 external control signal 12 flip-flop Circuit 13 Logic NOR gate 20 Video signal input terminal 21 Sync separation circuit 22 Horizontal sync signal 23 Vertical sync signal 24 Clock signal generation circuit 25 Dot clock signal 26 Graphic system 27 Composite / RGB converter 28 RGB switch circuit 29 RGB signal 30 RGB switch Control signal 31 RGB signal 32 CRT display 33 RGB signal

Claims (1)

[Claims] 1. Based on a control signal input from the outside,
In a clock signal generation circuit for generating a clock signal, an oscillation circuit that oscillates at a reference cycle, a first frequency division circuit that divides an oscillation output of the oscillation circuit to generate a clock signal, and the first frequency division circuit. A second frequency dividing circuit for frequency-dividing a clock signal output from the frequency dividing circuit, and a circuit for oscillating the oscillation circuit to the first frequency dividing circuit according to a control signal output output from the second frequency dividing circuit. Gate means for controlling the supply of oscillation output;
A pulse signal generating circuit that generates a pulse signal in synchronization with an oscillation output of the oscillation circuit according to a control signal input from the outside, the first frequency dividing circuit and the second frequency dividing circuit, The control signal output which is initialized by the pulse signal generated by the pulse signal generating circuit and is output from the second frequency dividing circuit to the gate means is predetermined after the second frequency dividing circuit is initialized. During the period until the number of clocks is divided, a level for supplying the oscillation output of the oscillation circuit to the first frequency divider is output, and the second frequency divider divides the predetermined number of clocks. After that, the clock signal generating circuit outputs a level for stopping the supply of the oscillation output of the oscillation circuit to the first frequency dividing circuit.