JPH0456481A - Picture processing circuit - Google Patents

Abstract

PURPOSE:To output characters, graphics, or the like in which jitters are reduced, at a prescribed picture position by providing an oscillating means and a frequency dividing means which divides the frequency of a clock outputted from the oscillating means, and which is reset by the synchronizing signal pulse of an inputted video signal. CONSTITUTION:A frequency divider 30 is set by the pulse rise of a horizontal synchronizing signal HD outputted from a synchronizing separator circuit 24, and operates frequency-division at a previous phase until the pulse fall of the signal HD. And also, the output of the frequency divider 30 is turned to a low level at the moment the frequency divider 30 is reset, and the frequency divider 30 starts the frequency-division from the next source oscillation clock. Thus, the output clock of the frequency divider 30 certainly synchronizes the signal HD, and a character pattern generating circuit 26 decides the output timing of a pattern signal by the output of the frequency divider 30. Because of this, the blurring of the picture indicating position of the pattern superimposed on the signal HD exists at most until one cycle of the output clock of the frequency divider 30, and the jitters can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video processing circuit for superimposing and displaying characters, pictures, etc. on a video of an input video signal.

[Prior Art] As such a video processing circuit, there is a character display IC that displays channels used by a television receiver. In this character display IC, the vertical position is known by a vertical counter that counts the horizontal synchronization signal of the input composite video signal, and the horizontal position is determined by the horizontal counter that counts self-oscillation clocks based on the vertical synchronization signal. When the count value of the counter reaches a predetermined value, the video pattern of the character to be displayed is superimposed on the input composite video signal, or the input composite video signal is switched to the video pattern signal of the character to be displayed. There is.

As the oscillator for determining the horizontal position, as partially shown in FIG. 4, a gated oscillator configuration is adopted which stops oscillation during the horizontal synchronization period and starts oscillation from the trailing edge of the horizontal synchronization signal. This provides a clock synchronized with the horizontal synchronization signal.

[Problems to be Solved by the Invention] However, as can be seen from Figure 4, gate oscillators are constructed using resistors and capacitors (or inductors and capacitors), so the oscillation frequency is subject to variations in components and changes in ambient temperature. This has the disadvantage that the size and display position of displayed characters are likely to change.

To deal with this, a configuration using an external clock may be considered, or if the external clock and the horizontal synchronization signal are not synchronized, the vertical lines of characters on the screen will have jagged jitter.

An object of the present invention is to provide a video processing circuit that solves the above problems.

[Means for Solving the Problems] A video processing circuit according to the present invention includes an oscillation means, a frequency division means that divides the output clock of the oscillation means and is reset by a synchronization signal pulse of an input video signal, and an input A pattern generating means for generating a specified pattern signal at a specified screen position according to a synchronizing signal of the video signal and the output of the frequency dividing means, and a superimposing means for superimposing the output pattern of the pattern generating means on the input video signal. It is characterized by consisting of.

[Operation] The output clock of the frequency dividing means is synchronized with the synchronization signal of the input video signal. The pattern generating means determines the output timing of the pattern signal based on the output of the frequency dividing means. Therefore, the blurring of the screen display position of the pattern superimposed on the input video signal is at most 1 of the output clock of the oscillation means.
jitter can be suppressed to a small level.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention applied to a still video floppy playback device. 10
12 is a motor for rotating the magnetic disk 10; 14 is a magnetic head; 16 is a motor drive circuit for driving the motor 12; This is a head feeding device that moves the head.

20 is a preamplifier that amplifies the reproduced RF output of the magnetic head 14; 22 is a reproduced signal processing circuit that reproduces the output of the preamplifier 2o and outputs a reproduced video signal; 24 is a synchronization separation circuit that separates a synchronization signal from the reproduced signal; 26 is a horizontal synchronization signal HD and a vertical synchronization signal V from the synchronization separation circuit 24.
28 is a self-synchronized oscillation circuit; 30 is a frequency divider that divides the clock from the oscillation circuit 28; 32 is a display A variable voltage battery 34 outputs a voltage according to the brightness level of the characters, and 34 is a reproduction signal processing circuit 2 in accordance with the output pattern signal of the character pattern signal generation circuit 26.
2, a switch for selecting output from the battery, 36 an output terminal for a reproduced video signal on which display characters are superimposed, and 38 a system control circuit for controlling the entire system.

FIG. 3 shows an example of the circuit configuration of the frequency divider 30.

A plurality of D-type flip-flops are connected in series in the required number of stages, and a horizontal synchronizing signal is applied to the reset terminals of these flip-flops. Note that it is desirable that the frequency division ratio of the frequency divider 30 can be changed by an external signal.

Next, the operation of this embodiment will be explained. The magnetic disk 10 is rotated at a predetermined number of rotations by a motor 12 and a motor drive device 16, and a head feeding device 18 moves the magnetic head 14 to a desired track. The reproduction output of the magnetic head is converted into a video signal by the reproduction signal processing circuit 22, and the synchronization separation circuit 24 separates and outputs a horizontal synchronization signal HD and a vertical synchronization signal VD from the signal from the reproduction signal processing circuit 22. The horizontal synchronization signal and vertical synchronization signal output from the synchronization separation circuit 24 are sent to the system control circuit 38 and the character pattern generation circuit 26.
The character pattern generation circuit 26 calculates the vertical position by counting the horizontal synchronization signal HD with the vertical synchronization signal VD as a reference, and calculates the vertical position by counting the horizontal synchronization signal HD with the frequency divider 30 as a reference with the horizontal synchronization signal HD.
The horizontal position is known by counting the clocks from the system control circuit 38, and a pattern signal of the specified character is output at the display position instructed by the system control circuit 38.

Character pattern generation circuit 2 is created by simply dividing the oscillator output.
6, when applied to the clock input for determining the horizontal position, jitter of one clock cycle occurs in the output of the frequency divider. Therefore, in this embodiment, the frequency divider 30 is connected to the horizontal synchronizing signal H.
It is now reset by D. As a result, the output of the frequency divider 30 is always synchronized with the horizontal synchronizing signal HD, and as in the case where a gate oscillator is used, blurring of the display position can be greatly reduced.

Character pattern generation circuit 26 by simply dividing the external clock
FIG. 3 shows timing charts for the cases in which the frequency division is reset by a horizontal synchronizing signal as in this embodiment, and a conventional gate oscillator is used.

Note that, to simplify the explanation, a case of frequency division by four is illustrated. Figure 3 (a) is the horizontal synchronization signal, (b) is the original oscillation clock, (c) is the clock that is simply frequency-divided from the clock shown in (b), and (d) is the horizontal synchronization signal. Clock in this embodiment with frequency division reset by HD, same (e)
shows each waveform of a clock in a conventional example using a gate oscillator.

The frequency divider 30 is reset at the rising edge of the horizontal synchronizing signal HD pulse, and divides by the previous phase until the falling edge of the horizontal synchronizing signal HD pulse, and the moment the reset is applied, the output becomes low level, and the next The original oscillation clock (Figure 3(b)
) to start dividing.

Therefore, in this example, as can be seen from FIG. 3(d),
The sick from the horizontal synchronizing signal HD is suppressed to at most one cycle of the original oscillation clock, and is reduced to 1/4 of the case where it is not reset by the horizontal synchronizing signal HD (FIG. 3(C)).

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, characters, figures, etc. can be outputted as images at predetermined screen positions with less jitter, without being affected by variations in temperature or components. . Further, since fewer elements need to be adjusted, adjustments during manufacturing become easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an example of the circuit configuration of the frequency divider 300 shown in FIG. 1, FIG. 3 is a timing diagram, and FIG. 4 is a conventional character display IC. This is an example of an oscillation circuit. 10: Magnetic disk 12: Motor 14: Magnetic head 16: Motor drive circuit 18: Head feeding device 20
: Preamplifier 22: Reproduction signal processing circuit 24: Synchronization separation circuit 26: Character pattern generation circuit 28: Oscillator circuit 30: Frequency divider 32: Battery 34: Switch 36:
Playback video output terminal 38 system control circuit

Claims (1)

[Claims] an oscillation means, a frequency division means that divides the output clock of the oscillation means and is reset by a synchronization signal pulse of the input video signal, and a designated screen according to the synchronization signal of the input video signal and the output of the frequency division means. 1. A video processing circuit comprising: a pattern generating means for generating a specified pattern signal at a position; and a superimposing means for superimposing an output pattern of the pattern generating means on an input video signal.