JPH0451680A - Video processing circuit - Google Patents

Abstract

PURPOSE:To reduce the variation of a displaying position due to the variation of clock frequency by separating a horizontal synchronizing signal and a vertical synchronizing signal from an input composite video signal, and inputting a designated pattern signal just behind the separated horizontal synchronizing signal so as to superimpose it on the composite video signal. CONSTITUTION:A synchronizing separation circuit 12 separates the horizontal synchronizing signal HD and the vertical synchronizing signal VD from the composite video signal from a input terminal 10, and supplies them to a character pattern generation circuit 14, and a control circuit 26 supplies the prescribed control signal of a character and the displaying position to a character pattern generation circuit 14. The character pattern generation circuit 14 counts a clock by an oscillation circuit in the inside on the basis of the horizontal synchronizing signal HD and the vertical synchronizing signal VD from the synchronizing signal separation circuit 12, and generates a pattern signal to show the pattern of a designated character at the displaying position instructed from the control circuit 26. Then, this character pattern is superimposed on the composite video signal, and is outputted from an output terminal 20. Thus, the variation of the displaying position due to the frequency variation of the clock can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video processing circuit for superimposing and displaying characters, pictures, etc. on a video of an input video signal.

[Prior Art] As such a video processing circuit, there is a character display IC that displays channels in use. In this character display IC, the vertical position is known by a vertical counter that counts the horizontal synchronization signal of the input composite video signal, and the horizontal position is determined by the horizontal counter that counts self-oscillation clocks based on the vertical synchronization signal. When the count value of the counter reaches a predetermined value, a video pattern of characters to be displayed is superimposed on the input composite video signal.

[Problems to be Solved by the Invention] In conventional examples, the timing is generally set so that characters to be displayed in a superimposed manner are placed at the upper right or lower right of the monitor screen. However, being on the right side of the monitor screen means that it is further away from the vertical synchronization signal. In other words, the character display begins after the horizontal counter has counted a large number of tarots. Therefore, in the conventional example, it is sensitive to changes in the horizontal display position or the oscillation frequency of the self-oscillator.
It is necessary to suppress variations in the parts used, or to use a trimmer capacitor or variable resistor for adjusting the oscillation frequency. In the former case, the product price becomes high, and in the latter case, the circuit scale becomes large and the effort of adjustment is added.

Furthermore, in recent years there has been an increase in the number of pieces of information that need to be displayed in addition to channel display, and collisions between these items and their avoidance have become a problem.

An object of the present invention is to provide a video processing circuit that solves these problems.

[Means for Solving the Problems] A video processing circuit according to the present invention includes a synchronization separation means for separating horizontal and vertical synchronization signals from an input composite video signal, and a synchronization signal immediately after the horizontal synchronization signal separated by the synchronization separation means. , and pattern generating means for superimposing a specified pattern signal on the input composite video signal.

[Operation] With the above means, the display position on the screen of the pattern based on the specified pattern signal does not change much even with frequency fluctuations of the clock for determining the horizontal display position. Therefore, the number of elements for adjusting the frequency of the clock can also be reduced.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit configuration block diagram of an embodiment of the present invention. 1o is an input terminal for the composite video signal; 12 is a synchronization separation circuit that separates the vertical synchronization signal VD and horizontal synchronization signal HD from the composite video signal; and 14 is a synchronization separation circuit that separates the horizontal synchronization signal HD and vertical synchronization signal VD from the synchronization separation circuit 12. This is a character pattern generation circuit that generates a pattern signal of a specified character at a specified character display position based on a reference. 16 is a battery whose output voltage can be externally controlled and which determines the brightness level of displayed characters; 18;
follows the output of the character pattern generation circuit 14, and input terminal 1
A switch 20 for selecting the composite video signal to be input to 0 or the battery 16 is an output terminal for the composite video signal on which the target character is superimposed. Further, 22 and 24 are a capacitor and a resistor, respectively, which determine the oscillation frequency of an oscillation circuit that generates a clock for display position control in the character pattern generation circuit 14.

Further, 26 is a control circuit that supplies the character pattern generation circuit 14 with a control signal indicating the character to be displayed and its display position. In this embodiment, the control circuit 26 supplies the character pattern generation circuit 14 with a control signal to be displayed on the upper left of the screen. In other words, it is to be displayed at a position close to the horizontal synchronizing signal, which means on the right side of the screen in a monitor device that scans the screen from right to left.

The synchronization separation circuit 12 separates the horizontal synchronization signal HD and the vertical synchronization signal VD from the composite video signal from the input terminal 10 and supplies them to the character pattern generation circuit 14. ) and its display position are supplied to the character pattern generation circuit 14 as a control signal.

The character pattern generation circuit 14 counts clocks generated by an internal oscillation circuit based on the horizontal synchronization signal HD and vertical synchronization signal VD from the synchronization separation circuit 12, and generates the character pattern at the display position instructed by the control circuit 26. generates a pattern signal indicating the pattern of characters specified by.

The switch 18 is connected to the battery 16 side when the character pattern generation circuit 14 is generating a character pattern signal, and otherwise connected to the input terminal 10 side. As a result, the character pattern specified by the control circuit 26 is superimposed on the composite video signal input to the input terminal 10 and output from the output terminal 20.

FIG. 2 is a timing chart showing an example of horizontal timing of the character pattern generation circuit 14. In Figure 2, the pattern of character pattern signal B is displayed at the 3rd clock from the horizontal synchronization signal, and for reference, the pattern of character pattern signal C is displayed at the 20th clock from the horizontal synchronization signal.
When the pattern is displayed, the case is also written. Figure 2 (1)
(2) shows the timing when the oscillation frequency changes due to external conditions such as temperature. The horizontal positional deviation of the character pattern signal B is Δb, whereas the horizontal positional deviation of the character pattern signal C is ΔC.

Obviously, Δb is smaller than ΔC, and therefore, this embodiment is less affected by changes in clock frequency.

FIG. 3 shows a block diagram of another embodiment of the present invention.

The same circuit elements as in FIG. 1 are given the same reference numerals. 30
32 is a delay circuit that delays the horizontal synchronization signal HD output from the sync separation circuit 12, and 32 is a character pattern generation circuit 14.
A clock generation circuit 34 that generates a clock having a sufficiently higher frequency than the clock used in the control circuit 34 is a control circuit that has the function of controlling the amount of delay of the delay circuit 30 in addition to the function of the control circuit 26 .

An example of the circuit configuration of the delay circuit 30 is shown in FIG. 36 is a counter that is cleared by the horizontal synchronization signal HD from the synchronization separation circuit 12 and counts the clock from the clock generation circuit 32; 38 is a latch circuit that latches the delayed data signal from the control circuit 34; and 40 is the latch circuit 38. This is a signal generating circuit that compares the held value of the counter 36 with the count value of the counter 36, and when they match, generates a signal (delayed horizontal synchronization signal) having the same width as the horizontal synchronization signal HD. With this circuit configuration, the delay circuit 30 delays the horizontal synchronization signal from the synchronization separation circuit 12 by the delay amount designated by the control circuit 34 in accordance with the clock from the clock generation circuit 32. The output of the delay circuit 30 is applied to the horizontal synchronization signal input terminal of the character pattern generation circuit 14.

FIG. 5 is a horizontal display position timing chart in the embodiment of FIG. 3. For example, assume that the delay amount of the delay circuit 30 is zero and characters are displayed at the timing of the character pattern signal D1. In this state, if the delay amount of the delay circuit 30 is, for example, τ, the output of the delay circuit 30 will be at the timing indicated as delayed HD signal in FIG. 5, and the settings in the character pattern generation circuit 40 will not be changed at all. , the same character pattern is displayed at the timing indicated by the character pattern signal D2. That is, the displayed character pattern moves to the right on the monitor screen. Since the count value of the counter for determining the display position inside the character pattern generation circuit 14 remains small, the display position variation due to the clock frequency variation remains small.

[Effects of the Invention] As can be easily understood from the above description, according to the present invention, the display position is relatively stable despite the instability of the oscillation frequency of the oscillation circuit. Therefore, adjustment elements such as adjustment trimmer capacitors and variable resistors can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of one embodiment of the present invention, FIG. 2 is a horizontal timing diagram of FIG. 1, FIG. 3 is a block diagram of another embodiment of the invention, and FIG. An example of the circuit configuration of the delay circuit 30, FIG. 5 is a timing diagram in the horizontal direction of FIG. 3. 10: Input terminal 12: Synchronous separation circuit 14: Character pattern generation circuit 16: Battery 18: Switch 20: Output terminal 22: Capacitor 24: Resistor 26: Control circuit 30: Delay circuit 32: Clock generation circuit 34:
control circuit

Claims (1)

[Claims] Synchronization separation means for separating horizontal and vertical synchronization signals from an input composite video signal; and pattern generation means for superimposing a specified pattern signal on the input composite video signal immediately after the horizontal synchronization signal separated by the synchronization separation means. A video processing circuit characterized by comprising: