JPH04195193A - Synchronizing signal generator - Google Patents

Abstract

PURPOSE:To allow superimposing by initializing frequency dividing circuits which generate horizontal and vertical synchronizing signals respectively with the horizontal and vertical synchronizing reset pulses synchronized with dot clock signals. CONSTITUTION:A reference clock 2 supplied from an oscillation circuit 1 is divided in the frequency dividing circuit 3 to generate the dot clock signal 4. The frequency of this signal is divided to generate the horizontal synchronizing signal 8 in the frequency dividing circuit 5. The frequency of this signal is divided to generate the vertical synchronizing signal 17 in the frequency dividing circuit 9. The dot clock signal 4 is inputted to the clock of a flip-flop circuit 13. The pulses 6, 7 synchronized with the dot clock signal are outputted according to the input signals of horizontal and vertical reset input terminals 15, 16 from two-input AND circuits 14. This horizontal synchronizing reset pulse 6 initializes the frequency dividing circuit 5 and the vertical synchronizing reset pulse 7 initializes the frequency dividing circuit 9. The superimposing of the images of a graphic system is obtd. in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a horizontal synchronization signal and a vertical synchronization signal for display display control, as well as display display control, in a graphic system controlled by a microprocessor, display controller, etc. Regarding the synchronization signal generation circuit that generates the dot clock signal, which is a clock signal corresponding to one pixel of graphic data, in particular, it is generated by the graphic system for the video signal (composite signal) output from a laser disc or VTR, etc. The present invention relates to a synchronization signal generation circuit used in a system that superimposes images generated by two graphics systems, or in cases where images generated by two independent graphics systems are superimposed.

[Prior Art] In order to construct a system that superimposes an image generated by a graphic system on a video signal output from a laser disk, VTR, etc. It is necessary to synchronize the image signals generated by the system.

Conventionally, when attempting to realize such a system, the video signal (composite signal) is synchronously separated to extract horizontal and vertical synchronizing signals, and the dot clock signal, which is the basic clock for image generation in the graphic system, is based on this horizontal synchronizing signal. From, P using VCO (voltage controlled oscillator)
This was caused by the LL (phase locked loop) circuit.

[Problems to be Solved by the Invention] However, the method using PLL as in the conventional example described above requires analog circuits such as phase comparison, low-pass filter, and VCO control, making the system complicated. Not only does this require highly sophisticated technology, but it also raises the cost of the system. SUMMARY OF THE INVENTION The present invention aims to solve these problems, and its purpose is to create a superimposable graphics system using simple digital circuits without complicating the system or increasing its cost. The purpose of the present invention is to provide a synchronization signal generation device that can be realized using the following methods.

[Means for Solving the Problems] A synchronization signal generating device of the present invention generates a horizontal synchronization signal, a vertical synchronization signal, and a dot clock signal, which is a clock signal corresponding to one pixel, for display display. In the generating circuit, the dot clock signal is generated by a first frequency divider circuit that divides the reference clock signal, the horizontal synchronization signal is generated by a second frequency divider circuit that divides the dot clock signal, and the horizontal synchronization signal is generated by a second frequency divider circuit that divides the dot clock signal. The vertical synchronization signal is generated by a third frequency dividing circuit that divides the frequency of the horizontal synchronization signal, and includes first and second reset signal input terminals for resetting the synchronization signal generator,
A first pulse signal synchronized with the dot clock signal by a reset signal input from the first reset signal input terminal, and synchronized with the dot clock signal by a reset signal input from the second reset signal input terminal. A frequency dividing circuit that generates a horizontal synchronizing signal is initialized by the first pulse signal generated by the pulse generating circuit and divides the vertical synchronizing signal. The frequency dividing circuit is characterized in that it is initialized by the second pulse signal.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention. 1
is an oscillation circuit that generates a reference clock for the synchronization signal generation circuit. 3 is a dot clock frequency dividing circuit;
By dividing the reference clock 2 supplied from the oscillation circuit,
A dot clock signal 4 is generated. 5 is a horizontal synchronizing signal frequency dividing circuit, which divides the frequency of the dot clock signal 4,
A horizontal synchronizing signal 8 is generated. A vertical synchronizing signal frequency dividing circuit 9 divides the frequency of the horizontal synchronizing signal 8 to generate a vertical synchronizing signal 17. 10, 11, and 12 are a dot clock signal output terminal, a horizontal synchronization signal output terminal, and a vertical synchronization signal output terminal, respectively. 15 is a horizontal synchronization reset input terminal, into which a signal for resetting the horizontal synchronization signal frequency dividing circuit of the synchronization signal generator is inputted. Reference numeral 16 denotes a view angle synchronization reset input terminal, into which a signal for resetting the vertical synchronization signal frequency dividing circuit of the synchronization signal generator is inputted. 13 is a flip-flop circuit, and 14 is a two-person AND circuit. The dot clock signal number 4 is input to the clock of the flip-flop circuit number 13, and by configuring the circuit as shown in the figure, the two-man power AND circuit number 14 is input to the horizontal and vertical reset input terminals number 15 and 16. In response to the signal, a pulse synchronized with the dot clock signal is output at 6.7. 6 is a horizontal synchronizing signal frequency dividing circuit reset signal, and 7 is a vertical synchronizing signal frequency dividing circuit reset signal. Also, 15
．． If there is no reset input of 16, the dot clock signal, horizontal synchronization signal, and vertical synchronization signal are sent out independently according to the set frequency division ratio.

FIG. 2 is a block diagram showing an example of a system for superimposing an image generated by a graphics system on a video signal supplied from the outside using the synchronization signal generating device of FIG. 1, which is an embodiment of the present invention. It is. 20 is a video signal input terminal to which a video signal (composite signal) is supplied from a laser disc or the like. A sync separation circuit 21 separates a horizontal sync signal and a vertical sync signal from the video signal input from 20. 24 is a synchronization signal generator which is an embodiment of the present invention. The horizontal synchronization signal 22 and vertical synchronization signal 23 separated by the 21 synchronization separation circuits are supplied to the 36 CRT display devices as synchronization signals for display display, and are also used as horizontal synchronization reset inputs of the 24 synchronization signal generators. and the vertical synchronization reset input terminal (corresponding to terminal 15.16 in FIG. 1). The sync signal generator 24 generates a horizontal sync signal 26, a vertical sync signal 29, and a dot clock signal 25 for the graphics system in response to the horizontal and vertical sync signals 22.23. 2
8 is a graphic system which generates images using horizontal and vertical synchronizing signals and dot clock signals supplied from 24 synchronizing signal generators. 31 is an RGB signal which is an image signal generated by a graphics system.

29 is a composite/RGB conversion device which converts the video signal (composite signal) input from 20 into RGB
Convert to signal 30. 33 is an R for switching between an RGB signal 30 obtained by converting the video signal inputted from 20 and an RGB signal 31 generated from the graphic system 28;
This is a GB switch circuit, which switches between two RGB signals using an RGB switch control signal 32 supplied from the graphic system 28, and outputs an RGB signal 34 to the display device. 36 is a CRT display device. With such a configuration, it is possible to superimpose an image of a graphics system onto a video signal.

FIG. 3 is a timing chart showing the operation of the synchronizing signal generator of FIG. 1. (a) is a dot clock signal, which is the signal shown in FIG. 14.

When the signal shown in (b) is input to the horizontal synchronization reset input terminal in FIG. 15, the dot clock shown in FIG. 16 is generated by the flip-flop shown in FIG. A pulse corresponding to one cycle of the dot clock signal is generated in synchronization with the signal. This reset pulse resets the horizontal synchronizing signal frequency divider circuit in FIG.
) The horizontal synchronizing signal 8 is generated at the timing as shown in FIG. The vertical synchronization signal frequency dividing circuit is also reset at the same timing as shown in FIG. 3, and a vertical synchronization signal is generated. Since the horizontal synchronization signal and the vertical synchronization signal are generated at such timing, the horizontal synchronization signal and the vertical synchronization signal of the video signal supplied from the outside are used as the synchronization signal according to the embodiment of the present invention, as shown in FIG. By supplying the signal to the horizontal synchronization reset input and vertical synchronization reset input of the generator, it is possible to generate horizontal and vertical synchronization signals synchronized with an external video signal. Assuming that the jitter of the horizontal sync signal of the video signal is smaller than the period of the dot clock, the configuration shown in Figure 2 will require a reset of the horizontal sync signal frequency divider circuit for each horizontal sync signal. , when the horizontal synchronization signal of the video signal and the horizontal synchronization signal output from the synchronization signal generator are shifted by one period of the dot clock,
This takes the form of correction being applied to the horizontal synchronization signal. Therefore, the number of dot clocks per horizontal phase signal generated by the synchronization signal generator may be N, N+1, or N-1, but it is necessary to reset in synchronization with the dot clock. Therefore, the phase relationship between the etch of the horizontal synchronizing signal outputted by the synchronizing signal generator and the dot clock is always maintained. Therefore, if a graphics system or a graphics controller is used in which the display position of image data is determined by the number of dot clocks from the etch of the horizontal synchronization signal, no particular problem will occur.

Further, when the correction is applied, a shift in the display position occurs, but if the system uses a dot clock with a frequency of about 10 MHz or more, this shift is slight on the display screen, and there is no particular problem.

As described above, by using the synchronization signal generator of the present invention, it is possible to construct a superimposable graphic system.

[Effects of the Invention] As described above, according to the present invention, a superimposable graphic system can be created without complicating the system or increasing the price, and without using advanced analog circuit technology. This has the advantage that it can be realized with a simple digital circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. Figure 2 shows
FIG. 1 is a block diagram showing an example of a graphics system using a synchronization signal generation device according to an embodiment of the present invention. FIG. 3 is a timing chart showing the operation of the synchronizing signal generator of FIG. 1. 1...Oscillation circuit 2...Reference clock signal 3...Dot clock frequency divider circuit 4...Dot clock signal 5...Horizontal synchronization signal frequency divider circuit 6...H counter reset signal 7... -Counter reset signal 8...Horizontal synchronization signal 9...Vertical synchronization signal frequency divider circuit IQ...Dot clock signal output terminal 11...Horizontal synchronization signal output terminal 12...Vertical synchronization signal output terminal 13 ...Flip-flop circuit 14...2 manual AND circuit 15...Horizontal synchronization reset input 16...Vertical synchronization reset human power 17...Vertical synchronization signal 20...Video signal input terminal 21...Synchronization Separation circuit 22...Horizontal sync signal 23...Vertical sync signal 24...Sync signal generator 25...Dot clock signal 26...Horizontal sync signal 27...Vertical sync signal 28...Graphic System 29...Composite/RGB conversion device 30...R
GB signal 31...RGB signal 32...RGB switch control signal 33...
RGB switch circuit 34...RGB signal 36...CRT display and above Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kizobe Suzuki (and 1 other person) KIIF) Office 2e

Claims (1)

[Scope of Claims] In a synchronization signal generation circuit that generates a horizontal synchronization signal, a vertical synchronization signal, and a dot clock signal which is a clock signal corresponding to one pixel unit for display display, the dot clock signal is a reference clock. The horizontal synchronization signal is generated from a first frequency division circuit that frequency divides the signal, the horizontal synchronization signal is generated from a second frequency division circuit that frequency divides the dot clock signal, and the vertical synchronization signal is generated from the horizontal synchronization signal. A reset generated by a third frequency dividing circuit that divides the frequency, comprising first and second reset signal input terminals for resetting the synchronization signal generator, and inputted from the first reset signal input terminal. signal, the first dot clock signal is synchronized with the dot clock signal.
and a pulse generation circuit that generates a second pulse signal synchronized with the dot clock signal by a reset signal inputted from the second reset signal input terminal, and a pulse generation circuit that generates the horizontal synchronization signal. The frequency dividing circuit is initialized by a first pulse signal generated by the pulse generating circuit, and the frequency dividing circuit that divides the frequency of the vertical synchronizing signal is initialized by a second pulse signal. Synchronous signal generator.