JP2008028696A - Synchronous circuit of imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous circuit of an imaging element that does not produce pixel displacement. <P>SOLUTION: The synchronous circuit of an imaging element 3 comprises: a frequency divider 8 for dividing the frequency of a clock 7 to generate a frequency division clock 9; a signal processing circuit 4 for generating a horizontal synchronizing signal 6 and a vertical synchronizing signal 16; and a timing generator 2 for generating an image element drive signal 18 from the frequency division clock 9, the horizontal synchronizing signal 6, and the vertical synchronizing signal 16. In the synchronous circuit, the timing generator 2 generates a gate signal 12, and a correction clock 15 is generated from the clock 7, the frequency division clock 9, the horizontal synchronizing signal 6, and the gate signal 12. There is further provided a clock correction circuit for supplying the correction clock to the signal processing circuit 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a synchronizing circuit for an image sensor such as a CCD or a CMOS image sensor, and more particularly to a synchronizing circuit for an image sensor having a plurality of output systems.

  There exists patent document 1 as an example of the synchronizing circuit of the conventional image pick-up element. A conventional synchronization circuit of an image sensor will be described with reference to FIG. FIG. 3 is a block diagram of a conventional synchronization circuit of an image sensor. An imaging apparatus comprising: a solid-state imaging device 32 that converts light transmitted through a lens 31 into an electrical signal; and a video signal processing circuit 33 that converts an electrical signal that is an output of the solid-state imaging device 32 into a video signal. A readout pulse control circuit 35 that controls the time interval of readout pulses for reading out the charges accumulated in the solid-state imaging device 32, and a synchronization signal generation circuit that supplies the readout pulses to the solid-state imaging device 32, the video signal processing circuit 33, and the video memory 36. 34 and a video memory 36 for recording a video signal in accordance with the timing of the readout pulse.

  The read pulse control circuit 35 changes the time interval of read pulses supplied to the solid-state imaging device 32. For example, in the case of low illuminance, the exposure time of the solid-state image sensor 32 is lengthened. The video memory 36 records the video signal output from the video signal processing circuit 33 in synchronization with the timing of the readout pulse.

  The above example is an example of a so-called master mode in which the synchronization signal generation circuit 34 controls the overall timing. Next, an example of a so-called slave mode in which the horizontal synchronizing signal HD and the vertical synchronizing signal VD are performed by other than the timing generator will be described. Here, the timing generator corresponds to the synchronization signal generation circuit 34 in the above example.

  FIG. 4 is a block diagram of a synchronization circuit of a conventional image sensor in slave mode. In FIG. 4, CLK 41 that is the output of the oscillator 1 is supplied to the timing generator TG 2 and the signal processing circuit 4. The image sensor drive signal 18 that is the output of the timing generator TG2 is supplied to the image sensor 3. An image signal 42 output from the image sensor 3 is supplied to the signal processing circuit 4. The signal processing circuit 4 counts CLK41 and generates a horizontal synchronizing signal HD6 and a vertical synchronizing signal VD16. The horizontal synchronization signal HD6 and the vertical synchronization signal VD16 are supplied to the timing generator TG2. The timing generator TG2 generates an image sensor driving signal 18 for driving the image sensor 3 from CLK41, HD6, and VD16.

  In addition, there is an image sensor having a plurality of output systems in a demand for higher pixels and higher speed. For example, there is an image sensor that outputs the image signal output from the image sensor in parallel to two systems of the upper half of the screen and the lower half of the screen. In such an image sensor, since the image signal can be read out at a double speed without doubling the frequency of the image sensor drive signal, an increase in power consumption by increasing the speed of the image sensor drive signal, While avoiding an increase in the amount of heat generation and an increase in radiation noise, high-speed image signal reading can be realized at the same time.

  FIG. 5A is a block diagram of a synchronization circuit of an image sensor having a plurality of output systems. In FIG. 5A, CLKa 7 that is the output of the oscillator 1 is supplied to the ½ frequency divider 8 and the signal processing circuit 4. CLKb9, which is the output of the 1/2 divider 8, is supplied to the timing generator TG2. The image sensor drive signal 18 that is the output of the timing generator TG2 is supplied to the image sensor 3. The image signal 10 in the upper half of the screen and the image signal 11 in the lower half of the screen output from the image sensor 3 are supplied to the signal processing circuit 4. The signal processing circuit 4 counts CLKa7 and generates a horizontal synchronizing signal HD6 and a vertical synchronizing signal VD16. The horizontal synchronization signal HD6 and the vertical synchronization signal VD16 are supplied to the timing generator TG2. The timing generator TG2 generates an image sensor driving signal 18 for driving the image sensor 3 from CLKa7, HD6, and VD16.

  The output of the oscillator 1 is set to double the conventional frequency, and the frequency is halved by the 1/2 frequency divider 8. Therefore, the image sensor drive signal 18 that is the output of the timing generator TG2 is the same as that of the image sensor that does not have a plurality of output systems. The image signal 10 in the upper half of the screen and the image signal 11 in the lower half of the screen output from the image sensor 3 are input to the signal processing circuit 4. The signal processing circuit 4 outputs the image signal 10 in the upper half of the screen and the image signal 11 in the lower half of the screen output from the image sensor 3 according to CLKa7 that is twice the frequency of an image sensor that does not have a plurality of output systems. Combine to generate a single image signal. CLKa7, which is twice the frequency of an image sensor that does not have a plurality of output systems, is supplied to the 1/2 frequency divider circuit 8 and the signal processing circuit 4, but is not supplied to the image sensor 3, so power consumption Increase, heat generation amount, and radiation noise increase can be avoided.

FIG. 5B is a timing chart of the synchronization circuit of the image sensor having a plurality of output systems. The CLKb9 output from the 1/2 frequency divider 8 is either one of two signals CLKb9 (A) and CLKb9 (B) whose phases are accidentally inverted by 180 degrees depending on the state at the time of power-on or reset. Become. Similarly, the horizontal synchronization signal HD6 is one of the two signals HD6 (A) and HD6 (B).
Japanese Patent Laid-Open No. 6-165048

  However, in such a configuration, it is necessary to synchronize between CLKa7, CLKb9, and HD6. If these synchronizations are not achieved, the phase varies depending on the state of power-on, reset, etc., and pixel shift occurs. Pixel shift appears as an abnormal image. In addition, the pixel shift may occur not only when the power is turned on or reset, but also when synchronizing every vertical period and horizontal period.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a synchronization circuit for an image sensor in which no pixel shift occurs.

  In order to solve the above problems, a synchronizing circuit of an imaging device of the present invention includes a frequency divider that divides a clock to generate a divided clock, a signal processing circuit that generates a horizontal synchronizing signal and a vertical synchronizing signal, A timing generator that generates an image sensor drive signal from the frequency-divided clock, the horizontal synchronization signal, and the vertical synchronization signal, wherein the timing generator generates a gate signal; A clock correction circuit is provided that generates a correction clock from the clock, the frequency-divided clock, the horizontal synchronization signal, and the gate signal and supplies the correction clock to the signal processing circuit.

  With the above configuration, by performing synchronization detection and synchronization of two clocks, it is possible to provide a favorable imaging device synchronization circuit in which pixel shift does not occur. According to the present invention, these effects can be realized with a simple configuration, which is extremely effective in practice.

(1. Configuration)
The configuration of the synchronizing circuit of the image sensor that is one embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a synchronizing circuit of an image sensor that is an embodiment of the present invention. In FIG. 1, CLKa 7 that is the output of the oscillator 1 is supplied to a ½ frequency divider 8 and an OR circuit 14. CLKb9 which is the output of the 1/2 frequency divider 8 is supplied to the timing generator TG2 and the D input of the flip-flop 5. The image sensor drive signal 18 that is the output of the timing generator TG2 is supplied to the image sensor 3. The image signal 10 in the upper half of the screen and the image signal 11 in the lower half of the screen output from the image sensor 3 are supplied to the signal processing circuit 4. The signal processing circuit 4 counts CLKc15, which is the output of the OR circuit 14, and generates a horizontal synchronizing signal HD6 and a vertical synchronizing signal VD16. The horizontal synchronization signal HD6 is supplied to the timing generator TG2 and the clock input of the flip-flop 5. The vertical synchronization signal VD16 is supplied to the timing generator TG2. * Q which is the output of the flip-flop 5 and the gate signal 12 which is the output of the timing generator TG 2 are supplied to the AND circuit 13. The output 17 of the logical product circuit 13 is supplied to the logical sum circuit 14. CLKc15, which is the output of the OR circuit 14, is supplied to the signal processing circuit 4. The flip-flop 5, the logical product circuit 13, and the logical sum circuit 14 constitute a clock correction circuit of the present invention.
(2. Operation)
The operation of the synchronizing circuit of the image sensor as an embodiment of the present invention will be described with reference to FIG. FIG. 2 is a timing chart of the synchronization circuit of the image sensor according to the embodiment of the present invention. In FIG. 2, CLKa7 which is the output of the oscillator 1 is divided by 1/2 by the 1/2 divider 8 to become CLKb9. CLKb9 is one of two signals CLKb9 (A) and CLKb9 (B) whose phases are accidentally inverted by 180 degrees depending on the state such as when the power is turned on or reset. Similarly, the horizontal synchronization signal HD6 is one of the two signals HD6 (A) and HD6 (B). Here, description will be made assuming that CLKb9 (A) and HD6 (A) are signals having the correct phase.
(2.1 Correct phase)
The case where CLKb9 and HD6 are in the correct phase, that is, the case of CLKb9 (A) and HD6 (A) will be described. At the rising edge of HD6 (A), the D input of the flip-flop 5, that is, CLKb9 (A) is in the H state, so the * Q output (A) of the flip-flop 5 is in the L state. In the * Q output (A) of the flip-flop 5, the dotted line indicates that the state is indefinite. The gate signal 12 that is the output of the timing generator TG2 maintains the H state for half a clock of CLKb9 (A) following the rising edge of HD6 (A). Here, the half clock is a period during which the clock maintains the H state. In the AND circuit 13, the * Q output (A) of the flip-flop 5 that is one input is in the L state. Therefore, even if the gate signal 12 that is the other input changes, the output 17 of the AND circuit 13 is changed. Maintain the L state. Therefore, CLKa 7 passes through the OR circuit 14 as it is to become CLKc 15 (A) and is supplied to the signal processing circuit 4.
(2.2 In case of incorrect phase)
The case where CLKb9 and HD6 are in the wrong phase, that is, the case of CLKb9 (A) and HD6 (B) will be described. At the rising edge of HD6 (B), the D input of the flip-flop 5, that is, CLKb9 (A) is in the L state, so the * Q output (B) of the flip-flop 5 is in the H state. In the * Q output (B) of the flip-flop 5, the dotted line indicates that the state is indefinite. The gate signal 12 that is the output of the timing generator TG2 maintains the H state for half a clock of CLKb9 (A) following the rising edge of HD6 (B). Here, the half clock is a period during which the clock maintains the H state. In the AND circuit 13, the * Q output (B) of the flip-flop 5 that is one input is in the H state, so the gate signal 12 that is the other input becomes the output 17 of the AND circuit 13 as it is. Therefore, CLKa7 which is the input of the OR circuit 14 is masked to become CLKc15 (A) while the gate signal 12 is maintained in the H state, and is supplied to the signal processing circuit 4.

Since the period during which CLKa7 is masked is a half clock of CLKb9 (A), that is, one clock of CLKa7, CLKc15 (B) is shifted by one clock with respect to CLKa7. As a result, pixel shifts that occur when CLKb9 and HD6 are in the wrong phase can be suppressed. FIG. 2 shows an ideal timing chart in which the influence of gate delay, wiring delay, etc. is ignored. Actually, the output 17 of the AND circuit 13 rises during the L state period of the CLKa 7 due to the influence of gate delay, wiring delay, etc., and a glitch may occur in the output of the CLKc 15 that is the output of the OR circuit 14. In such a case, a delay circuit such as one-shot may be used so that the output 17 of the AND circuit 13 rises during the H state period of CLKa7. Some recent timing generators have a function of adjusting the pulse phase and the pulse width. In such a case, it is possible to create the gate signal 12 in consideration of the delay amount of each part.
(2.3 Other cases)
When CLKb9 and HD6 are CLKb9 (B) and HD6 (B), the phase is correct, which is the same as described in (2.1 Correct phase). Further, when CLKb9 and HD6 are CLKb9 (B) and HD6 (A), it is a case of an incorrect phase, which is the same as described in (2.2 In the case of an incorrect phase).

  The present invention can be applied to an apparatus equipped with an image sensor such as a digital still camera, a digital video camera, and a mobile phone having a digital still camera function.

1 is a block diagram of a synchronizing circuit of an image sensor that is an embodiment of the present invention. 1 is a timing chart of a synchronization circuit of an image sensor according to an embodiment of the present invention. Block diagram of a conventional synchronization circuit of an image sensor Block diagram of a conventional slave mode image sensor synchronization circuit Block diagram and timing chart of synchronizing circuit of image sensor having multiple output systems

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Oscillator 2 Timing generator 3 Image pick-up element 4 Signal processing circuit 5 Flip-flop 6 Horizontal synchronizing signal 7 Clock 8 1/2 frequency divider 9 Frequency division clock 10 Image signal of upper half of screen 11 Image signal of lower half of screen 12 Gate signal DESCRIPTION OF SYMBOLS 13 AND circuit 14 OR circuit 15 Correction clock 16 Vertical synchronizing signal 17 Output of AND circuit 13 18 Image sensor drive signal

Claims (3)

A frequency divider that divides the clock to generate a divided clock;
A signal processing circuit for generating a horizontal synchronizing signal and a vertical synchronizing signal;
A timing generator that generates an image sensor drive signal from the divided clock, the horizontal synchronization signal, and the vertical synchronization signal;
A synchronization circuit of an image sensor having:
The timing generator generates a gate signal;
A clock correction circuit that generates a correction clock from the clock, the divided clock, the horizontal synchronization signal, and the gate signal and supplies the correction clock to the signal processing circuit;
An imaging device synchronization circuit comprising: The clock correction circuit includes:
A flip-prop having the horizontal synchronization signal as a clock input and the divided clock as a D input;
A logical product circuit for generating a logical product of the inverted output of the flip-flop and the gate signal;
An OR circuit for generating an OR of an output of the AND circuit and the clock;
The synchronizing circuit for an image sensor according to claim 1, comprising: The gate signal is
Maintaining the H state for one cycle of the clock after the rising edge of the horizontal synchronizing signal;
The synchronizing circuit for an image sensor according to claim 1 or 2.

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