JP2003298954A - Drive circuit for solid-state image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit for a solid-state image sensor which suppresses deviation in the timing of a horizontal drive pulse signal. <P>SOLUTION: An A1/A2 signal generating block 11 receives a basic clock signal of a frequency of 25 MHz, generates clock signals A1, A2 with a frequency of 12.5 MHz, selects either of the cock signals and outputs the selected clock signal. A B1/B2 signal generating block 12 receives the basic clock signal of a frequency of 25 MHz, generates clock signals B1, B2 of a frequency of 12.5 MHz delayed by a half period of the basic clock signal from the clock signals A1, A2, selects either of the clock signals and outputs the selected clock signal. A synchronization block 13 outputs the clock signals outputted from the blocks 11, 12 synchronously with the leading edge of the system clock signal of a frequency higher than 25 MHz. A logic gate 14 logically composes synchronized clock signals Async and Bsync to output a horizontal drive signal H1. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for driving a solid-state image pickup device such as a CCD image sensor.

[0002]

2. Description of the Related Art Solid-state image pickup devices represented by CCD image sensors are widely used in electronic cameras and the like. C
In the CD image sensor, the signal charges accumulated in each pixel are vertically transferred according to the vertical transfer clock signal, and after the vertical transfer, are horizontally transferred according to the horizontal transfer clock signal. The vertical transfer clock signal and the horizontal transfer clock signal are generated according to the specifications of the solid-state image sensor by performing frequency division, delay, logic synthesis, and the like on the basic clock signal. The vertical transfer clock signal is, for example,
Four drive pulse signals V1 to V4 each having a different phase
Composed by. The horizontal transfer clock signal is composed of, for example, two drive pulse signals H1 and H2 whose logics are opposite to each other, that is, opposite polarities.

[0003]

A plurality of drive pulse signals forming a horizontal transfer clock signal and a plurality of drive pulse signals forming a vertical transfer clock signal are transferred unless they are synchronized with each other. This causes a timing shift and makes accurate signal charge transfer difficult. If the signal charge is not transferred, a correct image cannot be obtained from the solid-state image sensor, resulting in deterioration of image quality. The timing deviation of the drive pulse signal tends to be a problem when the frequency of the clock signal is high.

It is an object of the present invention to provide a drive circuit for a solid-state image pickup device which prevents deterioration of image quality due to a timing shift of a drive pulse signal.

[0005]

The invention described in claim 1 is applied to a drive circuit for supplying a drive pulse signal to a solid-state image pickup device, and a first pulse signal and a second pulse signal different from the first pulse signal. A first selection circuit that selects and outputs any one of the pulse signals, and selects and outputs any one of the third pulse signal and a fourth pulse signal different from the third pulse signal. And a synchronization circuit that synchronizes the pulse signal output from the first selection circuit and the pulse signal output from the second selection circuit using a common clock signal. By supplying the synchronized pulse signals to the respective solid-state image pickup devices, the above-mentioned object is achieved. The invention according to claim 2 is applied to a drive circuit that supplies a drive pulse signal to a solid-state image sensor, and performs a torgu operation at a rising edge of a basic clock signal to reverse a first pulse signal and a first pulse signal. Generate a second pulse signal of each phase,
A first signal output circuit that selects and outputs one of the first pulse signal and the second pulse signal; and a third pulse signal that performs a toggling operation at the falling edge of the basic clock signal. 4th of opposite phase with 3rd pulse signal
Pulse signals generated from the first signal output circuit and the second signal output circuit for respectively generating one of the third pulse signal and the fourth pulse signal and outputting the selected pulse signal. A synchronization circuit that synchronizes the signal and the pulse signal output from the second signal output circuit using a common clock signal, and supplies the pulse signals synchronized by the synchronization circuit to the solid-state imaging device, respectively. Achieve the purpose. The common clock signal is
The clock signal may have a frequency higher than that of the basic clock signal.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a drive circuit for a solid-state image sensor according to an embodiment of the present invention. Such a drive circuit is used, for example, in an electronic camera. In FIG. 1, the drive circuit includes an A1 / A2 signal generation block 11, a B1 / B2 generation block 12, a synchronization block 13, a logic gate 14, an A1 / A2 signal generation block 21, and a B1 / B2 generation block 22. ,
It has a synchronization block 23 and a logic gate 24. Figure 1
The drive circuit of 1 supplies the horizontal drive pulse signals H1 and H2 to the solid-state image pickup device including a CCD image sensor or the like.

A1 / A2 signal generation blocks 11 and B
To the 1 / B2 signal generation block 12, for example, a basic clock signal having a frequency of 25 MHz is input from a clock generation circuit (not shown). A1 / A2 signal generation block 11
Detects a rising edge of the basic clock signal and performs a toggle operation each time a rising edge is detected. The toggle operation is, for example, an output inversion operation performed when the data input terminal D of the D-flip-flop (not shown) is connected to the data inversion output terminal Q-1 and the basic clock signal is input to the clock input terminal CK. Is.

The basic clock signal is set to 1 by the toggle operation.
Clock signal A with a frequency of 12.5 MHz divided by 2
1 is output from the data output terminal Q of the D-flip-flop. A clock pulse signal A2 having a logic opposite to that of the clock signal A1, that is, an opposite phase, is output from the data inversion output terminal Q-1 of the D-flip-flop. In this way, the A1 / A2 signal generation block 11 generates clock signals A1 and A2 synchronized with the basic clock signal.

The B1 / B2 signal generation block 11 detects the falling edge of the basic clock signal and performs a toggle operation each time the falling edge is detected. The basic operation clock signal is divided in half by the toggle operation, and the clock signal B1 having a frequency of 12.5 MHz and the clock signal B
A clock pulse signal B2 having a phase opposite to that of 1 is generated. The clock signal B1 is a signal obtained by delaying the clock signal A1 by 1/2 cycle of the basic clock signal. The clock signal B2 is a signal obtained by delaying the clock signal A2 by 1/2 cycle of the basic clock signal.

A1 / A2 signal generation blocks 11 and B
A selection signal PHASE SEL is further input to the 1 / B2 signal generation block 12 from a control circuit (not shown).
The selection signal PHASE SEL is the selection signal SEL A and the selection signal SEL B.
Composed of and. The selection signal SEL A is input to the A1 / A2 signal generation block 11, and the selection signal SEL B is input to the B1 / B2 signal generation block 12, respectively. A1 / A2
The signal generation block 11 has a selection circuit (not shown). When the selection signal SEL A is L level, the clock signal A1 is selected and output, while when the selection signal SEL A is H level,
The clock signal A2 is selected and output. The B1 / B2 signal generation block 12 selects and outputs the clock signal B1 when the selection signal SEL B is L level, and selects and outputs the clock signal B2 when the selection signal SEL B is H level.

The synchronization block 13 synchronizes the clock signal A1 or A2 and the clock signal B1 or B2 output from the A1 / A2 signal generation block 11 and the B1 / B2 signal generation block 12 with the system clock signal, and after synchronization. It outputs the clock signal Async and the clock signal Bsync, respectively. The system clock signal is supplied to the synchronization block 13 from a clock generation circuit (not shown). The system clock signal is a clock signal having a frequency higher than that of the basic clock signal, and is, for example, a clock signal having a frequency of 100 MHz.

The synchronization block 13 is composed of two D-flip-flops 131 and 132. A1 / A2 is connected to the data input terminal D of the D-flip-flop 131.
Clock signal A1 output from the signal generation block 11
Alternatively, A2 is input. D-flip-flop 13
The clock signal B1 or B2 output from the B1 / B2 signal generation block 12 is input to the second data input terminal D. The system clock signal is input to the clock input terminals CK of the D-flip-flops 131 and 132, respectively.

FIG. 2 is a diagram showing an example of waveforms of input / output signals of the synchronization block 13. In particular, FIG. 2 shows the synchronization block 1
3 shows a state in which the clock signal A1 is input from the A1 / A2 signal generation block 11 and the clock signal B1 is input from the B1 / B2 signal generation block 12. The D-flip-flop 131 samples the H level at the first rising edge of the signal input to the clock input terminal CK after the input signal (clock signal A1) of the data input terminal D goes to the H level, and outputs the H level. Signal is output to the data output terminal Q. Further, the D-flip-flop 131 samples the L level at the first rising edge of the signal input to the clock input terminal CK after the input signal (clock signal A1) of the data input terminal D becomes the L level, The L level signal is output to the data output terminal Q. The signal output to the data output terminal Q has the same cycle as the input signal of the data input terminal D (in this case, the clock signal A1) and is the clock signal Async synchronized with the system clock signal.

On the other hand, the D-flip-flop 132 sets the H level at the first rising edge of the signal input to the clock input terminal CK after the input signal (clock signal B1) of the data input terminal D becomes the H level. It samples and outputs an H level signal to the data output terminal Q.
Further, the D-flip-flop 132 samples the L level at the first rising edge of the signal input to the clock input terminal CK after the input signal (clock signal B1) of the data input terminal D becomes the L level, The L level signal is output to the data output terminal Q. The signal output to the data output terminal Q has the same cycle as the input signal of the data input terminal D (in this case, the clock signal B1) and is the clock signal Bsync synchronized with the system clock signal.

The A1 / A2 signal generating block 11 and the A1 / A2 signal generating block 21, B1 / B described above
2 signal generation block 12 and B1 / B2 signal generation block 22, synchronization block 13 and synchronization block 23
Are composed of the same circuit. Therefore, the synchronization block 13 and the synchronization block 23 output the same clock signals Async and Bsync, respectively.

The logic gate 14 has a synchronous clock signal Asy.
Opposite phase synchronous clock signal Async-1 with the logic of nc inverted
And the synchronous clock signal Bsync are ANDed, and the AND is inverted to output the horizontal drive pulse signal H1.

The logic gate 24 has a synchronous clock signal Bsy.
Reverse phase synchronous clock signal Bsync-1
And the synchronous clock signal Async are taken, and the logical sum is inverted to output the horizontal drive pulse signal H2.

FIG. 3 shows horizontal drive pulse signals H1 and H.
It is a figure which shows the example of 2 waveforms. In Figure 3, PH = 0 (PHASE
0) is the above-mentioned selection signal SEL A = L level, selection signal SE
LB = L level is shown. PH = 1 (PHASE 1) indicates a state in which the selection signal SEL A = L level and the selection signal SEL B = H level. PH = 2 (PHASE 2) indicates a state in which the selection signal SEL A = H level and the selection signal SEL B = H level. PH = 3 (PHASE 3)
Indicates a state in which the selection signal SEL A = H level and the selection signal SEL B = L level.

At PH = 0 (PHASE 0), the synchronous clock signal Async is a signal obtained by synchronizing the clock signal A1 with the system clock signal. The synchronous clock signal Bsync is obtained by synchronizing the clock signal B1 with the system clock signal. The waveform of the horizontal drive pulse signal H1 in this case is
It has a waveform shown by the signal H1 (PH0). Further, the waveform of the horizontal drive pulse signal H2 becomes the waveform shown in the signal H2 (PH0).

When PH = 1 (PHASE 1), the synchronous clock signal Async is obtained by synchronizing the clock signal A1 with the system clock signal. The synchronous clock signal Bsync is obtained by synchronizing the clock signal B2 with the system clock signal. The waveform of the horizontal drive pulse signal H1 in this case is
It has the waveform shown in the signal H1 (PH1). Further, the waveform of the horizontal drive pulse signal H2 becomes the waveform shown in the signal H2 (PH1).

In PH = 2 (PHASE 2), the synchronous clock signal Async is the clock signal A2 synchronized with the system clock signal. The synchronous clock signal Bsync is obtained by synchronizing the clock signal B2 with the system clock signal. The waveform of the horizontal drive pulse signal H1 in this case is
The waveform becomes the signal H1 (PH2). Further, the waveform of the horizontal drive pulse signal H2 becomes the waveform shown in the signal H2 (PH2).

In PH = 3 (PHASE 3), the synchronous clock signal Async is a signal obtained by synchronizing the clock signal A2 with the system clock signal. The synchronous clock signal Bsync is obtained by synchronizing the clock signal B1 with the system clock signal. The waveform of the horizontal drive pulse signal H1 in this case is
The waveform becomes the signal H1 (PH3). Further, the waveform of the horizontal drive pulse signal H2 becomes the waveform shown in the signal H2 (PH3).

The control circuit (not shown) has PH = 0 to
Select signal PHAS to select any one of PH = 3
E SEL (selection signal SEL A and selection signal SEL B) is output. Which of PH = 0 to PH = 3 is selected is determined according to the driving state of the solid-state image sensor.

According to the embodiment described above, the following operational effects can be obtained. (1) An A1 / A2 signal generation block 11 (21) is provided, and a basic clock signal (frequency 25 MH in the above example) is provided.
z) and the toggle operation causes a frequency half the frequency of the basic clock signal (12.5 MH in the above example).
z), generating a clock signal A1 synchronized with the basic clock signal and a clock signal A2 having a phase opposite to that of the clock signal A1, and generating the clock signal A1 and the clock signal A
Either one of 2 is selected and output. Since the basic clock signal is divided by a toggle operation to generate a plurality of signal groups (clock signal A1 and clock signal A2), it is not necessary to provide a logic gate for generating the signal group, and the circuit configuration is simple. Multiple clock signals can be obtained. The same applies to the B1 / B2 signal generation block 12 (22). (2) A1 / A2 signal generation block 11 (21), B1
The signal output of the / B2 signal generation block 12 (22) is such that one clock signal is selected from a plurality of clock signal groups by a selection circuit (not shown) and is output. The delay amount (propagation delay time) given to the signal is the delay time of one selection circuit regardless of which clock signal is selected. As a result, it is possible to prevent the delay amount from varying for each selected clock signal. (3) The synchronization block 13 (23) is provided, and the clock signal output from the A1 / A2 signal generation block 11 (21) and the B1 / B2 signal generation block 12 (22)
Since the clock signal output from each of the signal generating blocks is output in synchronization with the rising edge of the system clock signal having a frequency higher than the frequency of the basic clock signal (clock signals Async and Bsync), the signal is output from each signal generation block. Even if there is a phase shift (difference in delay amount) between the clock signals, these phase shifts can be made zero. (4) The horizontal drive pulse signal H1 is obtained by logically combining the clock signals Async and Bsync synchronized by the above (3) with only one logic gate 14.
It is possible to minimize the delay amount given to the horizontal drive pulse signal H1 as compared with the case where logic synthesis is performed using a plurality of logic gates after synchronization with the system clock signal. (5) Like the horizontal drive pulse signal H1, the horizontal drive pulse signal H2 is obtained by logically synthesizing the clock signals Async and Bsync synchronized by the above (3) with only one logic gate 24. The amount of delay given to the horizontal drive pulse signal H2 can be minimized. (6) The logic gate 24 has three stages (NOT, OR, N).
OT configuration, and the logic gate 14 is configured in three stages (NO
Because of the T, AND, NOT) configuration, it is possible to match the difference in delay amount between the logic gates 24 and 14 without using a delay element such as a delay line. As a result, the horizontal drive pulse signal H2 and the horizontal drive pulse signal H1 can be accurately set in the opposite phase relationship.
A shift in the transfer timing of the signal charges output from the solid-state image sensor is suppressed, and the charges can be accurately transferred. As a result, it is possible to prevent the image quality from being deteriorated due to the transfer timing deviation. In addition, since time-consuming timing adjustment work is unnecessary, the number of adjustment steps can be reduced.

In the above description, the generation of the horizontal drive pulse signal is described as an example, but the same applies to the generation of the vertical drive pulse signal.

Although the driving circuit of the CCD image sensor in which the pixel regions are arranged two-dimensionally has been described as an example, it may be applied to the driving circuit of the line sensor in which the pixels are arranged in a line.

In the above description, the synchronization is achieved by using the rising edge of the system clock signal.
You may make it synchronize using a falling edge.

Correspondence between each component in the claims and each component in the embodiment of the invention will be described. The clock signal A1 corresponds to the first pulse signal, for example. The clock signal A2 corresponds to the second pulse signal, for example. The first selection circuit is configured by, for example, the selection circuit in the A1 / A2 signal generation block 11. For example, the clock signal B1 corresponds to the third pulse signal. For example, the clock signal B2 corresponds to the fourth pulse signal. The second selection circuit is
For example, it is configured by a selection circuit in the B1 / B2 signal generation block 12. The common clock signal corresponds to, for example, the system clock signal. The first signal output circuit is composed of, for example, the A1 / A2 signal generation block 11. The second signal output circuit is, for example,
It is configured by the B1 / B2 signal generation block 12.
Note that each component is not limited to the above configuration as long as the characteristic function of the present invention is not impaired.

[0029]

According to the drive circuit of the solid-state image pickup device of the present invention, it is possible to prevent the image quality from being deteriorated due to the timing deviation of the drive pulse signal.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a drive circuit for a solid-state image sensor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a waveform example of an input / output signal of a synchronization block.

FIG. 3 is a diagram showing a waveform example of a horizontal drive pulse signal.

[Explanation of symbols]

11,21 ... A1 / A2 signal generation block, 12,22 ...
B1 / B2 signal generation block, 13, 23 ... Synchronous block, 14, 24 ... Logic gate, 131, 13
2,231,232 ... D-flip flop

Claims (3)

[Claims] 1. A drive circuit for supplying a drive pulse signal to a solid-state image pickup device, which selects and outputs one of a first pulse signal and a second pulse signal different from the first pulse signal. A first selection circuit, a second selection circuit that selects and outputs one of a third pulse signal and a fourth pulse signal different from the third pulse signal, and the first selection circuit A synchronization circuit for synchronizing a pulse signal output from a circuit and a pulse signal output from the second selection circuit using a common clock signal, and the pulse signals synchronized by the synchronization circuit are each the solid-state imaging device. A drive circuit for a solid-state imaging device, which is supplied to the device. 2. A drive circuit for supplying a drive pulse signal to a solid-state image pickup device, wherein a toggle operation is performed at a rising edge of a basic clock signal to perform a first pulse signal and a second pulse having a phase opposite to the first pulse signal. A first signal output circuit for respectively generating pulse signals and selecting and outputting any one of the first pulse signal and the second pulse signal; and a toggle signal at a falling edge of the basic clock signal. An operation is performed to generate a third pulse signal and a fourth pulse signal having a phase opposite to that of the third pulse signal.
Second signal output circuit for selecting and outputting any one of the pulse signal and the fourth pulse signal, and the pulse signal output from the first signal output circuit and the second signal output. A solid-state imaging device, comprising: a synchronization circuit that synchronizes a pulse signal output from a circuit using a common clock signal, and supplies the pulse signals synchronized by the synchronization circuit to the solid-state imaging device. Drive circuit. 3. The drive circuit for a solid-state image pickup device according to claim 2, wherein the common clock signal is a clock signal having a frequency higher than that of the basic clock signal. circuit.