JP2001313874A - Camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a camera system that applies delay adjustment with high accuracy, without electrically changing a duty of an output pulse signal and optimizes a phase relation of each pulse signal so as to attain high image quality of a display image. SOLUTION: Output signals from a circuit, consisting of a 1st delay adjustment cell 19, a 1st inverter 20, a 2nd delay adjustment cell 21 and a 2nd inverter 22 where two sets each comprising a logical inverter circuit and a delay circuit are connected in cascade are outputted as pulse signals H1, H2, R, DS1, DS2 to take timing for drive control to a solid-state image pickup section and a signal processing section, by uniformizingdelay time with respect to each timing of rising and falling of the output signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a camera device which captures an image of an object by an imaging unit, and electrically processes an image signal from the imaging unit to generate a video signal of the object.

[0002]

2. Description of the Related Art Conventionally, a solid-state image pickup unit (for example, a CCD) comprising a plurality of photoelectric conversion elements (photodiodes or the like) arranged two-dimensionally in a matrix has been used as an image pickup unit for receiving light from a subject and taking an image. ) Or a camera system including a plurality of camera devices is widely used in both the industrial field and the consumer field.

In particular, in recent years, camera devices have become more multifunctional and have higher image quality, and the solid-state imaging section has also been increased in the number of pixels.
The frequency of the high-speed pulse for driving the solid-state imaging unit is increasing, and it is necessary to adjust the phase with high precision.

A driving LSI for driving the solid-state image pickup unit and the like
For the optimization, the phase is adjusted for the high-speed pulse for driving the CCD, which is a solid-state imaging unit, and for the pulse used for correlated double sampling of the imaging signal from the CCD in order to optimize the driving. Have been done.

[0005] Regarding the conventional camera device as described above,
This will be described below with reference to the drawings. FIG. 4 is a block diagram showing the overall configuration of a camera device described here as a conventional example. As shown in FIG. 4, the camera device includes a driving LSI 3, a voltage conversion LSI 4, which is a driving circuit unit for a solid-state imaging unit and the like, a solid-state imaging unit 5, which is an imaging unit, and a signal processing unit 6.
It consists of.

FIG. 5 is a block diagram showing the configuration of the solid-state imaging unit 5 used in the above-mentioned camera device. As shown in FIG. 5, the solid-state imaging unit 5 includes a photodiode 7, which is one of the photoelectric conversion elements, a vertical transfer unit 8, a horizontal transfer unit 9, and a charge detection unit 10. In FIG. 5, the photodiodes 7 and the vertical transfer units 8 are arranged one by one for the sake of simplicity, but in the actual solid-state imaging unit 5, it is assumed that the combinations are arranged by the number of horizontal CCDs.

FIG. 6 is a block diagram showing a configuration related to a high-speed pulse in the driving LSI 3. As shown in FIG. 6, this block (the driving LSI 3) includes a high-speed pulse generator 11, a delay adjuster 12, and an output buffer 2.

FIG. 7 is a waveform chart showing the operation of the camera apparatus as described above, and is a timing chart of various driving pulses (high-speed pulses) from the driving LSI 3 to the solid-state imaging unit 5 and the like. As shown in FIG. 7, various drive pulses composed of high-speed pulses include a reference clock 13, a horizontal transfer unit drive pulse (H1) 14, and a horizontal transfer unit drive pulse (H2) 1.
5, a reset pulse (R) 16, a correlated double sampling pulse (DS1) 17, and a correlated double sampling pulse (DS2) 18.

FIG. 3 shows the driving LSI 3 shown in FIG.
FIG. 3 is a block diagram illustrating a configuration of a phase adjustment unit that adjusts the phase of a high-speed pulse. As shown in FIG. 3, the phase adjustment unit is configured by a delay adjustment cell 1.

In the camera device shown in FIG. 4, various driving pulses are generated by the driving LSI 3 and the voltage conversion LSI 4 and input to the solid-state imaging unit 5, whereby an output of an imaging signal is obtained from the solid-state imaging unit 5. The signal processing unit 6 is used as a correlated double sampling unit to perform signal processing such as correlated double sampling and A / D conversion on the image pickup signal. A corresponding video signal is output.

High-speed pulses H1, H2, R, DS1, DS
2 is generated by the driving LSI 3. Among them, the high-speed pulses H1, H2, and R are directly applied to the solid-state imaging unit 5 to drive the solid-state imaging unit 5. Also, the high-speed pulse DS1,
DS2 is sent to the signal processing unit 6 for use in the correlated double sampling process.

Next, the drive control of the solid-state imaging unit 5 will be described. In the solid-state imaging unit 5 illustrated in FIG. 5, first, a high voltage (about 15 V) is applied to the vertical transfer unit 8 and charges are read from the photodiode 7 to the vertical transfer unit 8. Next, by inputting a vertical transfer pulse to the vertical transfer unit 8, the charge is transferred to the horizontal transfer unit 9. Further, the horizontal transfer unit 9
Then, by applying horizontal transfer section drive pulses H1 and H2, charges are transferred, and the charges are converted into image pickup signals by the charge detection section 10 and output. Here, the horizontal transfer section drive pulse H1 is applied to the final gate for transferring the electric charge. Each time a signal for one pixel is output, the charge detection unit 10 is reset by a reset pulse R.

In the solid-state imaging section 5, the phase relationship between the pulses H1 and H2 must be adjusted with high accuracy in order to efficiently transfer the charge of the signal. In addition, in order to reset the charge detection unit 10 at an appropriate timing that does not overlap with the output of the imaging signal, the phase relationship between the pulse H1 and the reset pulse R needs to be adjusted with high accuracy. is there. Further, in order to properly perform the correlated double sampling process, the phase relationship between the pulse H1 and the correlated double sampling pulse DS1 and the phase relationship between the reset pulse R and the correlated double sampling pulse DS2 are also required to be highly accurate. Adjustments need to be made.

The pulses H1, H2, R, DS1, DS
6 is generated by the high-speed pulse generation unit 11 of the driving LSI 3 as shown in FIG. 6, and is delayed from the output buffer 2 after passing through the delay adjustment unit 12.
It is output outside I3. Here, the pulse H1 is generated by dividing the reference clock 13 by two, and the pulse H1 is generated.
2 is generated by inverting the pulse H1. The pulses R, DS1, and DS2 are generated by extracting one portion from the reference clock 13 or an inverted version of the reference clock 13.

In the conventional delay adjusting section 12, these pulses are generated as pulses delayed by passing through the delay adjusting cell 1. As the delay adjustment cell 1, a cell having a delay time of about 0.02 ns is prepared, and high-precision delay adjustment can be performed by changing the wiring during layout. Used for delay adjustment before input. The delayed pulse passes through the output buffer 2 and is output to the outside of the driving LSI 3.

With this circuit, the delay time of the pulse can be adjusted with high accuracy. By performing the delay adjustment for the various drive pulses shown in FIG. 7 using the circuit of FIG.
The phase relationship between the drive pulses is adjusted, and these pulses are used as drive pulses for the solid-state imaging unit 5.

[0017]

However, in the above-described conventional method for adjusting a delay in a camera device, in order to perform delay adjustment with high accuracy, a delay adjustment cell 1 capable of performing the delay adjustment is used as a phase adjustment unit. However, when the phase adjustment unit is configured using the delay adjustment cell 1 in this manner, the input pulse signal has different delay characteristics at the rising and falling timings, so that the duty of the output pulse signal changes. However, the charge transfer of the horizontal transfer unit 9 of the solid-state imaging unit 5 is not completely performed, or a noise portion due to the reset pulse (R) 16 for the solid-state imaging unit 5 in the correlated double sampling unit which is the signal processing unit 6. Noise is superimposed on the video signal due to sampling up to the point where the image quality of the display image based on the video signal deteriorates, etc. The problem had.

The present invention solves the above-mentioned conventional problems, and can perform a delay adjustment with high precision without electrically changing the duty of the output pulse signal, and optimize the phase relationship between the pulse signals. The present invention provides a camera device capable of improving display image quality.

[0019]

In order to solve the above-mentioned problems, a camera device according to the present invention comprises a logic inversion circuit and a delay circuit as one set, and outputs signals from two sets of cascaded circuits.
The delay time for each of the rising and falling timings is made uniform and output as a pulse signal for setting the timing of drive control for the imaging unit and the signal processing unit.

As described above, highly accurate delay adjustment can be performed without electrically changing the duty of the output pulse signal, and the phase relationship between the pulse signals is optimized.
It is possible to improve the quality of a display image.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A camera device according to a first aspect of the present invention includes: an imaging unit configured to receive light from a subject and capture an image;
A signal processing unit that electrically processes an imaging signal output from the imaging unit; and a driving circuit unit that drives and controls the imaging unit and the signal processing unit. The signal processing unit is driven by the driving circuit unit. A camera circuit that generates a video signal of the subject from the first circuit; a first delay circuit to which a clock of an arbitrary cycle is input to the drive circuit unit;
A first logical inverting circuit having an input connected to the output of the delay circuit, a second delay circuit having an input connected to the output of the first logical inverting circuit, and an input connected to the output of the second delay circuit. A second logical inversion circuit connected thereto, and the drive circuit section outputs a signal output from the second logical inversion circuit by delay-adjusting the clock as a pulse signal for obtaining the timing of the drive control. The configuration is as follows.

The camera device according to the second aspect is the first aspect.
Is configured such that the delay times of the first delay circuit and the second delay circuit are equal. According to a third aspect of the present invention, in the camera device, the imaging unit according to the first or second aspect is a solid-state imaging unit including a plurality of photoelectric conversion elements arranged two-dimensionally in a matrix, and a signal processing unit. A correlated double sampling unit for performing correlated double sampling processing to reduce noise from an imaging signal from the solid-state imaging unit, and a driving circuit unit for driving the solid-state imaging unit and the correlated double sampling unit. Is output as each sampling pulse.

The camera device according to the fourth aspect is the first aspect of the invention.
4. The drive circuit unit according to claim 3, wherein each of the pulse signals for setting the drive control timing for the image pickup unit and the signal processing unit is supplied to each of the first delay circuit and the second delay circuit. The delay is adjusted to be at least the minimum delay amount among the amounts.

According to a fifth aspect of the present invention, there is provided a camera device according to the first aspect.
5. The driving circuit unit according to claim 1, further comprising a first delay circuit, a first logical inversion circuit, a second delay circuit, and a second delay circuit.
And a plurality of sets are cascade-connected as one set, and arbitrarily selected from output signals from the cascade connection section, and output as pulse signals for taking timing of drive control for the imaging section and the signal processing section. The configuration is as follows.

According to these configurations, the output signals from the two sets of cascade-arranged circuits, each of which includes a logic inversion circuit and a delay circuit, are equalized in delay time with respect to each of rising and falling timings. The signal is output as a pulse signal for setting the timing of drive control for the signal processing unit.

Hereinafter, a camera device according to an embodiment of the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a delay adjustment unit in a driving LSI in the camera device according to the present embodiment. 4 is a block diagram showing a general overall configuration of this type of camera device, FIG. 5 is a schematic block diagram showing a configuration of a solid-state imaging unit in the camera device of FIG. 4, and FIG. 6 is a block diagram of the camera device of FIG. FIG. 7 is a block diagram showing a configuration related to a high-speed pulse in the driving LSI. FIG. 7 is a timing chart of a solid-state imaging unit driving pulse showing an operation in the camera device of FIG. Since FIGS. 4 to 7 have been described in the related art, the description thereof is omitted here.

In the camera device of the present embodiment, high-speed pulses H1 and H1 are generated by using a driving LSI 3 as a driving circuit configured based on the block diagram shown in FIG.
2, R and delay adjustment for the high-speed pulses DS1 and DS2.

Driving LSI 3 in this camera device
As shown in FIG. 1, a first delay adjustment cell 19 as a first delay circuit, a first inverter 20 as a first logic inversion circuit, a second delay adjustment cell 21 as a second delay circuit,
It is configured by a second inverter 22 which is a second logic inversion circuit. Here, the first delay adjustment cell 19 and the second
The delay adjustment cells 21 are configured to have the same delay time, and have the same characteristics with respect to the delay time.
The first inverter 20 and the second inverter 22 also have the same electrical characteristics.

The circuit configuration of the present embodiment is configured by connecting two stages of the same combination of the delay adjustment cells 19 and 21 and the inverters 20 and 22. With such a configuration, the difference between the rising and falling delay times generated in the first delay adjustment cell 19 is determined by passing the logically inverted pulse through the second delay adjustment cell 21 further. It becomes 0. Further, by using two inverters having the same characteristics (inverters 20 and 22), the difference between the rise and fall delay time of the inverter itself becomes zero.

These delay adjustment cells 19 and 21 are prepared with cells having a delay time of about 0.02 ns, and the wiring is changed at the time of layout by using this as the minimum delay amount, and the delay adjustment cells 19 and 21 have a delay time of about 0.02 ns or more. By obtaining various delay times, highly accurate delay adjustment can be performed with a delay time of about 0.02 ns.

As described above, the camera apparatus according to the present embodiment enables a circuit configuration in which the duty of the output pulse does not change even when the delay is adjusted. Next, another configuration example of the camera device according to the embodiment of the present invention will be specifically described with reference to the drawings.

For example, when driving a plurality of types of solid-state imaging units, the optimum phase relationship of the high-speed pulse differs depending on the type of the solid-state imaging units. Therefore, a selector is used in the phase adjustment unit, and the driving L
In some cases, a delay adjustment circuit that adjusts the amount of delay in response to data input from outside the SI may be used.

A driving L having such a delay adjusting circuit
A camera device having an SI will be described below. FIG. 2 is a block diagram illustrating another configuration example of the camera device according to the present embodiment. As shown in FIG. 2, this camera device
A delay buffer 23 as a first and a second delay circuit, a selector 24, a first inverter 20 as a first logic inversion circuit, and a second inverter 22 as a second logic inversion circuit
It consists of.

The input pulse signal is supplied to the first inverter 20,
By passing a plurality of sets of delay adjustment circuits each including the second inverter 22 and two delay buffers 23, a plurality of types of pulse signals having various delay amounts are generated from a connection between the delay adjustment circuits. I do.

Thus, the delay buffer 23, the inverter 20, the delay buffer 23, and the inverter 22 (delay adjustment circuit (1)), the delay buffer 23, the inverter 20, the delay buffer 23, and the inverter 22 (delay adjustment circuit (2)) ,..., The duty of the output pulse signal does not change even when performing multi-stage delay adjustment. A pulse from each connection between these delay adjustment circuits is input to the selector 24,
A pulse having an arbitrary delay amount is selected and output by a selector control signal based on a data input from the outside of the driving LSI 3.

With the camera apparatus of the present embodiment as described above, it is possible to configure a circuit in which the duty of the output pulse does not change even when the delay is adjusted using the selector.

Here, the delay amount adjustment circuit using the delay adjustment cell has been described. However, the delay adjustment may be performed by a combination of buffers or other methods. In the present invention, the delay circuit is not particularly limited. Absent.

Further, the pulse for performing the delay adjustment is as follows.
The present invention is applicable to other than high-speed pulses, and is not particularly limited in the present invention. As described above, according to the camera device of the present embodiment, when delay adjustment is performed using the delay adjustment cell, or when delay adjustment is performed by external data input,
For the problem that the duty of the output pulse changes, without changing the duty of the output pulse,
The delay amount can be adjusted with high accuracy.

[0039]

As described above, according to the present invention, the output signals from two sets of cascaded circuits each including a logical inverting circuit and a delay circuit are set to a delay time with respect to each rising and falling timing. It can be output as a pulse signal for making the timing of drive control for the imaging unit and the signal processing unit uniform.

Therefore, the delay can be adjusted with high precision without electrically changing the duty of the output pulse signal, and the phase relationship between the pulse signals can be optimized to improve the quality of the displayed image. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a delay adjustment unit in a driving LSI in a camera device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing another configuration of the delay adjusting unit in the driving LSI in the camera device according to the embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a phase adjustment unit in a driving LSI in a conventional camera device.

FIG. 4 is a block diagram showing an overall configuration of a camera device described in the related art.

FIG. 5 is a schematic block diagram illustrating a configuration of a solid-state imaging unit in the camera device described in the related art.

FIG. 6 is a block diagram showing a configuration related to a high-speed pulse in a driving LSI in a conventional camera device.

FIG. 7 is a timing chart of a solid-state imaging unit driving pulse showing an operation in the camera device of the conventional example.

[Explanation of symbols]

 Reference Signs List 3 driving LSI 4 voltage conversion LSI 5 solid-state imaging unit 6 signal processing unit 7 photodiode 8 vertical transfer unit 9 horizontal transfer unit 10 charge detection unit 13 reference clock 14 horizontal transfer unit drive pulse (H1) 15 horizontal transfer unit drive pulse ( H2) 16 reset pulse (R) 17 correlated double sampling pulse (DS1) 18 correlated double sampling pulse (DS2) 19 first delay adjustment cell 20 first inverter 21 second delay adjustment cell 22 second inverter 23 delay Buffer 24 selector

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Shinichi Tashiro, Inventor Shinichi Tashiro 1-1, Yuukicho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. F-term (reference) 4M118 AA05 AB01 BA10 CA02 DB06 DD10 DD12 5C024 CX06 CY16 GY01 GZ01 HX02 HX03 HX15 HX53

Claims (5)

[Claims] An imaging unit configured to receive light from a subject to capture an image; a signal processing unit configured to electrically process an imaging signal output from the imaging unit; and a drive control unit configured to drive and control the imaging unit and the signal processing unit. A camera device that includes a drive circuit unit and generates a video signal of the subject from the signal processing unit under drive control by the drive circuit unit.
A first delay circuit to which a clock of an arbitrary cycle is input, a first logic inversion circuit having an input connected to the output of the first delay circuit, and an input connected to an output of the first logic inversion circuit A second delay circuit; and a second logic inversion circuit having an input connected to the output of the second delay circuit, and the drive circuit unit adjusts the clock by delaying the clock from the second logic inversion circuit. A camera device wherein the output signal is output as a pulse signal for setting the timing of the drive control. 2. The camera device according to claim 1, wherein the drive circuit section is configured such that delay times of the first delay circuit and the second delay circuit are equal. 3. An image pickup unit comprising a solid-state image pickup unit comprising a plurality of photoelectric conversion elements arranged two-dimensionally in a matrix, and a signal processing unit for reducing noise from an image pickup signal from the solid-state image pickup unit. A correlated double sampling unit for performing correlated double sampling processing, and a driving circuit unit configured to output each pulse for driving the solid-state imaging unit and for sampling in the correlated double sampling unit. The camera device according to claim 1 or 2, wherein 4. A drive circuit unit according to claim 1, wherein each of the pulse signals for setting the drive control timing for the imaging unit and the signal processing unit is at least the minimum of the delay amounts in the first delay circuit and the second delay circuit. 4. The camera device according to claim 1, wherein the delay is adjusted to be equal to or more than the delay amount. 5. A driving circuit unit comprising a first delay circuit, a first logic inversion circuit, a second delay circuit, and a second logic inversion circuit, which are cascade-connected as one set, and wherein the cascade connection unit comprises: 2. A pulse signal for arbitrarily selecting an output signal from the controller and outputting drive control timing for the imaging unit and the signal processing unit.
The camera device according to any one of claims 1 to 4.