JP2000324407A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify as much as possible the clock phase management against the video signals by using two types of sampling pulses of different phases which are generated to a correlative double sampling(CDS) control part as the reference clocks, converting the output signals of the CDS control part into the digital signals and processing these signals. SOLUTION: The video signals outputted from a CCD 1 perform the CDS processing at a CDS part 4 for every pixel via two types of sampling pulses having different phases in the feed-through and effective signal component periods respectively. The sampling pulse used at the part 4, i.e., the sampling pulse that is generated by a sampling pulse generation circuit 5 is used as a reference clock of an A/D converter 6 which converts the output signals of the part 4 into the digital signals. Furthermore, the reference clock of a digital signal processing part 7 which is placed at the next stage of the converter 6 also uses the sampling pulse of the circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an imaging apparatus in which the timing of a reference clock used in an A / D converter and a digital signal processing unit is easily adjusted.

[0002]

2. Description of the Related Art In recent years, image pickup apparatuses have been reduced in size and cost.

[0003] A conventional imaging device will be described below.

FIG. 3 shows a conventional image pickup apparatus. FIG. 3 shows a block diagram of a conventional imaging device. In FIG. 3, reference numeral 1 denotes a CCD which is a solid-state image sensor for converting an optical signal of an incident object into an electric signal, and 2 denotes a horizontal synchronization pulse Φ.
A horizontal CCD drive pulse generation circuit for generating H, a clock generation circuit for generating a clock, a CDS section as a correlated double sampling control section, and a sampling pulse generation for generating a sampling pulse used in the CDS section A / D converter 6 is an A / D converter which converts an analog signal from CDS unit 4 into a digital signal.
A converter 7 for processing a digital signal from the A / D converter 6; a clock 8 for adjusting the output clock of the clock generation circuit 3 in accordance with the timing of the output signal of the CDS unit 4 This is a timing adjustment circuit.

The operation of the conventional imaging apparatus having the above-described configuration will be described below with reference to FIGS.

FIG. 4 shows an example of a general CDS unit 4, FIG.
(A) is a horizontal synchronizing pulse, (b) is an output signal of the CCD 1, and (c) is a first sampling pulse S of the CDS unit 4.
P1, (d) is the second sampling pulse SP2,
(E) is an example of each waveform of the output signal of the CDS unit 4.

First, the CCD 1 outputs a video signal in a waveform as shown in FIG. 5A in accordance with the horizontal synchronizing pulse ΦH generated by the horizontal CCD driving pulse generating circuit 2. Next, as an example, the CDS unit 4 of the circuit as shown in FIG.
The feedthrough period of the output signal of the CCD1 is SP1 and the effective signal component period is SP2, and the correlated double sampling process is performed using two types of sampling pulses having different phases. FIG. 5E shows an example of a signal waveform after performing the correlated double sampling process.

At this time, SP1 and SP2 are generated by the sampling pulse generating circuit 5.
And a phase adjustment circuit that manages the AC timing between the video signal input to the input terminal and the sampling pulse.

Thereafter, the A / D converter 6 controls the CDS unit 4
Is converted into a digital signal. In order to minimize errors during this conversion, the clock output from the clock generation circuit 3 as a reference clock is adjusted in timing by a clock timing adjustment circuit 8.
Further, the clock whose timing has been adjusted is also used as a reference clock in the digital signal processing unit 7 arranged at the subsequent stage of the A / D converter 6.

[0010]

However, in the above-mentioned conventional configuration, the clock timing adjusting circuit has
There is a problem that the adjustment value needs to be determined in consideration of the following four factors. 1. Relative phase between the clock of the clock generation circuit output and ΦH of the horizontal CCD drive pulse circuit output. 2. Relative phase between φH and CCD output signal. 3. Relative phase between the clock output from the clock generation circuit and SP1 and SP2 output from the sampling pulse generation circuit. 4, SP1,
Relative phase between SP2 and CDS output signal.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide an imaging apparatus capable of making clock phase management for a video signal as simple as possible.

[0012]

In order to achieve this object, an image pickup apparatus according to the present invention comprises an image pickup device for converting an optical signal incident from a subject into an electric signal, and for driving the image pickup device in a horizontal direction. Horizontal CC that generates necessary pulses
D drive pulse generation means, clock generation means for generating a reference clock of the present apparatus, and correlated double sampling control means for performing correlated double sampling control for suppressing the noise component to the output signal of the image sensor as much as possible. , Two different phases with respect to the correlated double sampling control means.
Sampling pulse generation means for generating various types of sampling pulses, analog-to-digital conversion means for converting the output signal of the correlated double sampling control means to a digital signal using the sampling pulse as a reference clock,
Digital signal processing means for performing signal processing on an output signal of the analog-to-digital conversion means using the sampling pulse as a reference clock.

With this configuration, an effect is obtained in which the clock phase management for the video signal in the A / D converter and the digital signal processing unit is made as simple as possible.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to an image pickup device for converting an optical signal incident from a subject into an electric signal, and a pulse necessary for driving the image pickup device in a horizontal direction. Horizontal CCD driving pulse generating means for generating a clock, clock generating means for generating a reference clock of the present apparatus, and correlated double sampling control for performing correlated double sampling control in order to suppress a noise component to the output signal of the image sensor as much as possible. Sampling control means, sampling pulse generating means for generating two kinds of sampling pulses having different phases with respect to the correlated double sampling control means, and an output signal of the correlated double sampling control means using the sampling pulse as a reference clock. Analog-to-digital conversion means for converting the sampling pulse into a digital signal; Digital signal processing means for processing the output signal of the analog / digital conversion means, wherein the sampling pulse of the CDS section is used as a reference clock in an A / D converter and a digital signal processing section. Thus, the operation of making the clock phase management for the video signal in the A / D converter and the digital signal processing unit as simple as possible can be obtained.

An embodiment of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of an imaging apparatus according to Embodiment 1 of the present invention.
In FIG. 1, reference numeral 1 denotes a CCD which is a solid-state image pickup device for converting an optical signal of an incident object into an electric signal; A horizontal CCD driving pulse generating circuit as a pulse generating means; 3 a clock generating circuit as a clock generating means for generating a clock;
Reference numeral 4 denotes a CDS unit which is correlated double sampling control means for performing correlated double sampling on a signal from the CCD based on two types of sampling pulses SP1 and SP2 from the sampling pulse generation circuit 5, and 5 denotes a signal from the clock generation circuit 3. CDS unit 4 and A / D converter 6 based on clock
And a sampling pulse generating circuit which is a sampling pulse generating means for generating a sampling pulse used in the digital signal processing unit 7, the first sampling pulse SP1 and the second sampling pulse S2 having different phases from each other.
Generates P2. Reference numeral 6 denotes an A / D converter which is an analog / digital converter for converting an analog signal from the CDS unit 4 into a digital signal, and reference numeral 7 denotes a digital signal processing means for variously processing the digital signal from the A / D converter 6. It is a digital signal processing unit.

FIG. 4 shows an example of a general CDS unit 4, FIG.
(A) is a horizontal synchronizing pulse, (b) is an output signal of the CCD 1, and (c) is a first sampling pulse S of the CDS unit 4.
P1, (d) is the second sampling pulse SP2,
(E) is an example of each waveform of the output signal of the CDS unit 4.

The operation of the imaging apparatus according to the present embodiment configured as described above will be described below.

First, the CCD 1 outputs a video signal with a waveform as shown in FIG. 5A in accordance with the horizontal synchronizing pulse ΦH generated by the horizontal CCD drive pulse generating circuit 2. Next, the video signal output from the CCD 1 is subjected to a feedthrough period of the output signal of the CCD 1 by SP1 (FIG. 5 (c)) in the CDS unit 4 comprising a circuit as shown in FIG.
Correlation double sampling processing is performed for each pixel in the effective signal component period with two types of sampling pulses having different phases as shown in SP2 (FIG. 5D). FIG. 5E shows an example of a signal waveform after performing the correlated double sampling process.

At this time, SP1 and SP2 are generated by the sampling pulse generation circuit 5, and this circuit includes a phase adjustment circuit for managing the AC timing between the video signal input to the CDS unit 4 and the sampling pulse. ing.

The output signal of the CDS unit 4 is supplied to an A / D converter 6
In this case, the reference clock in the A / D converter 6 uses the sampling pulse used in the CDS unit 4, that is, the sampling pulse from the sampling pulse generation circuit 5. Further, the sampling clock from the sampling pulse generation circuit 5 is also used as the reference clock of the digital signal processing unit 7 arranged at the subsequent stage of the A / D converter 6.

As described above, according to the first embodiment, the A / D converter and the clock timing adjustment circuit required as the clock of the digital signal processing unit required in the prior art can be eliminated, and the cost can be reduced. Downs and the circuit scale (or the number of parts) can be reduced. Further, the sampling pulse of the CDS unit 4 and the reference clock of the A / D converter 6 and the digital signal processing unit 7 are processed by the same pulse, so that the timing of the video signal and the clock in the subsequent block after the CDS unit 4 is processed. Management is unified and a simple system can be configured.

(Embodiment 2) FIG. 2 is a block diagram of an imaging apparatus according to Embodiment 2 of the present invention. 2 is different from the configuration of FIG. 1 in that an AGC circuit 9 which is a gain control means capable of changing a gain by adapting an output signal of the CDS unit 4 to a signal level is different from the AGC circuit 9 in FIG. And a point that a sampling pulse delay circuit 10 as sampling pulse delay means for delaying a sampling pulse used in the CDS unit 4 by a delay in the AGC circuit 9 is provided.

The operation of the imaging apparatus of the present embodiment configured as described above will be described below.

First, the CCD 1 outputs a video signal in a waveform as shown in FIG. 5A in accordance with the horizontal synchronizing pulse ΦH generated by the horizontal CCD drive pulse generating circuit 2. Next, the video signal output from the CCD 1 is subjected to a feedthrough period of the output signal of the CCD 1 by SP1 (FIG. 5 (c)) in the CDS unit 4 comprising a circuit as shown in FIG.
Correlation double sampling processing is performed for each pixel in the effective signal component period with two types of sampling pulses having different phases as shown in SP2 (FIG. 5D). FIG. 5E shows an example of a signal waveform after performing the correlated double sampling process.

At this time, SP1 and SP2 are generated by the sampling pulse generation circuit 5, and this circuit includes a phase adjustment circuit for managing the AC timing between the video signal input to the CDS unit 4 and the sampling pulse. ing.

The output signal of the CDS unit 4 is input to an AGC circuit 9, adjusted to a predetermined gain, and converted to a digital signal by an A / D converter 6. At this time, a sampling clock output from the sampling pulse generation circuit 5 and delayed by the delay in the AGC circuit 9 by the sampling pulse delay circuit 10 is used as a reference clock in the A / D converter 6. Further, a sampling pulse from the sampling pulse delay circuit 10 is also used as a reference clock of the digital signal processing unit 7 arranged at a stage subsequent to the A / D converter 6.

In this configuration, as shown in FIG. 2, an AGC circuit for applying a gain to a video signal according to a signal level after a CDS unit (correlated double sampling processing) is provided. In the case where the sampling pulse of the CDS unit 4 is used as the reference clock of the A / D converter 6 and the digital signal processing unit 7 as in the first embodiment, the video signal is naturally delayed by the AGC circuit. It is necessary to delay the sampling pulse by that much. This delay control is performed by the sampling pulse delay circuit 1
Control at 0.

As described above, according to the present embodiment, AG
Since the set value of the delay amount in the C circuit 9 only needs to consider the AGC circuit, a system capable of simple clock management can be configured.

[0030]

As described above, conventionally, the sampling pulse used in the CDS section and the reference clock used in the A / D converter and digital signal processing are generated separately, so that the timing control for the video signal is performed. In the present invention, since the reference clock used in the A / D converter and digital signal processing uses the sampling pulse of the CDS unit, the timing management with the video signal can be easily realized. The excellent effect that can be obtained is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an imaging device according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram of an imaging device according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional imaging device.

FIG. 4 is a circuit diagram showing an example of the correlated double sampling circuit according to the present invention and the related art.

FIG. 5: ΦH pulse, CCD output signal, SP1, SP2
Each waveform diagram of pulse and CDS part output signal

[Explanation of symbols]

 Reference Signs List 1 CCD 2 horizontal CCD drive pulse generating circuit 3 clock generating circuit 4 CDS section 5 sampling pulse generating circuit 6 A / D converter 7 digital signal processing section

Claims (2)

[Claims] 1. An image pickup device for converting an optical signal incident from a subject into an electric signal, a horizontal CCD driving pulse generating means for generating a pulse necessary for driving the image pickup device in a horizontal direction, A clock generating means for generating a reference clock, a correlated double sampling control means for performing correlated double sampling control for suppressing a noise component to an output signal of the image sensor infinitely, and a correlated double sampling control means. Sampling pulse generating means for generating two kinds of sampling pulses having different phases, analog / digital converting means for converting an output signal of the correlated double sampling control means to a digital signal using the sampling pulse as a reference clock, and Using the pulse as a reference clock, the output of the An image pickup apparatus comprising: digital signal processing means for performing signal processing on a force signal. 2. An image pickup device for converting an optical signal incident from a subject into an electric signal, a horizontal CCD drive pulse generating means for generating a pulse necessary for driving the image pickup device in a horizontal direction, A clock generating means for generating a reference clock, a correlated double sampling control means for performing correlated double sampling control for suppressing a noise component to an output signal of the image sensor infinitely, and a correlated double sampling control means. Sampling pulse generating means for generating two types of sampling pulses having different phases; gain control means for adjusting the gain of the video signal from the first-generation double sampling pulse control means; and sampling pulse from the sampling pulse generating means. Sampling pulse delay means for delaying a predetermined time, and the sampling pulse Analog-to-digital conversion means for converting the output signal of the gain adjustment means into a digital signal using the sampling pulse from the delay means as a reference clock,
An image pickup apparatus comprising: a digital signal processing unit that performs signal processing on an output signal of the analog-to-digital conversion unit using a sampling pulse from the sampling pulse delay unit as a reference clock.