JP2000013691A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a solid-state image pickup device, also to prevent a signal level from deteriorating and to make noise low by performing correlation double sampling of an output signal of the solid-state image pickup device by means of digital processing and eliminating noise. SOLUTION: An output signal of an input frame memory 12a is supplied to a data bus 12b. A digital signal processing circuit 12 is controlled by a CPU 12c. A digital signal processor (DSP) 12f for signal processing which performs signal processing according to a program stored in a memory 12d for operation and an instruction memory 12e is connected to the bus 12b and performs prescribed signal processing. And, in this device, the circuit 12 digitally performs correlation double sampling of an output signal of a solid-state image pickup device 1 and eliminates noise. Because of that, a program through which correlation double sampling is digitally performed is stored in the memory 12e.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device using a solid-state imaging device.

[0002]

2. Description of the Related Art Generally, a solid-state imaging device (video camera) using a solid-state imaging device using a CCD, for example, as shown in FIG.
The following has been proposed.

Referring to FIG. 3, in FIG. 3, reference numeral 1 denotes a solid-state imaging device using a CCD.
A predetermined bias voltage is supplied from a bias power supply input terminal 1a to the solid-state imaging device 1 using a CD, and a predetermined drive pulse is supplied from a drive pulse input terminal 1b.

The reset pulse and the readout pulse generated by the timing signal generation circuit 2 are supplied to the solid-state imaging device 1 so that the solid-state imaging device 1 is operated as is well known.

As shown in FIG. 4, an output signal of the solid-state imaging device 1 is obtained in which a reset period t _R , a zero level period t ₀ of feedthrough, and a signal period t _S are repeated. In this case, the noise (noise) included in the 0-level period t ₀ of the feedthrough and the noise included in the signal period t _s have the same correlation.

An output signal as shown in FIG. 4 obtained at the output side of the solid-state imaging device 1 is supplied via an amplifier 3 to a correlated double sampling (CDS) circuit 4 for removing reset noise. An analog signal is converted into a digital signal through an amplifier 5 for adjusting an input range of an A / D conversion circuit 6 described later on a video signal from which noise obtained at the output side of the correlated double sampling circuit 4 has been removed. The signal is supplied to the AD conversion circuit 6. A predetermined clock signal is supplied from the timing signal generation circuit 2 to the AD conversion circuit 6.

The digital video signal obtained at the output side of the A / D conversion circuit 6 is supplied to and stored in an input frame memory 7a constituting a digital signal processing circuit 7. The output signal of the input frame memory 7a is supplied to the data bus 7b. The digital signal processing circuit 7 is controlled by a microcomputer (CPU) 7c. The data bus 7b has a digital signal for signal processing for signal processing according to programs stored in an operation memory 7d and an instruction memory 7e. A processor (DSP) 7f is connected and performs predetermined signal processing.

A digital video output circuit 7g is connected to the data bus 7b so that a digital video signal subjected to predetermined signal processing is obtained at an output terminal 8.

[0009]

[Problems that the Invention is to Solve The conventional correlated double sampling circuit 4 to remove the reset noise of the solid-state imaging device as shown in FIG. 3, sample the feedthrough level (t ₀ period) for each output of each pixel A sampling and holding circuit 4a for holding and a sampling and holding circuit 4 for sampling and holding a signal level (t _S period)
b, a sampling and holding circuit 4c for sampling and holding the output signal of the sampling and holding circuit 4a in the same phase as the sampling and holding circuit 4b, and
Sampling and holding circuits 4d and 4 for shaping the waveforms of the respective output signals of sampling and holding circuits 4b and 4c
e, and a differential amplifier 4f that outputs a signal level from the difference between the sampling and holding circuits 4d and 4e.

The correlated double sampling circuit 4 is composed of a combination of single analog parts such as the five sampling and holding circuits 4a to 4e and the differential amplifier 4f as described above. Had become a bottleneck.

The sampling and holding circuit 4a #
The problem of signal level accuracy degradation due to the occurrence of droop and the like in 4e and the circuit noise due to the complicated circuit configuration as described above could not be ignored.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to reduce the size of a solid-state imaging device, prevent deterioration in signal level accuracy, and reduce noise.

[0013]

The solid-state imaging device according to the present invention is configured so that the output signal of the solid-state imaging device is correlated double-sampled by digital processing to remove noise.

According to the present invention, since the output signal of the solid-state image sensor is correlated double-sampled by digital processing to remove noise, the circuit configuration becomes complicated because a plurality of sampling and holding circuits are not used. Therefore, the solid-state imaging device can be reduced in size and noise can be reduced, and there is no problem peculiar to an analog circuit such as droop of a sampling and holding circuit, and signal level accuracy does not deteriorate.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a solid-state imaging device according to the present invention will be described below with reference to FIGS. FIG.
In FIG. 3, the portions corresponding to FIG.

In FIG. 1, reference numeral 1 denotes a solid-state imaging device using a CCD. A predetermined bias voltage is supplied to the solid-state imaging device 1 from a bias power input terminal 1a and a predetermined driving pulse is supplied from a driving pulse input terminal 1b. Supply. In addition, the solid-state imaging device 1 generates the reset pulse and the readout pulse generated by the timing signal generation circuit 2.
To operate the solid-state imaging device 1 in a known manner.

As shown in FIG. 4, on the output side of the solid-state imaging device 1, an output signal in which a reset period t _R , a zero level period t ₀ of feedthrough, and a signal period t _S are repeated is obtained. In this case, the noise (noise) included in the 0 level period t ₀ of the feedthrough and the noise included in the signal period t _S have the same correlation.

An output signal as shown in FIG. 4 obtained at the output side of the solid-state imaging device 1 is supplied to a sampling and holding circuit 10 via an amplifier 3. The sampling and holding circuit 10 sequentially repeats the feed-through level (period t ₀ ) and the signal level (period t _s ) of the output signal of the solid-state imaging device 1 according to the sampling and holding clock signal from the timing signal generation circuit 2, and performs sampling. Make it hold.

The feed-through level (period t ₀ ) and the signal level (period t ₀ ) of the output signal of the solid-state image sensor 1 that the sampling and holding circuit 10 samples and holds.
_S ) is supplied to an A / D conversion circuit 11 for converting an analog signal into a digital signal, and is converted into a feed-through level (period t ₀ ) and a signal level (period t _s ) of the output signal. The digital signal is sequentially converted to a digital signal and supplied to and stored in an input frame memory 12a constituting the digital signal processing circuit 12.

This sampling and holding circuit 10 and A
A predetermined clock signal from the timing signal generation circuit 2 is supplied to the -D conversion circuit 11 so that the phase of the reset pulse and the readout pulse supplied from the timing signal generation circuit 2 to the solid-state imaging device 1 are adjusted.

The output signal of the input frame memory 12a is supplied to the data bus 12b. The digital signal processing circuit 12 includes a microcomputer (CPU) 1
A digital signal processor (DSP) for processing a signal in accordance with programs stored in an operation memory 12d and an instruction memory 12e is provided on the data bus 12b.
12f is connected to perform predetermined signal processing.

In this embodiment, the digital signal processing circuit 12 digitally performs correlated double sampling to remove noise. Therefore, the digitally correlated double sampling program is stored in the instruction memory 12e.

In the present embodiment, a correlated double sampling (CDS) process using the feed-through level and signal level of each pixel of the output signal of the solid-state imaging device 1 for "address 1" of the instruction memory 12e is performed. Correlation double sampling (CDS) using a feed-through level obtained by sampling this feed-through level once in one horizontal period and a signal level for each pixel is stored in "address 2" at a program and other signal processing programs. ) And a signal processing program, and a correlation using a feed-through level obtained by sampling the feed-through level once in one vertical period and a signal level of each pixel in “address 3”. Double sampling (CDS) processing program and others Stores a program signal processing,
A program for only other signal processing is stored in "address 4".

In the present embodiment, "address 1", "address 2", "address 3" and "address 4" stored in the instruction memory 12e can be arbitrarily selected. Let's do it.

The digital correlated double sampling process of the digital signal processing circuit 12 when "address 1" of the instruction memory 12e is selected is shown in FIG.
This is performed according to the flowchart shown in FIG. That is,
The feedthrough level of the n-th pixel of the solid-state imaging device 1 (t
₀ period) is sampled and held by the sampling and holding circuit 10 and is converted into a digital signal by the A / D conversion circuit 11, and this digital signal is input to the input frame memory 1
The data is stored in the feed-through level storage unit of the operation memory 12d via 2a (step S1).

Next, the signal level (t _S period) of the n-th pixel is sampled and held by a sampling and holding circuit 10 and converted into a digital signal by an A / D conversion circuit 11, and this digital signal is converted into an input frame memory 12a.
Is stored in the signal level storage unit of the operation memory 12d via the memory (step S2).

Next, the signal level is obtained by subtracting the feedthrough level of the nth pixel from the signal level of the nth pixel stored in the operation memory 12d by a signal processing digital signal processor (DSP) (step S3). The digitally correlated double sampling process for the n-th pixel is terminated (step S4). In this example, the above is repeated for each pixel.

When the "address 2" of the instruction memory 12e is selected, the digital correlated double sampling processing is performed in the above-described feed-through level storage section of the operation memory 12d once every one horizontal period. Is updated and stored, and the feedthrough level stored in the calculation memory 12d is subtracted from the signal level for each pixel, and the others are the same as described above.

In the digital correlated double sampling process when "address 3" of the instruction memory 12e is selected, the feedthrough level is stored in the feedthrough level storage section of the operation memory 12d once every vertical period. It is updated and stored, and the feedthrough level stored in the operation memory 12d is subtracted from the signal level for each pixel, and the others are the same as described above.

In this case, when any one of "address 1", "address 2", "address 3", and "address 4" is selected, similar processing is performed for other processes.

A digital video output circuit 12g is connected to the data bus 12b so that a digital video signal subjected to the predetermined signal processing is obtained at the output terminal 8.

According to this embodiment, since the output signal of the solid-state image sensor 1 is correlated double-sampled by digital processing to remove noise, there is no need to use a plurality of sampling and holding circuits and the like. Since the device can be miniaturized and the circuit configuration is not complicated, no circuit noise is generated and the noise can be reduced.

Further, according to this embodiment, since a plurality of sampling and holding circuits are not used, there is no problem peculiar to an analog circuit such as droop, and the accuracy of the signal level is not degraded.

The present invention is not limited to the above embodiment,
It goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0035]

According to the present invention, the output signal of the solid-state imaging device is correlated double-sampled by digital processing to remove noise, so that a plurality of sampling and holding circuits are not used, so that the circuit configuration is complicated. Therefore, there is an advantage that the solid-state imaging device can be reduced in size and noise can be reduced, there is no problem peculiar to an analog circuit such as a droop of a sampling and holding circuit, and the accuracy of a signal level does not deteriorate.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an example of an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a flowchart for explaining the present invention.

FIG. 3 is a configuration diagram illustrating an example of a conventional solid-state imaging device.

FIG. 4 is a diagram illustrating an example of an output signal of a solid-state imaging device.

[Explanation of symbols]

1 solid-state imaging device, 2 timing signal generation circuit,
8 ‥‥ output terminal, 10 ‥‥ sampling hold circuit,
11 ‥‥ AD converter circuit, 12 ‥‥ digital processing circuit,
12a input frame memory, 12b data bus, 12c microcomputer, 12d operation memory, 12e instruction memory, 12
Digital signal processor for signal processing, 12g
‥‥ Digital video output circuit

Claims (4)

[Claims] 1. A solid-state imaging device wherein output signals of a solid-state imaging device are correlated double-sampled by digital processing to remove noise. 2. The solid-state imaging device according to claim 1, wherein the sampling of the feedthrough level of the correlated double sampling in the digital processing is performed for each horizontal line. 3. The solid-state imaging device according to claim 1, wherein the sampling of the feedthrough level of the correlated double sampling of the digital processing is performed for each frame. 4. The solid-state imaging device according to claim 1, further comprising means for selecting whether or not to perform correlated double sampling of said digital processing.