JPH04322560A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To improve the quantization accuracy of an A/D converter used for video signal processing such as a video camera by one bit. CONSTITUTION:The processing circuit is provided with a solid-state image pickup element (CCD) 1 converting a picked-up optical image into an electric signal, 1st and 2nd sample-and-hold circuits 2,3 sampling and holding an output signal S1 of the CCD1 and 8-bit 1st and 2nd A/D converters 4, 5 quantizing respective output signals S2, S3. First and second adder means 10, 11 comprising latch circuits 6, 7 and adder circuits 8,9 process addition of a data of n-th clock and a data of (n+1)th clock (n is an optional integer) of respective output signals S4, S5 and output signals S8, S9 of the 1st and 2nd adder means 10,11 are selected and one system of digital signal S10 is outputted.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit used in video cameras and the like.

0002

[Prior Art] Digitizing video cameras can be expected to have benefits such as a reduction in the number of parts, a reduction in adjustment processes, improved stability, higher image quality, and higher functionality. There are certain considerations, such as the quantization accuracy of the analog-to-digital (A-D) converter. Conventionally, when quantizing the output signal of a camera's image sensor (e.g. CCD), higher quantization accuracy was required compared to other video equipment due to the need for gamma correction and the dynamic range of the signal. 9-1 as shown in A)
A method of linear quantization with a 0-bit A-D converter 102, or a method of linear quantization with a 0-bit A-D converter 102, or a method of performing correction with a gamma correction circuit 103 by analog processing as shown in FIG.
A method is known in which quantization is performed using 0.04, resulting in non-linear quantization. In addition, 100 is CCD, 101 is sample
This is a hold circuit.

0003

[Problem to be Solved by the Invention] Among the conventional techniques, the former has the problem that the power consumption of the high bit A-D converter is large and the cost increases. . In the latter case, although the problems of power consumption and cost can be solved, color multiplexed CC
It becomes necessary to perform gamma correction processing on the D output signal, which tends to cause image quality deterioration such as deterioration of phase characteristics and generation of color false signals.
Another problem is that a high-band gamma correction circuit is also required on a separate chip.

0004

[Means for Solving the Problems] The present invention to solve the above-mentioned problems includes a solid-state image sensor that converts an optical image to be captured into an electrical signal, and an output signal of the solid-state image sensor that converts the output signal of the solid-state image sensor into a driving clock of the solid-state image sensor. a first sample/hold means for sampling and holding with a sample pulse having a frequency of 1/2; and a sample pulse having the same frequency as that of the first sample/hold means but having a phase different by 180° from the solid-state image pickup device. a second sample hold that samples and holds the output signal of
a first analog-to-digital conversion means for quantizing the output signal of the first sample and hold means with a clock having the same frequency as a driving clock of the solid-state image sensor; and a second sample and hold means. a second analog-to-digital conversion means for quantizing the output signal of the means at the same clock as the first analog-to-digital conversion means; and n-th clock data of the output signal of the first analog-to-digital conversion means; (n+1) clock data (n is an arbitrary integer); and the output signal of the second analog-to-digital conversion means, the n clock data and (n+1) clock data.
+1) second addition means for adding clock-th data;
The apparatus is composed of data selection means for selecting the output signals of the first addition means and the second addition means at the same frequency as the driving clock of the solid-state image sensor and outputting one system of digital signals. Further, a correlated double sampling (CDS) circuit may be used for the first sample and hold means and the second sample and hold means.

[0005]

[Operation] The quantization accuracy is improved by 1 bit in terms of equalization.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a video signal processing circuit according to the present invention, and FIG. 2 is a timing chart.

The video signal processing circuit has a first circuit that samples and holds the output signal S1 of the CCD 1, which is a solid-state image sensor.
and the second sample/hold circuits 2 and 3, and the first and second
The output signals S2 of sample and hold circuits 2 and 3 of
, S3 of the 8-bit first and second A-D converters 4 and 5, and n clocks of the output signals S4 and S5 of the first and second A-D converters 4 and 5, respectively. Eye data and (n+1
) first and second addition means 10 and 11 consisting of latch circuits 6 and 7 and adder circuits 8 and 9 for adding clock-th data (n is an arbitrary integer); Means 10,1
The data selection circuit 12 selects one output signal S8, S9 and outputs one system of digital signal S10.

[0008] The first sample and hold circuit 2 is a CCD1
The second sample and hold circuit 3 samples and holds the output signal S1 of the CCD 1 with a sample pulse SP1 having a frequency of 1/2 of the driving clock CP.
The output signal S1 of the CCD 1 is sampled and held using a sample pulse SP2 having the same frequency as P1 and a phase difference of 180°. The first and second A-D converters 4 and 5 are each CCD
1 drive clock CP1 and a clock CP2 of the same frequency.
The output signals S2 and S3 of the first and second sample-and-hold circuits 2 and 3 are quantized.

In the first and second addition means 10 and 11, both the latch circuits 6 and 7 are connected to the first and second AD converters 4 and 5 using a common clock CP2, respectively. A of
- The output signals S4 and S5 of the D converters 4 and 5 are delayed by one clock, and then the adder circuits 8 and 9 output the data before and after the delay to the first and second A-D converters 4 and 5. output signal S4,
S5 and output signals S6 and S7 of latch circuits 6 and 7 are added to output signals S8 and S9. Furthermore, the data selection circuit 12 arranges the output signals S8 and S9 of the first and second addition means 10 and 11 in a desired arrangement at the same frequency as the driving clock CP1 of the CCD 1, and outputs a digital signal S10.

The operation of the video signal processing circuit configured as described above will be explained with reference to FIG. A, B, C, D, . . . shown in the output signal S1 of the CCD 1 correspond to each pixel signal. The first sample/hold circuit 2 has a sample pulse SP1
is supplied, among the pixel signals of the output signal S1 of the CCD 1, B, D, F, H, etc. are sampled and each data
The data is held over two pixels and a signal S2 is output. Similarly, when the second sample/hold circuit 3 is supplied with the sample pulse SP2, it samples A, C, E, G, etc. of the pixel signals of the output signal S1 of the CCD 1 and outputs each data. Two pixels are held and a signal S3 is output.

The output signals S2 and S3 are quantized by the first and second AD converters 4 and 5, respectively, using a clock CP2 having the same frequency as the driving clock CP1 of the CCD 1, and are converted into signals S4 and S5.
becomes. Here, even if the same analog data A is quantized, a difference between A and A' occurs in the digital data. This A and A'
The difference is due to linearity error in A-D conversion, and is usually at most ±1/2 LSB.

Output signals S4 and S5 of the first and second A/D converters 4 and 5 are delayed by one clock in latch circuits 6 and 7, respectively, to become signals S6 and S7, and further outputted in adder circuits 8 and 9, respectively. The signals S4 and S5 before and after the delay and the signals S6 and S7 are added to become the signals S8 and S9. From these signals S8 and S9, pairs A+A', B+B', C+C', . . .
The signal S10 is obtained by rearranging the data in the data select circuit 12 in the following order. By adding the same data in the signal S10, the original quantization error is compressed to a 1/2 error, and the quantization accuracy is equivalently improved by 1 bit.

[0013] The subsequent digital circuit for processing the signal S10 can be included in the process IC of the video camera, and the scale of the overall digital process is hardly increased.

FIG. 3 shows the first and second sample-and-hold circuits 2 and 3 in FIG.
S) This is a configuration diagram in which circuits 20 and 21 are replaced, and other components are the same. FIG. 4 shows the output signal S1 of the CCD 1 and the CDS circuit 20, 21 when the CDS circuits 20 and 21 are used.
21 is a timing chart of each pulse.

The output signal S1 of the CCD 1 is a combination of the original signal and the reset noise at the time of signal detection. Therefore, first, the feedthrough period in which only reset noise appears in the output signal S1 of CCD1 is controlled by clamp pulses FCP1 and FC.
After clamping at P2, the signal period in which the signal and reset noise are superimposed in the output signal S1 is sampled and held using sample and hold pulses CDS1 and CDS2, and the difference between the two is taken to suppress the reset noise. are doing. This makes it possible to achieve the effect of improving the SN ratio (signal-to-noise ratio) inherent in CDS, as well as to achieve block sharing, and to simplify the overall configuration.

[0016]

As described above, according to the present invention, it is possible to construct a video signal processing circuit whose quantization accuracy is improved by one bit. Furthermore, even if digital processing is included in the subsequent stage, lower costs and lower power consumption can be achieved than in the case of using a high-bit A-D converter.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a video signal processing circuit according to the present invention.

[Figure 2
] Timing chart of the video signal processing circuit according to the present invention

[Figure 3] Main part configuration diagram in which the sample-and-hold circuit in Figure 1 is replaced with a correlated double sampling (CDS) circuit

[Figure 4] Timing chart in Figure 3

[Figure 5] (A
) and (B) are configuration diagrams of conventional technology.

[Explanation of symbols]

1...CCD (solid-state image sensor), 2, 3...sample hole
field circuit, 4, 5... A-D converter, 10, 11... addition means, 12... data selection circuit, 20, 21... correlated double sampling (CDS) circuit, CP1... CCD drive clock, CP2...A -D converter clock, S1...CC
D output signal, S2, S3...output signal of sample/hold circuit, S4, S5...output signal of A-D converter, S8
, S9... Output signal of the adding means, S10... Output signal of the data selection circuit.

Claims (2)

[Claims] 1. A solid-state image sensor that converts an optical image to be captured into an electrical signal, and an output signal of the solid-state image sensor that is sampled and held using a sample pulse having a frequency of 1/2 of a driving clock of the solid-state image sensor. a first sample/hold means for sampling and holding the output signal of the solid-state image sensor using a sample pulse having the same frequency as that of the first sample/hold means but having a phase different by 180°; holding means; first analog-to-digital conversion means for quantizing the output signal of the first sample and hold means with a clock having the same frequency as the driving clock of the solid-state image sensor; - second analog-to-digital conversion means for quantizing the output signal of the second analog-to-digital conversion means at the same clock as the first analog-to-digital conversion means; and n-th clock data of the output signal of the first analog-to-digital conversion means. and (n+1)th clock data (n is an arbitrary integer);
a second adding means for adding the data of the data and the data of the (n+1)th clock, and output signals of the first adding means and the second adding means are selected at the same frequency as the drive clock of the solid-state image sensor to form one system. 1. A video signal processing circuit comprising: data selection means for outputting a digital signal. 2. Correlated double sampling (C
2. The video signal processing circuit according to claim 1, using a DS) circuit.