JPH0335672A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To make relation optimum between the output signal of an image senor and a pulse for correlative double sampling (CDS) circuit by generating the pulse for CDS circuit while controlling the pulse width of a horizontal reset pulse and a horizontal transfer pulse beng an output from the horizontal driving circuit of the image sensor. CONSTITUTION:A pulse generating circuit 6 generates the single pulse by execut ing phase adjustment and waveform shaping to a horizontal reset pulse OHR and a horizontal transfer pulse OH2, which are the outputs of a horizontal driving circuit 5, and generates a pulse for CDS circuit 8 suitable for the output signal of an image sensor 1 while controlling the pulse width by a delay circuit 20. Thus, the pulse for CDS circuit 8 can be easily generated to be applied for the image sensor with any number of picture elements and suitable for the output signal of the image sensor 1.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is directed to noise components of an output signal of a solid-state image sensor (image sensor), which has a period in which a signal is output and a period in which a signal is not output in at least one bit. , correlation 2
The present invention relates to a solid-state imaging device that uses a double sampling circuit (hereinafter abbreviated as a CDS circuit) to eliminate noise.

[Conventional technology]

FIG. 5 is a block diagram showing the configuration of a conventional solid-state imaging device. In FIG. 5, (1) is an image sensor;
2) is a timing generator, (3) is a synchronization signal generation circuit, and (4) receives vertical drive signals (Vl) to (V4) from the timing generator (2) to drive a vertical register in the image sensor (1). a vertical drive circuit that supplies vertical transfer pulses (OVl) to (OV4) for
(5) receives the horizontal drive signals (Hl), (H2) and reset signal (HR) from the timing generator (2) and generates a horizontal transfer pulse (OH1) for driving the horizontal register in the image sensor (1). , (OH2) and a horizontal drive circuit that supplies the horizontal reset pulse (OHR), (7) is the output terminal for the video signal output from the image sensor (1), and (8) is the video input from the output terminal (7). CDS circuit that removes the noise component of the signal (9
) is the output terminal of the CDS circuit (8).

FIG. 6 is a block diagram showing the configuration of the CDS circuit (8). In FIG. 6, (24) is an input terminal for a signal sample and hold pulse that samples and holds the signal component of the human input signal, and (25) is an input terminal for the human input signal. Noise sample and hold pulse input terminal that samples and holds the noise component of
(26) is a signal input terminal, (27), (28)
, (29) is a sample and hold circuit, (30) is a subtracter that subtracts the signals of the sample and hold circuits (28) and (29), and (31) is a buffer circuit that outputs to the output terminal (9).

Next, the operation will be explained. The video signal (optical signal) accumulated in the image sensor (1) is sent to the vertical drive circuit (4).
) from the vertical transfer pulses (OVl) to (OV4) and the horizontal transfer pulse (OHI) from the horizontal drive circuit (5).
) and (OH2), the signal is sequentially transferred in the vertical and horizontal directions and extracted as an electrical signal.

At this time, the noise component described in, for example, Japanese Patent Publication No. 11406/1983 is generated at the output terminal (7) of the image sensor (1). In order to remove this noise component, the output signal of the image sensor (1) is input to the CDS circuit (8) via the output terminal (7) to obtain a video signal with the noise component suppressed.

FIG. 7 is a waveform diagram for explaining this noise suppression principle. After being reset by the horizontal reset pulse (OHR) of the horizontal drive circuit (5), the output signal of the image sensor (1) is read from the falling edge of the horizontal transfer pulse (OH2), as shown in FIG. 7(C). noise component N,
This is a form that includes a signal component S. Note that the subscript numbers for N and S indicate the reading order.

The output signal of this image sensor (1) is transmitted to the CDS circuit (8
) to the signal hole horn terminal (26), and then connect the input terminal (25
), a noise sample hold pulse shown in FIG. 7(J) is manually applied. As a result, the sample hold circuit (2
7), the noise output signal shown in FIG. 7(L) is obtained.

In addition, the signal sample and hold pulse shown in FIG. 7 (K) is input to the input terminal (24), and the sample and hold circuits (28) and (29) which receive this signal sample and hold pulse (K) as input The noise output signal shown in FIG. 7(M) and the noise output signal child signal output signal shown in FIG. 7(N) are obtained.

The signals shown in FIG.
By subtracting by 0), the output signal shown in FIG. 7(P) containing only signal components without noise components can be obtained without the influence of glitches due to the sample-and-hold pulse.

[Problem to be solved by the invention]

Since the conventional solid-state imaging device is configured as described above, the sample and hold pulse of the CDS circuit is output from the timing generator, and if the image sensor output signal phase and the pulse phase do not match, a delay circuit or a delay circuit is installed outside the device. There are problems in that a pulse width control circuit or the like must be provided to match the phase, and it is also necessary to change the delay amount and pulse width using a vertical drive circuit and a horizontal drive circuit.

This invention was made with the aim of solving the above-mentioned problems, and it is possible to easily generate pulses for the CDS circuit with a phase and pulse width suitable for the image sensor output signal, and the delay can be reduced depending on the number of pixels and the drive circuit. The purpose of the present invention is to obtain a solid-state imaging device that can be used for general purposes even if the amount and pulse width change.

[Means to solve the problem]

The solid-state imaging device according to the present invention generates a single pulse by adjusting the phase and shaping the horizontal reset pulse and horizontal transfer pulse, which are the outputs of the horizontal drive circuit, and controlling the width of this pulse by a delay circuit. It is equipped with a pulse generation circuit that generates pulses for the CDS circuit suitable for the output signal of the image sensor.

[Effect]

The pulse generation circuit in this invention generates a single pulse by adjusting the phase and shaping the horizontal reset pulse and horizontal transfer pulse, which are the outputs of the horizontal drive circuit, and controls the pulse width by a delay circuit to generate an image sensor. By generating pulses for the CDS circuit suitable for the output signal,
Application is possible using an image sensor with any number of pixels.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, in which the same parts as those in FIG.
8) This is a pulse generation circuit that generates pulses for

FIG. 2 shows an example of the configuration of the pulse generating circuit (6), and in FIG. 2, (10).

(13) is an input terminal for the horizontal transfer pulse and horizontal reset pulse, which are the output signals of the horizontal drive circuit (5);
), (33) are input terminals (10).

(13) A buffer circuit connected to (11).

(14) is a phase adjustment circuit (34) provided externally.

Input terminals (35), (12) and (15) are input terminals for manually inputting horizontal transfer pulses and horizontal reset pulses whose phases have been adjusted by phase adjustment circuits (34) and (35), (17) and (18) is the input terminal (12),
(15) is a waveform shaping circuit connected to (19) a timing pulse generation circuit that generates a single pulse from the output signals of the waveform shaping circuits (17) and (18);
0) is a delay circuit, (21) is a selection circuit that determines the delay amount of the delay circuit (20), (16) is an inversion circuit, and (22) is a signal generated by the signals of the delay circuit (20) and the inversion circuit (16). A signal sample and hold pulse generation circuit that generates a sample and hold pulse; (23) a noise sample and hold pulse generation circuit that generates a noise sample and hold pulse based on the signals from the delay circuit (20) and the buffer circuit (32); (24); 25) is a CD that manually generates the signal sample hold pulse and noise sample hold pulse.
This is the input terminal of the S circuit (8).

Next, the operation of the above embodiment will be explained with reference to the signal waveform diagram of FIG. FIG. 3(C) shows the output signal of the image sensor (1), and the horizontal reset pulse (
After being reset by OHR), it is read out from the falling edge of the horizontal transfer pulse (0) (2) shown in FIG. 3(B).

Here, the horizontal reset pulse (OHR) is passed through an externally provided phase adjustment circuit (34) to a third pulse having a time constant.
A signal as shown in figure (D) is obtained. This signal is input to the waveform shaping circuit (17), and the noise sampling pulse 2! shown in FIG. 3(E) is generated. Create a standard signal.

Similarly, the horizontal transfer pulse shown in FIG. 3(B) is passed through an external phase adjustment circuit (35) to obtain a signal having a time constant as shown in FIG. 3(F). This signal is input to the waveform shaping circuit (18) to obtain a reference signal for the signal sampling pulse shown in FIG. 3(G).

The timing pulse generating circuit (19) generates the signal shown in FIG. 3(H) from the falling edge of the signal shown in FIG. 3(E) to the falling edge of the signal shown in FIG. 3(G). This third
The period from the rise of the signal shown in Figure 3 (H) until the horizontal transfer pulse shown in Figure 3 (B) becomes L becomes the noise sampling pulse, and from the fall of the signal shown in Figure 3 (H) The period until the horizontal reset pulse shown in FIG. 3A becomes H becomes a signal sampling pulse.

However, here, the signal shown in FIG.
The pulse shown in Fig. 3 (1) is generated through the circuit, the pulse width is determined, and the signal sample and hold pulse generation circuit (22)
, the noise sample and hold pulse generation circuit (23) in FIG. 3 (J).

Obtain the signal sample hold pulse and noise sample hold pulse shown in (IK).

In this example, since the output signal of the actual drive circuit is used, the phase of the output signal of the image sensor (1) shown in FIG. 3(C) and the phase of the output signal of the image sensor (1) shown in FIG.
The phases of the signal sample and hold pulse and the noise sample and hold pulse shown in are suitable for the CDS circuit (8), and the trailing edge of the signal sample and hold pulse (K) does not enter the leakage region of the reset pulse. The trailing edge of the noise sample and hold pulse (J) never enters the signal readout region.

In addition, the phase and amplitude of the pulse are determined by an external phase adjustment circuit (34).
, (35), can be easily determined using the delay circuit (20). Therefore, it can be used regardless of phase changes due to the influence of the drive circuit, frequency changes when the number of pixels changes, etc.

FIG. 4 shows another embodiment of the present invention, in which the output signal of the image sensor (1) is directly transmitted to the CDS.
Although the configuration is such that the circuit (8) is manually inputted, in this example, the output signal of the image sensor (1) is once passed through the amplifier (36) and then manually inputted to the CDS circuit (8). In this case, the horizontal transfer pulse (OH
2) and horizontal reset pulse (OHR) through simple delay circuits (37) and (38), the pulse generation circuit (
6) can be adequately handled by human labor.

〔Effect of the invention〕

As described above, according to the present invention, the CDS circuit pulse is generated by controlling the phase pulse width of the horizontal reset pulse and the horizontal transfer pulse, which are the outputs of the horizontal drive circuit of the image sensor. It is possible to easily optimize the relationship between the output signal of the image sensor and the pulse for the CDS circuit, and there is an effect that it is possible to use an image sensor with any number of pixels.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a block diagram of a pulse generation circuit in the device shown in FIG. 1, FIG. 3 is a signal waveform diagram for explaining the operation, and FIG. FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 5 is a block diagram of a conventional solid-state imaging device, FIG. 6 is a block diagram of a CDS circuit, and FIG. 7 is a signal diagram explaining the operation of the CDS circuit. FIG. In the figure, (1) is an image sensor, (4) is a vertical drive circuit, (5) is a horizontal drive circuit, (6) is a pulse generation circuit, and (8) is a CDS circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A vertical drive circuit that drives a vertical register and a horizontal drive circuit that drives a horizontal register of a solid-state image sensor, and a correlated double sampling circuit that removes noise components from a video signal output from the solid-state image sensor. and adjusting the phase and shaping the waveform of a horizontal reset pulse and a horizontal transfer pulse, which are the outputs of the horizontal drive circuit, to generate a single pulse,
A solid-state imaging device comprising a pulse generation circuit that controls the pulse width of the pulse using a delay circuit to generate a pulse for the correlated double sampling circuit suitable for an output signal of the solid-state imaging device.