JPH04156076A - Video signal processing system - Google Patents

Abstract

PURPOSE:To improve the S/N of a picture from which an FPN is eliminated by setting number of times of addition of the FPN data based on the number of times of addition of a picture data for expanding a dynamic range. CONSTITUTION:An FPN data stored in a fixed pattern noise(FPN) memory 4 is read out of an FPN memory 4 in a timing in matching with a required picture data, and since the read addition FPN data differs from the added picture data in terms of a data level, the level is divided by 1/8 at a divider 8 to match the data level and the result is inputted to a subtractor 6. In this case, a minimum value of number of times (x) of addition of the FPN data is set so that the relation of x=n is satisfied with respect to the number of times (n) of addition of a signal data by an n-time adder circuit. Thus, an error in the case of FPN elimination processing is reduced and the S/N of the picture with the FPN eliminated therefrom is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal processing method in a video camera system using an amplified solid-state image sensor, and particularly to fixed pattern noise (hereinafter referred to as FPN) of an amplified solid-state image sensor. (abbreviated)).

[Conventional technology] Conventionally, static! Induction transistor (Stati)
c Induction Transistor:
(abbreviated as SIT) and charge modulation element (Cha
rge ModulationDevice: CM
In devices that reproduce images using amplified solid-state image sensors that use internally amplified photoelectric conversion elements (abbreviated as D) as unit pixels, the element-specific FPN has become a problem. In order to cancel, a storage means such as a frame memory is provided, the FPN is stored for each pixel in the storage means, and the FPN corresponding to that pixel is subtracted from the image information obtained from each pixel of the solid-state image sensor. Therefore, an FPN suppressing means is required to obtain an image signal.

FIG. 10 is a block diagram of a conventional FPN suppressing means used in an image reproducing apparatus using such an internally amplified solid-state image sensor. In FIG. 10, 101 is an amplified solid-state image sensor, 102 is an A/D converter, and 103
is a frame memory, and 104 is a subtracter. In the FPN suppressing means configured in this way, first, in order to obtain FPN data, incident light to the solid-state image sensor 101 is blocked, and the dark level data output at that time is written into the memory 103 as FPN data. After writing the FPN data, the solid-state image sensor 101 is in the normal imaging state.
Obtain image data from. The image data is then repeatedly subtracted from the FPN data stored in the frame memory 103 by a subtracter 104, and is output as image data with FPN canceled.

On the other hand, in the data processing method of the solid-state image sensor output, as shown in FIG.
By adding the current frame data from the solid-state image sensor and the previous frame data delayed by one frame stored in the frame memory 111, the dynamic range is wider than that of the solid-state image sensor. A widely known method is to obtain gain by reducing random noise while obtaining dynamic range characteristics.

This circuit system converts the input and output levels of a solid-state image sensor that has a saturation level as shown in Figure 12 (C
), and by adding the current frame input shown in Fig. 12 (■) and the previous frame input shown in Fig. 12 (C), the saturation level shown in Fig. 12 is exceeded. The input/output characteristics shown in Figure 12) are obtained.

The circuit system shown in FIG. 11 is for one-time addition of video signals, but by increasing the number of frame memories and adders, n-time addition is possible and the dynamic range can be further expanded. For example, if n=2, the first
Two frame memories 111 and 113 as shown in Figure 3
and two adders 112 and 114.

[The invention tries to solve f! Title]

However, when FPN is removed using the conventional FPN suppression means, FPN data changes depending on the timing of capture due to the influence of random noise components, so there is a problem that FPN cannot be completely removed from image data. there were.

On the other hand, when using a conventional circuit method as a means of expanding the dynamic range of the output of a solid-state image sensor, there is a time difference of 1730 seconds between the current frame and the previous frame, so the two signal data to be added are not necessarily the same. Not only that, but the addition may cause image blurring, resulting in an unsightly screen. Furthermore, if the circuit is configured to perform n additions, n memories and n adders are required, resulting in a problem that the circuit scale becomes large.

The present invention has been made in order to solve the above-mentioned problems in conventional video signal processing methods, and it is possible to obtain a screen with less blur from a solid-state image sensor and to perform more accurate FPN removal from a video signal. The purpose is to provide a processing method.

[Means and effects for solving the problems] In order to solve the above problems, the present invention provides an amplification type solid-state image pickup device that can read data m times in one field period and has an FPN specific to the device. , a delay means for delaying signal data of the two-time solid-state image sensor, an adder for adding signal data of the solid-state image sensor and delay data of the delay means, and controlling addition of delay data from the delay means. a cyclic n-time addition circuit consisting of a control circuit that performs
A memory that stores data and an F output from the memory.
In a video signal processing method in a video camera system that includes a subtracter that subtracts PN data from the addition data of the n-time addition circuit, the FPN data stored in the FPN storage memory is FPN data that has been added X times. and the minimum value of the number of additions X of the FPN data is the n
The value of the number of times n of signal data addition by the times adding circuit is set so as to satisfy the relationship x=n.

In this way, by reading m times from the solid-state image sensor in one field period, adding them using a cyclic n-times adding circuit, and outputting them, it is possible to reduce the time difference during addition without increasing the circuit scale. The dynamic range can be expanded without causing image blur. Furthermore, by setting the minimum value of the number of additions X of the FPN data to satisfy the relationship x-n with respect to the number of additions n of signal data by the n-time addition circuit, the error during FPN removal processing can be reduced. It is possible to improve the S/N of an image with FPN removed.

〔Example〕

Next, an example will be described. FIG. 1 is a block configuration diagram of a video signal processing circuit for explaining an embodiment of the video signal processing method according to the present invention, and FIG. 2 is a diagram showing the timing of data readout of the solid-state image sensor. It is. In FIG. 1, 1 is an amplified solid-state image sensor using a CMD or the like as a unit pixel, 2 is an A/D converter, and 3 is a 1/2
2 field delay device, 4 memory for storing FPN, 5
6 is an adder, 6 is a subtracter, 7 is a cyclic addition control circuit, 8 is a divider, 9 is a control signal generation circuit for sending control signals to each section, and 10 is a time axis conversion memory. In Figure 2,
VD is a pulse signal with a period of one field in the NTSC system, and VD4 is a pulse signal with a period of 1/4 of the pulse signal VD. The read data is read out in synchronization with the rising edge of the pulse signal VD4.

Next, the configuration and readout method of the amplified solid-state image sensor 1 used in this embodiment will be explained. The solid-state image sensor used in this embodiment is used for special purposes such as endoscopes, and has a square screen size as shown in FIG. 3, so it does not require full screen information. Therefore, by using a square size so that the information on one screen is 1/4 of the information on one field screen, it becomes possible to read data four times in one field without performing high-speed operation.

If the exposure time in one frame is set to 1/4 field, that is, 1/240 seconds or more, four consecutive pieces of data in one field are read out in the order of A field and B field, as shown in Figure 2. . For a full screen of one field, reading is performed as shown in FIG. 4, and the horizontal period is 1/2 period.

Also, if the exposure time is longer than 17,240 seconds, it is impossible to read out four times as described above, so if the exposure time is set to 17,120 seconds, the L field will be read twice,
At 1/60 seconds, data is read once per 1 field. The readout timing when the exposure time is 1760 seconds is read out in synchronization with the pulse signal VD, as shown in FIG.

In this example, when expanding the dynamic range,
The purpose is to obtain images with less blur. Therefore, if exposure is performed for 1/60 second, it will have the same drawbacks as the conventional example, so addition will not be performed, but in case the exposure time is given priority over the dynamic range,
It is configured to have this data output mode.

Next, the operation of the video signal processing circuit shown in FIG. 1 will be explained. Adder 5. The delay device 3 and the cyclic addition control circuit 7 constitute a cyclic addition circuit.

Now, in the cyclic adder circuit, the cyclic adder control circuit 7
is through, the read data of delay device 3 is A
1 If it is field data, solid-state image sensor 1
Since the read data ① is data after 1/2 field, it becomes A2 field data, and the field data A1 and A2 are added by the adder 5. Since the delay unit 3 always provides a delay of 1/2 field, the A field data is added to the A field data, and the B field data is added to the B field data.

On the other hand, when the cyclic addition control circuit 7 controls the cyclic addition stop, when the "L" level control signal is applied from the control signal generation circuit 9, the cyclic addition control circuit 7 sends the feedback data ■ to the adder 5. Since all data are output as ``0°'', no addition is performed in the adder 5, and the output data of the solid-state image sensor 1 is passed through as is, so that the cyclic adder circuit can be initialized.

In this example, the exposure time is 1/240 second and 1/60 second.
In the 17240 second exposure mode, data is read four times in one field, so addition is performed three times to facilitate processing in frame units. As shown in FIG. 6, by using the cyclic control signal ■ which is repeated every frame in synchronization with the rising edge of the pulse signal VD when adding data, the data added three times becomes "L" of the cyclic control signal ■. Obtained in a period of . Since addition is not performed in the 1/60 second exposure mode, the cyclic control signal ■ is set to “L”.
’.

On the other hand, the acquisition of dark FPN data is also performed using a cyclic adder circuit. Note that FPN data is imported each time depending on the exposure time. Here, it is necessary to set the number of additions of FPN data, but in the 17240 second exposure mode, the image data is added three times and noise is integrated, so the FPN to be subtracted from the added image data. If the data is not added at least three times, it will not be possible to obtain the same noise integration effect as the added image data.
This causes an error during FPN subtraction and removal.

For example, if you subtract FPNY-Yu without adding it, then F
Since the data level of the PN data is I/4, it is necessary to provide a gain of 4 times, so if 0'' is added to the lower 2 pinpoints and subtraction is performed, the lower 2 bit data after the FPN subtraction is removed will be treated as an error. Therefore,
In this case, the number of additions X of the FPN data is determined by the value of α in the following formula %, with three times as the minimum unit, and further reduction is applied to the data that has obtained the same integral effect as the added image data. I can do it.

In this embodiment, the number of additions x=31, FPN
Addition of data is performed, and since the value of α is 8, division can be performed only by bit adjustment.

As shown in FIG. 7, the FPN data is stored in the FPN memory 4 by applying a control signal ■ synchronized with the rising edge of the pulse signal VD, which is “L”° for a 1/2 field period, and adding it 31 times. At the timing when the data is output from the delay device 3, the write enable signal of the FPN memory 4 is set to "°L°" for 1/2 field period to perform writing.

On the other hand, in the 1/60 second exposure mode, since image data is not added, the minimum value of the number of additions X of FPN data may be O. However, in this embodiment, since it is necessary to integrate the FPN data, the number of additions X is set to seven. As shown in FIG. 8, the storage in the FPN memory 4 is 1.
It is "L" during the frame period, and a control signal (2) synchronized with the pulse signal VD is given at the time of capture. Since the data added seven times is output separately for the A field and the B field over one frame, the write enable signal of the FPN memory 4 is set to "L" twice for a 1/4 field period. Write to.

The FPN data accumulated in the FPN memory 4 as described above is transferred to the FPN at a timing that matches the required image data.
It is read from the PN memory 4.

Since the read addition FPN data has a data level different from that of the addition image data, the data level is matched by dividing it by 1/8 in the divider 8, and the data level is inputted to the subtracter 6.

The image data from which the dark FPN data has been removed by the subtracter 6 is written into the time axis conversion memory 10 and read out at the timing shown in FIG. 9 to obtain an image as shown in FIG. 3. .

As described above, in this embodiment, addition of image data for expanding the dynamic range and addition for integrating FPN data are performed in the same adding circuit, and since a cyclic circuit is used, the circuit It is possible to significantly reduce the scale. In addition, since the number of additions of FPN data is set based on the number of additions of image data to expand the dynamic range, the S
/N improvement can be measured.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, it is possible to reduce the time difference during addition while reducing the circuit scale and expand the dynamic range without causing image blur.

Furthermore, it is possible to reduce errors during FPN removal processing, and it is possible to improve the S/N of an image from which FPN has been removed.

In addition, the number of additions n of image data is determined according to the number of times m of reading one field of the solid-state image sensor, and the minimum value of the number of additions X of FPN data is set to x=n-(m-1). Since processing can be performed in units, the circuit scale can be reduced.

Furthermore, the circuit scale can be further reduced by using the same cyclic n-time addition circuit to perform the addition of the image data of the solid-state image sensor and the addition of the FPN data.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a video signal processing circuit for explaining an embodiment of the video signal processing method according to the present invention, FIG. 2 is a data read timing diagram of the solid-state image sensor, and FIG. , A diagram showing the screen size of the solid-state image sensor used in the embodiment shown in FIG. 1, FIG. A data read timing diagram of the solid-state image sensor in the second exposure mode. FIG. 6 is a diagram showing the relationship between the cyclic control signal and the delay device output to explain the image data processing mode. FIG. 7 is a 17240 second exposure FIG. 8 is a diagram showing the relationship between the signals of each part and the output of the delay device to explain the processing aspect of dark FPN data in the mode.
9 is a diagram showing the relationship between the signals of each part and the output of the delay device to explain the processing mode of dark FPN data in the 1/60 second exposure mode; FIG. 9 is a diagram showing the output data of the time axis conversion memory; FIG. 10 is a block configuration diagram of a conventional FPN suppressing means, FIG. 11 is a block configuration diagram showing an example of the configuration of a conventional video signal processing circuit, and FIG. 12 ~■) is for explaining its operation. Figure 13 shows the input/output characteristics of
FIG. 2 is a block configuration diagram showing another configuration example of a conventional video signal processing circuit. In the figure, 1,101 is an amplified solid-state image sensor, 2.1
02 is an A/D converter, 3 is a delay device, 4 is an FPN storage memory, 5, 112, 114 is an adder, 6, 104 is a subtracter, 7 is a cyclic addition control circuit, 8 is a static eliminator, 9 is a control Signal generation circuit, 10 is time axis conversion memory, 103, 111.1
13 indicates a frame memory. Patent applicant Kenji Mogami, Patent attorney representing Olympus Optical Industry Co., Ltd., 77. π71.5 ho・-1
7 tj -, ;, V Figure 3 Figure 4 Figure 5 ± 2 countries Country Figure 10 Figure 12 Figure 13

Claims (1)

[Scope of Claims] 1. An amplified solid-state imaging device capable of reading data m times in one field period and having a fixed pattern noise unique to the device, and a delay means for delaying signal data of the solid-state imaging device; a cyclic n-time addition circuit comprising an adder for adding signal data of the solid-state image sensor and delay data of the delay means; and a control circuit for controlling addition of the delay data from the delay means; In a video signal processing method in a video camera system comprising a memory that stores fixed pattern noise data of an image sensor, and a subtracter that subtracts the fixed pattern noise data output from the memory from the addition data of the n-time addition circuit. , the fixed pattern noise data stored in the fixed pattern noise storage memory is fixed pattern noise data that has been added x times, and the minimum value of the number of additions x of the fixed pattern noise data is determined by the signal generated by the n-time addition circuit. A video signal processing method characterized in that the value of the number of additions n of data is set so as to satisfy the relationship x=n. 2. Number of times m of reading one field of the solid-state image sensor
is changed according to the exposure time, the number of additions n is changed according to the number of readouts m, and the minimum value of the number of additions x of the fixed pattern noise data is set to x=n=(m-1). The video signal processing system according to claim 1, characterized in that: 3. The video signal processing system according to claim 1 or 2, wherein the x additions of the fixed pattern noise data are performed using the cyclic n-time addition circuit.