JP5215695B2 - Imaging device - Google Patents

Description

  The present invention relates to an image capturing apparatus that acquires image information.

  As a circuit configuration around the image sensor mounted on the image capturing apparatus, a configuration in which a drive signal is supplied to the image sensor and the A / D converter by a timing generator is known. According to Japanese Patent Laid-Open No. 2004-228561, a configuration is shown in which a drive signal is supplied from a control / drive clock generator to a CCD line sensor and an A / D converter.

  FIG. 4 is a diagram illustrating a circuit configuration around the image sensor of the image capturing apparatus according to the related art. The CPU 101 controls the timing generator 102, the CMOS sensor 103, and the A / D converter 104. The timing generator 102 generates and outputs an image sensor reference signal for driving the CMOS sensor 103 and an A / D converter drive signal for driving the A / D converter 104. The CMOS sensor 103 includes a photoelectric conversion unit 105, a drive signal generation unit 106, and a serial interface 107. The photoelectric conversion unit 105 photoelectrically converts light corresponding to the document image into an analog image signal. The drive signal generation unit 106 generates an image sensor drive signal necessary for photoelectric conversion. The serial interface 107 transmits and receives control signals to the CPU 101. The A / D converter 104 converts the analog image signal into a digital image signal according to the A / D converter drive signal received from the timing generator 102, and outputs the digital image signal.

  The drive signal generation unit 106 of the CMOS sensor 103 receives the image sensor reference signal output from the timing generator 102. The drive signal generation unit 106 generates an image sensor drive signal necessary for photoelectric conversion based on the synchronization signal and the reference clock included in the image sensor reference signal. The photoelectric conversion unit 105 outputs an analog image signal in accordance with the image sensor driving signal.

  FIG. 5 is a diagram for explaining the drive signal generation unit 106. The register 502 holds a setting value included in a control signal received from the CPU 101 via the serial interface 107 (FIG. 4). The counter 503 performs counting in synchronization with a reference clock included in the image sensor reference signal. The comparator 504 compares the set value held in the register 502 with the counter value of the counter 503 to generate an image sensor driving signal and a mask signal. The mask unit 505 masks a part of the image sensor reference signal according to the mask signal from the comparator 504.

  Incidentally, the analog image signal output from the CMOS sensor 103 is output with a delay with respect to the image sensor reference signal. This is because signal delay occurs inside the photoelectric conversion unit 105 and the drive signal generation unit 106.

  On the other hand, the A / D converter 104 converts the analog image signal output from the CMOS sensor 103 into a digital image signal based on the A / D converter drive signal output from the timing generator 102, and converts the analog image signal to the subsequent circuit ( Output to a shading circuit).

  In order to transfer and process an image correctly in such a system for transferring an image signal, it is necessary to always maintain a synchronization relationship and a phase relationship between the image signal and the drive signal of each element. If the synchronization relationship and the phase relationship are lost, the main scanning position may be shifted, or the A / D converter cannot correctly perform A / D conversion.

  The delay amount of the analog image signal described above depends on changes in environmental conditions such as the ambient temperature of the image sensor, the operating state, and the power supply voltage, and thus is not always constant. Therefore, the higher the drive frequency of the image sensor in the image capturing apparatus having the above-described configuration, the more analog image signal output from the image sensor for one pixel period of the digital image signal output from the A / D converter. The variation in the delay amount increases. As a result, in a subsequent element (for example, an A / D converter), the synchronization relationship or the phase relationship is lost between the analog image signal and the drive signal of the element, and correct image processing cannot be performed.

  FIG. 6 is a diagram illustrating an example of input / output signals in the image sensor. The CLK_IN signal and the SYNC_IN signal are signals included in the image sensor reference signal and are input to the CMOS sensor 103. The CLK_IN signal is a reference clock for image transfer. The SYNC_IN signal is an image synchronization signal synchronized with the reference clock, and is a signal indicating the main scanning imaging start position of the image, for example. With these signals, each element synchronizes the image. The CLK_IN signal and the SYNC_IN signal are also included in the image sensor driving signal and the A / D converter driving signal, and are input to the CMOS sensor 103 and the A / D converter 104. The CMOS sensor 103 outputs an analog image signal based on the CLK_IN signal and the SYNC_IN signal.

  At that time, the timing at which the analog image signal is output from the image sensor is delayed with respect to the timing at which the reference clock is input to the image sensor. This delay varies according to environmental conditions as described above. That is, the output timing of the analog image signal (DATA) varies between when the signal delay is minimum (DATA_minDELAY) and when the signal delay is maximum (DATA_maxDELAY).

  If this variation is greater than one period of the reference clock, the synchronization relationship between the SYNC_IN signal and the analog image signal is lost, and the image signal cannot be transferred correctly. In particular, as the frequency of the reference clock increases, variation in signal delay cannot be ignored.

  Even if the variation is one cycle or less of the reference clock, the phase relationship between the analog image signal and the A / D converter drive signal changes in the A / D converter at the subsequent stage if the variation ratio with respect to the reference clock increases. End up. This makes it impossible to uniquely determine the sample timing of the analog image signal, so that the analog image signal cannot be correctly converted into a digital image signal.

In relation to this, Patent Document 2 discloses that the phase of the clock supplied to the A / D conversion circuit is shifted from the phase of the clock supplied to the CCD. Patent Document 3 discloses that a delay element is provided in a pixel clock transmission path from a CCD camera to an A / D converter.
JP 2003-319133 A JP-A-7-288660 JP 2000-236487 A

  However, the conventional technology cannot dynamically cope with the variation in the delay amount of the analog image signal depending on the environmental conditions such as the ambient temperature, the operating state, and the power supply voltage of the image sensor described above.

SUMMARY OF THE INVENTION An object of the present invention is to prevent synchronization between an imaging unit and a conversion unit that converts an analog image signal into a digital image signal due to self-heating of the imaging unit.

The present invention includes an imaging unit that captures an image and outputs an analog image signal;
Conversion means for converting the analog image signal into a digital image signal;
Generating a synchronization signal to be supplied to the imaging unit and the conversion unit, and supplying a synchronization signal to the imaging unit;
A correction unit that corrects the timing of supplying the synchronization signal generated by the synchronization signal generation unit to the conversion unit and supplies the synchronization signal to the conversion unit;
The correction unit is provided on a member that prevents positional distortion of the imaging unit and is affected by the self-heating of the imaging unit. The generated synchronization signal is delayed.

The present invention can prevent the synchronization of the imaging means and the conversion means for converting the analog image signal into the digital image signal due to self-heating of the imaging means.

  An embodiment of the present invention is shown below. Of course, the individual embodiments described below will be helpful in understanding various concepts such as the superordinate concept, intermediate concept and subordinate concept of the present invention. Further, the technical scope of the present invention is determined by the scope of the claims, and is not limited by the following individual embodiments.

  FIG. 1 is a block diagram illustrating an example of an image capturing apparatus according to the embodiment. The CPU 101 controls the timing generator 102, the CMOS sensor 103, and the A / D converter 104. The timing generator 102 generates and outputs an image sensor reference signal for driving the CMOS sensor 103 and an A / D converter drive signal for driving the A / D converter 104, respectively. In this manner, the timing generator 102 is an example of a synchronization signal generating unit that generates and supplies the first drive signal and the second drive signal corresponding to the synchronized image sensor reference signal and the A / D converter drive signal, respectively. is there.

  The CMOS sensor 103 includes a photoelectric conversion unit 105, a drive signal generation unit 106, and a serial interface 107. The photoelectric conversion unit 105 photoelectrically converts light corresponding to the document image into an analog image signal. That is, the photoelectric conversion unit 105 is an example of an imaging unit that captures an image according to the first drive signal and outputs an analog image signal.

  The drive signal generation unit 106 generates an image sensor drive signal necessary for photoelectric conversion. More specifically, the drive signal generation unit 106 first receives the image sensor reference signal output from the timing generator 102. The drive signal generation unit 106 generates an image sensor drive signal necessary for driving the photoelectric conversion unit based on the synchronization signal SYNC_IN and the reference clock CLK_IN included in the image sensor reference signal. In accordance with the image sensor driving signal, the photoelectric conversion unit 105 outputs an analog image signal. Note that the drive signal generation unit 106 employs the configuration described above, for example.

  The serial interface 107 transmits and receives control signals to the CPU 101. The A / D converter 104 converts the analog image signal into a digital image signal according to the A / D converter drive signal generated by the timing generator 102 and arrived via the signal delay circuit 108, and outputs the digital image signal.

  The signal delay circuit 108 is an example of a correction unit that corrects a deviation between the arrival timing of the analog image signal to the A / D converter 104 and the arrival timing of the second drive signal to the A / D converter 104. The signal delay circuit 108 is formed on the same semiconductor chip of the CMOS sensor 103 as will be described later. This is because the configuration is such that the environmental fluctuations (ambient temperature and power supply voltage fluctuations) experienced by the photoelectric conversion unit 105 and the signal delay circuit 108 are substantially the same. That is, the signal delay circuit 108 is provided at a position where the influence of environmental fluctuations received by the photoelectric conversion unit 105 and the signal delay circuit 108 can be substantially identical, or in such a configuration. The variation in the ambient temperature includes not only the variation in the temperature in the image capturing apparatus but also the variation in the temperature of the photoelectric conversion unit 105 due to self-heating of the photoelectric conversion unit 105. In other words, the signal delay circuit 108 is provided at a position that is substantially affected by the self-heating of the photoelectric conversion unit 105 or in such a configuration. Further, the signal delay circuit 108 delays the second drive signal, and determines the arrival timing of the analog image signal to the A / D converter 104 and the arrival timing of the second drive signal to the A / D converter 104. It is also an example of signal delay means for reducing the deviation. The A / D converter 104 is an example of a conversion unit that converts an analog image signal into a digital image signal according to a second drive signal whose arrival timing at the A / D converter 104 is corrected, and outputs the digital image signal.

  More specifically, the signal delay circuit 108 receives an A / D converter drive signal from the timing generator 102, delays the received A / D converter drive signal by a predetermined delay amount, and outputs the delayed signal. Circuit. The signal delay circuit 108 can be composed of, for example, a flip-flop and a delay buffer. That is, the signal delay circuit 108 is a circuit that adjusts the output timing of the flip-flop in the final stage so that the delay amount of the analog image signal and the signal delay amount of the A / D converter driving signal are equal. is there. Here, the delay amount of the analog image signal is a signal delay amount of the analog image signal output from the CMOS sensor 103 with respect to the image sensor reference signal input to the CMOS sensor 103. The signal delay amount of the A / D converter drive signal is the signal delay amount of the A / D converter drive signal output from the CMOS sensor 103 with respect to the A / D converter drive signal input to the CMOS sensor 103. . A specific example of the signal delay circuit 108 will be described later.

  The CMOS sensor 103 receives an A / D converter drive signal and an image sensor reference signal from the timing generator 102, and outputs an analog image signal and an A / D converter drive signal. In the related art shown in FIG. 4, the A / D converter drive signal output from the timing generator 102 is directly input to the A / D converter. However, in this embodiment, the A / D converter drive signal is input to the A / D converter 104 via the signal delay circuit 108 provided in the CMOS sensor 103.

  It is ideal if an analog image signal is output from the CMOS sensor 103 almost simultaneously with the image sensor drive signal being input to the CMOS sensor 103. However, in reality, in addition to the propagation delay that occurs in the transmission path, internal signal delay of the photoelectric conversion unit 105 and the drive signal generation unit 106 occurs. Therefore, in the related art, even when the synchronization and phase relationship between the image element reference signal and the A / D converter drive signal is maintained at the time of output from the timing generator, the A / D to the A / D converter 104 is maintained. The arrival timing of the converter drive signal and the analog image signal is shifted. That is, the synchronization relationship and phase relationship between the A / D converter drive signal and the analog image signal are broken.

  On the other hand, in this embodiment, the A / D converter drive signal is passed through the signal delay circuit 108 provided in the CMOS sensor 103, so that the arrival timing of the analog image signal and the A / D converter drive signal Deviation from arrival timing is reduced. That is, it is possible to maintain the synchronization relationship and phase relationship between the A / D converter drive signal and the analog image signal.

  FIG. 2 is a diagram illustrating an example of a relationship between an input signal and an output signal for the image sensor according to the embodiment. In FIG. 2, the CLK_IN signal and the SYNC_IN signal are as described above. The CMOS sensor 103 outputs an analog image signal based on the CLK_IN signal or the SYNC_IN signal.

  The CLK_OUT signal and the SYNC_OUT signal are image synchronization signals included in the A / D converter drive signal output from the signal delay circuit 108. As described above, the signal delay varies depending on the environmental conditions. That is, the amount of delay varies depending on the environmental conditions. This means that the delay amount has a minimum value and a maximum value, and the delay amount takes any value between them. Here, the analog image signal when the delay amount is minimum is DATA_minDELAY, and the analog image signal when the delay amount is maximum is DATA_maxDELAY. As shown in FIG. 2, when the signal delay variation, which is the difference between the minimum value and the maximum value of the delay amount, exceeds one pixel period, the subsequent circuit cannot correctly execute the process.

  In the present embodiment, the signal delay circuit 108 outputs a CLK_OUT signal and a SYNC_OUT signal to which a delay amount equivalent to the delay amount of the analog image signal output from the photoelectric conversion unit 105 is added. Therefore, it is possible to maintain the synchronization relationship and phase relationship between the A / D converter drive signal and the analog image signal. That is, taking the SYNC_OUT signal as an example, as shown in FIG. 2, SYNC_OUT_min is output when the delay amount of the analog image signal is minimum, and SYNC_OUT_max is output when it is maximum. Thereby, the A / D converter 104 can uniquely determine the sample timing of the analog image signal.

  FIG. 3 is a block diagram illustrating an example of the CMOS sensor 103 and the signal delay circuit 108 according to the embodiment. The selector 301 is a selector or a gate circuit arranged at the final stage of the image signal. The image signal is controlled by the changing point of the switching signal (CLK1) input to the selector 301. That is, the read image signal is switched by the switching signal (CLK1). Note that the image signal 1 and the image signal 2 are image signals output from the odd-numbered pixels and the even-numbered pixels of the photoelectric conversion unit 105, respectively. The output amplifier 302 amplifies the image signal selected by the selector 301 and outputs it from the image signal output terminal 303. Therefore, the delay of the image signal is caused by a delay due to the wiring from the selector 301 to the image signal output terminal 303, the delay of the output amplifier 302, or the like.

  In order to delay the A / D converter drive signal by the same amount as the delay amount of the image signal, the flip-flop 304 delays the A / D converter drive signal and the switching signal of the selector 301 (CLK2). Are entered. The number of stages and the wiring length of the delay buffer 305 are adjusted so that the delay amount from the flip-flop 304 to the drive signal output terminal 306 is the same as the delay amount of the image signal. The number of stages and the wiring length are determined by performing an actual delay simulation at the time of wiring in the logic circuit design of the CMOS sensor 103. At this time, it is desirable to consider variations in ambient temperature and power supply voltage.

  Since the selector 301, the output amplifier 302, and the delay buffer 305 are manufactured by the same semiconductor process, the variation tendency of the delay amount with respect to variations in the ambient temperature and the power supply voltage is very similar. Therefore, even when the ambient temperature, power supply voltage, etc. fluctuate when using the CMOS sensor 103, the delay amount of each element fluctuates in conjunction with each other. The amount of delay can be made equal.

  According to the present invention, even if the drive frequency of the image sensor increases, the correction means for correcting the difference between the arrival timing of the analog image signal and the arrival timing of the A / D converter drive signal is provided. It becomes easy to maintain the synchronous relationship and phase relationship between the signal and the drive signal. Of course, this makes it possible to correctly process the image signal by the conversion means and further downstream circuits.

  For example, by providing the signal delay circuit 108 that delays the A / D converter drive signal, the difference between the arrival timing of the analog image signal to the A / D converter 104 and the arrival timing of the A / D converter drive signal. Is reduced.

  As described above, the delay amount depends on changes in environmental conditions such as the ambient temperature of the image sensor, the operating state, and the power supply voltage. Therefore, it is desirable that the transmission path of the A / D converter drive signal and the transmission path of the analog image signal are placed under substantially the same environmental conditions. This is because the delay amount of the A / D converter drive signal and the delay amount of the analog image signal are substantially the same if the environmental conditions are substantially the same.

  For this purpose, it is desirable to form the photoelectric conversion unit 105 and the signal delay circuit 108 on the same semiconductor chip. That is, if a signal delay circuit is also mounted on the CMOS sensor 103, both circuits can be manufactured by the same semiconductor process, and therefore the fluctuation tendency with respect to variations in ambient temperature and power supply voltage will be the same.

  Of course, it is not essential that the signal delay circuit 108 is mounted in the CMOS sensor 103. The present invention can also be applied to other configurations in which the influences of environmental fluctuations (ambient temperature and power supply voltage fluctuations) on the photoelectric conversion unit 105 and the signal delay circuit 108 are substantially the same. For example, the signal delay circuit 108 may be attached to a ceramic plate (a member for preventing positional distortion) attached to the photoelectric conversion unit 105 in order to prevent positional distortion of the photoelectric conversion unit 105. . That is, the signal delay circuit 108 is provided at a position where the photoelectric conversion unit 105 is substantially affected by the self-heating of the photoelectric conversion unit 105 or in such a configuration. If the delay amount of the A / D converter drive signal and the delay amount of the analog image signal are substantially the same even if the environmental conditions change, the signal delay circuit 108 is disposed outside the CMOS sensor 103. Also good.

  The signal delay amount also depends on the length of the transmission path. Therefore, the length of the transmission path of the image sensor reference signal and the length of the transmission path of the A / D converter drive signal from the timing generator 102 to the CMOS sensor 103 (photoelectric conversion unit 105) are the same length (equal length wiring). Would be desirable. Similarly, the length of the transmission path of the image sensor reference signal and the length of the transmission path of the A / D converter drive signal from the CMOS sensor 103 (photoelectric conversion unit 105) to the A / D converter 104 are the same length ( It would be desirable to have equal length wiring). As a result, the phase shift between the analog image signal and the A / D converter drive signal can be further reduced.

  The delay amount given to the A / D converter drive signal by the signal delay circuit 108 may be a value determined in advance by an actual delay simulation executed at the time of designing the semiconductor chip. The CMOS sensor is only an example of an image sensor, and may be an image sensor having another configuration such as a CCD sensor.

1 is a block diagram illustrating an example of an image reading apparatus according to an embodiment. It is a figure which shows an example of the relationship between the input signal with respect to the image sensor which concerns on embodiment, and an output signal. It is a block diagram which shows an example of the CMOS sensor which concerns on embodiment, and its signal delay circuit. It is a figure which shows the circuit structure around the image pick-up element of the image reading apparatus in related technology. It is a figure for demonstrating a drive signal production | generation part. It is a figure which shows an example of the input-output signal in an image sensor.

Explanation of symbols

101 ... CPU
102 ... Timing generator 103 ... CMOS sensor 104 ... A / D converter 105 ... Photoelectric converter 106 ... Drive signal generator 107 ... Serial interface 108 ... Signal delay circuit

Claims (5)

Imaging means for capturing an image and outputting an analog image signal;
Conversion means for converting the analog image signal into a digital image signal;
Generating a synchronization signal to be supplied to the imaging unit and the conversion unit, and supplying a synchronization signal to the imaging unit;
A correction unit that corrects the timing of supplying the synchronization signal generated by the synchronization signal generation unit to the conversion unit and supplies the synchronization signal to the conversion unit;
The correction unit is provided on a member that prevents positional distortion of the imaging unit and is affected by the self-heating of the imaging unit. An image pickup apparatus characterized by delaying a generated synchronization signal.   2. The image pickup apparatus according to claim 1, wherein the image pickup unit and the correction unit are formed on the same semiconductor chip.   The length of the transmission path for supplying the synchronization signal from the synchronization signal generation means to the imaging means is the same as the length of the transmission path for supplying the synchronization signal from the synchronization signal generation means to the correction means. The image capturing apparatus according to claim 2, wherein   The length of the transmission path for supplying the analog image signal from the imaging means to the conversion means is the same as the length of the transmission path for supplying the synchronization signal from the correction means to the conversion means. The image capturing apparatus according to claim 2, wherein the image capturing apparatus is an image capturing apparatus. The member imaging apparatus according to any one of claims 1 to 4, characterized in that a ceramic plate.

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