WO2010079749A1

WO2010079749A1 - Data transfer device and camera

Info

Publication number: WO2010079749A1
Application number: PCT/JP2010/000051
Authority: WO
Inventors: 小山勝; 田村勉; 向山日出海
Original assignee: 株式会社ニコンシステム
Priority date: 2009-01-09
Filing date: 2010-01-06
Publication date: 2010-07-15
Also published as: JP2010161692A

Abstract

A data transfer device (data transfer unit (4)) arranged in a digital camera (1) includes: a delay process unit (7) which outputs a data signal as reference delay data signal N0 delayed by a predetermined delay amount, a small-delay data signal N- delayed by the predetermined delay amount subtracted by a delay compensation amount, and a large-delay data signal N+ delayed by an amount greater than the predetermined delay compensation amount; an acquisition unit (8) which acquires data from the reference delay data signal N0 according to a clock signal and outputs it; and a delay control unit (9) which controls the predetermined reference delay amount in the delay process unit (7) according to at least one of the matching between the reference data signal N0 and the small-delay data signal N- and the matching between the reference data signal N0 and the large-delay data signal N+.

Description

Data transfer device and camera

The present invention relates to a data transfer device and a camera having the data transfer device.

Conventionally, when designing electronic equipment for the purpose of high-speed transfer of digital data, transmission path impedance control, equal-length wiring, selection of materials such as printed circuit boards, etc. are performed, and then signal waveforms are simulated to validate the data. Period (eye pattern) is secured. In particular, in the case of a parallel method in which data transfer is performed using a plurality of signal lines, there is a limit to measures such as isometric wiring if the transfer speed is in the order of gigahertz, and jitter (fluctuation in the delay time of the data signal) is limited. It is also known that stable high-speed transmission becomes difficult due to the influence. Patent Document 1 discloses a data transfer apparatus that corrects delay variation between signals in parallel data transfer.

JP 2004-171254 A

However, even if the delay variation between signals is corrected, the data delay changes every moment due to temperature change and voltage change. If the amount of delay of the transferred data greatly changes with respect to the data fetch timing, there is a problem that erroneous data reading is likely to occur and the accuracy of data transfer is lost.

The present invention has been made in view of the above problems, and a data transfer apparatus that enables stable data transfer by correcting a delay in data transfer that changes from time to time due to temperature change or voltage change, and the data transfer apparatus. It aims at providing the camera which has this.

In order to solve the above problems, a data transfer device according to the present invention is a data transfer device that transfers a data signal in synchronization with a clock signal, and is a reference delayed data signal obtained by delaying the data signal by a reference delay amount. A delay processing unit that outputs a small delay data signal delayed by a first delay compensation amount smaller than a reference delay amount, and a large delay data signal delayed by a second delay compensation amount larger than a reference delay amount And a capture unit that captures and outputs data from the reference delay data signal based on the clock signal, matching between the reference delay data signal and the small delay data signal, and the reference delay data signal and the large delay data signal A delay control unit that controls a reference delay amount in the delay processing unit based on at least one of the matching.

In such a data transfer device, the delay control unit increases the reference delay amount of the delay processing unit when the reference delay data signal and the small delay data signal cannot be matched, and increases the reference delay data signal and the large delay data signal. When the data signal cannot be matched, the reference delay amount of the delay processing unit may be decreased.

In such a data transfer device, the capturing unit compares the data captured from the reference delay data signal with the data captured from the small delay data signal based on the clock signal, and when the matching is not achieved. The delay control unit is configured to output a delay plus signal, compare the data fetched from the reference delay data signal with the data fetched from the large delay data signal, and output a delay minus signal if a match is not achieved. When the delay plus signal is output from the capture unit, the reference delay amount of the delay processing unit is increased, and when the delay minus signal is output from the capture unit, the reference delay amount of the delay processing unit is decreased. You may let them.

In such a data transfer apparatus, the first and second delay compensation amounts may be set to be smaller than half the data width of the data signal.

Furthermore, in such a data transfer device, the frequency of the clock signal may be 1 GHz or more.

In addition, the camera according to the present invention includes any one of the data transfer devices described above.

It is a block diagram which shows the structural example of the data transfer apparatus which concerns on this invention. It is a block diagram which shows the structural example of a delay processing part, (a) shows the structure of the whole delay processing part, (b) shows the structure of the principal part. It is a block diagram which shows the structural example of a taking-in part. It is a flowchart which shows the initial setting process of the reference | standard delay amount performed with a delay control part. It is a timing chart which shows the example of initial setting of the reference delay amount. 5 is a timing chart showing an example of correcting a reference delay amount, where (a) shows a data signal at the time of initial setting, (b) shows a data signal when a delay time increases due to a temperature rise or the like, and (c) Indicates a data signal after correction of the reference delay amount. It is a flowchart which shows the correction process of the reference | standard delay amount performed with a delay control part. (A) shows an output example of the capture unit in the initial state, (b) shows an output example of the capture unit in the case of S204, and (c) shows an output example of the capture unit in the case of S206. Indicates.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the case where the data transfer apparatus according to this embodiment is applied to a digital camera will be described with reference to FIG. In FIG. 1, a data transfer device is a data transfer device provided in the signal processing circuit 3 with the image sensor 2 of the camera 1 as an output device, the signal processing circuit 3 as an input device, and a data signal output from the image sensor 2. An example of a configuration in which the image is captured by the unit 4 and transferred to the image processing unit 5 is shown.

In this camera 1, the image sensor 2 is connected to one end of two data signal lines DATA 0 and DATA 1 that output image signals (data signals) in parallel and one end of a clock signal line CLK that outputs a clock signal. . The other ends of these signal lines DATA0, DATA1, and CLK are connected to the data transfer unit 4 of the signal processing circuit 3, respectively. By providing the two signal lines DATA0 and DATA1 in this way, in the data transfer between the image sensor 2 and the signal processing circuit 3, an image signal (data signal) is transmitted in parallel using two channels using a clock signal. Can be transferred. Note that the image sensor 2 also has a function of outputting test data to be described later to the data signal lines DATA0 and DATA1.

The signal processing circuit 3 is a digital front-end circuit that performs various types of image processing on the digital image signal (data signal) input from the image sensor 2. The signal processing circuit 3 includes a data transfer unit 4, an image processing unit 5, and a storage unit 6. Further, each of the data transfer units 4 includes two delay processing units 7 and capture units 8 and a delay control unit 9. In the signal processing circuit 3, the delay processing unit 7, the capturing unit 8, and the storage unit 6 are each connected to a delay control unit 9. The image processing unit 5 is an ASIC that performs various types of image processing (defective pixel correction, gradation correction, white balance adjustment, edge enhancement, etc.) on a digital image signal. In FIG. 1, the flow of the data signal (image signal) is indicated by a solid line, and the flow of the control signal is indicated by a broken line.

The above-described delay processing unit 7 and capturing unit 8 are arranged for each of the signal lines DATA0 and DATA1. The delay processing unit 7 and the capturing unit 8 of each set are connected in series, and each delay processing unit 7 is connected to one of the data signal lines DATA0 and DATA1. The output of each capturing unit 8 is connected to the image processing unit 5 via a signal line 19. Each capturing unit 8 is connected to a clock signal line CLK. Further, the delay control unit 9 and each delay processing unit 7 are connected by a signal line 20, and the delay control unit 9 and each take-in unit 8 are connected by a signal line 21. Note that the delay processing unit 7 and the capturing unit 8 of each set have the same configuration. Therefore, in the following description, the delay processing unit 7 and the capturing unit 8 connected to the data signal line DATA0 will be described, and the description of the delay processing unit 7 and the capturing unit 8 connected to the data signal line DATA1 will be omitted. To do.

The delay processing unit 7 is a circuit that controls the delay amount of the data signal output from the data signal line DATA0. As shown in FIG. 2A, the delay processing unit 7 includes a plurality of delay elements (buffers, etc.) 11 connected in series in a plurality of stages, and a plurality of paths 12 connected to the outputs of the respective delay elements 11. And a selector 10 for selecting one of these paths 12. The signal line DATA0 is connected to the input terminal of the first stage of the delay element 11 (delay 1 in FIG. 2A). The delay processing unit 7 is configured such that signals passing through the three paths 12 selected by the selector 10 are output from the three signal lines 13 (13a to 13c) connected to the selector 10. . The above three paths are selected by the selector 10 based on the reference delay switching signal A and the delay compensation amount signal N transmitted from the delay control unit 9 via the signal line 20. Specifically, as shown in FIG. 2B, the output of the A-stage delay element (delay A in FIG. 2B) designated by the reference delay switching signal A, that is, the A-stage delay A signal that has passed through the element 11 (hereinafter referred to as “reference delay data signal N0”) is output to the signal line 13a. Further, the delay element 11 (the Ath stage) N stages before the Ath stage has a delay quantity smaller than the delay quantity by the delay element 11 from the first stage to the Ath stage (referred to as “reference delay quantity”). A signal (hereinafter referred to as “small delay data signal N−”) that has passed through the −N stage delay element 11) is output from the signal line 13b. Further, a signal having a delay amount larger than the reference delay amount and having passed through the delay element 11 N stages after the A stage (the A + N delay element 11) (hereinafter referred to as “large delay data signal N +”). Is output from the signal line 13c. As apparent from the configuration of FIG. 2, the amount by which the data signal input via DATA 0 in the delay processing unit 7 is delayed is determined by the number of delay elements 11. Therefore, the reference delay switching signal A and the delay compensation amount signal N are actually expressed as the number of stages of the delay elements 11.

FIG. 2B shows a case where the delay compensation amount 1 (one stage of the delay element 11) is designated as the delay compensation amount signal N, and the signal that has passed through the delay A-1 and the delay A + 1 is shown. These are output as a small delay data signal N− and a large delay data signal N +, respectively. In the example of this embodiment, the delay time of one delay element 11 is about 1/10 or less of the data transfer period (when the data transfer period is 1 GHz, the delay time of one delay element 11 is 100 picoseconds or less). And In the example of the present embodiment, the number of delay elements 11 is at least 1.5 times the data transfer period of the entire delay element 11 (15 when the data transfer period is 1 GHz and the delay time of the delay element 11 is 100 picoseconds). The margin may be ensured by setting it to be several times the data transfer cycle. As described above, the delay processing unit 7 is used to adjust the delay amount of the data signal captured by the capturing unit 8 with respect to the clock signal. Further, the delay compensation amount signal N is set in a range where the delay compensation amount is smaller than half of the data width of the data signal. In this embodiment, the delay compensation amount for the small delay data signal is the same as the delay compensation amount for the large delay data signal, but they may be different. In this case, the signal transmitted from the delay control unit 9 via the signal line 20 includes the reference delay switching signal A, the first delay compensation amount signal N1 for the small delay data signal N−, and the large delay data signal N +. Becomes the second delay compensation amount signal N1.

The fetch unit 8 is a value indicated by the input data signal (reference delay data signal N0) in synchronization with the rising or falling edge of the clock signal input from the clock signal line CLK or both the falling and rising timings. Is to capture. As shown in FIG. 3, the fetch unit 8 includes three flip-flop circuits (FF) 14 to 16 and two exclusive OR circuits (EXOR) 17 and 18. The reference delay data signal N0 output to the signal line 13a of the delay processing unit 7 is input to the D terminal of the first flip-flop circuit 14. The small delay data signal N− output to the signal line 13b is input to the D terminal of the second flip-flop circuit 15. The large delay data signal N + output to the signal line 13c is input to the D terminal of the third flip-flop circuit 16. The clock signal line CLK is connected to the CK terminals of the first to third flip-flop circuits 14 to 16, and the clock signal output from the image sensor 2 is input to these CK terminals. The flip-flop circuits 14 to 16 hold the value (“1” or “0”) of the signal input to the D terminal at the time of rising or falling of the clock signal or both of falling and rising, and the Q terminal Is output from The value output from the Q terminal of the first flip-flop circuit 14 is output to the image processing unit 5 through the signal line 19 and simultaneously output to the delay control unit 9 through the signal line 21 as the data signal Sd. The

Also, the Q output of the first flip-flop circuit 14 and the Q output of the second flip-flop circuit 15 are connected to the two IN terminals of the first exclusive OR circuit 17, respectively. The delay plus signal Sp is output from the OUT terminal of the first exclusive OR circuit 17 to the delay control unit 9 via the signal line 21. Further, the Q output of the first flip-flop circuit 14 and the Q output of the third flip-flop circuit 16 are connected to the two IN terminals of the second exclusive OR circuit 18, respectively. A delay minus signal Sn is output from the OUT terminal of the second exclusive OR circuit 18 to the delay control unit 9 via the signal line 21. The first and second exclusive OR

circuits

17 and 18 are configured such that “0” is output from the OUT terminal when the input values of the two IN terminals are the same, and “1” is output when they are different. ing. That is, when the clock signal rises or falls, “0” is output as the delay plus signal Sp when the reference delay data signal N0 and the small delay data signal N− match, and “1” when they are different. Is output. Similarly, “0” is output as the delay minus signal Sn when the reference delay data signal N0 matches the large delay data signal N +, and “1” is output when they are different. That is, when the reference delay data signal N0 and the small delay data signal N− cannot be matched, the capturing unit 8 outputs the delay plus signal Sp, and the reference delay data signal N0 and the large delay data signal N + When the matching cannot be achieved, the delay minus signal Sn is output.

When the delay compensation amount (the delay compensation amount for the small delay data signal and the delay compensation amount for the large delay data signal) is set too large, or when the eye pattern becomes small due to a temperature change or the like, FIG. In the flow process, there is a possibility that the outputs of the two exclusive OR circuits (EXOR) 17 and 18 may become 1, so a process for reducing the delay compensation amount is required. However, normally, if a delay compensation amount is set in consideration of eye pattern reduction, a process for reducing the delay compensation amount is not necessary. Alternatively, a process for reducing the delay compensation amount may be added to the flow process of FIG.

The delay control unit 9 is a processor that controls each group of the delay processing unit 7 and the capturing unit 8 independently. For example, the delay control unit 9 is based on signals (data signal Sd, delay plus signal Sp, and delay minus signal Sn) input via the signal line 21 connected to the capturing unit 8. It controls the reference delay amount (the number of delay stages) (detailed control method will be described later). The storage unit 6 includes a storage medium such as a register. The storage unit 6 stores data such as a reference delay amount (the number of delay stages) of the delay processing unit 7 controlled by the delay control unit 9.
(Reference delay amount initial setting process)
Now, an operation example of the data transfer unit 4 configured as described above will be described. First, a method for initially setting the reference delay amount of the delay processing unit 7 by the delay control unit 9 will be described with reference to FIG. Note that the processing shown in FIG. 4 is executed, for example, at a timing immediately after the camera 1 is turned on or just before the recording image data is transferred from the image sensor 2. In the process shown in FIG. 4, the delay control unit 9 determines the reference delay amount in the delay processing unit 7 using the test data output from the image sensor 2. The test data in this case is composed of a binary data string in which “0” and “1” are repeated in the same cycle as the clock signal.

First, the delay control unit 9 initializes the reference delay amount of the delay processing unit 7 (for example, sets the number of delay stages to 0) and instructs the image sensor 2 to start outputting test data (step S101). Thus, test data is output from the image sensor 2 to the data signal lines DATA0 and DATA1 in synchronization with the clock signal. Then, the test data of the data signal line DATA0 is input to the capturing unit 8 via the delay processing unit 7. Next, the delay control unit 9 determines whether or not the data signal Sd captured by the capturing unit 8 and input to the delay control unit 9 at the rising edge of the clock signal is “0” (step S102). . When the data signal Sd is not “0” (NO side of S102), the delay control unit 9 increases the reference delay amount (the number of delay stages) by 1, and uses the reference delay amount as the reference delay switching signal A as a delay processing unit. 7 is output. As a result, the delay control unit 9 increases the number of stages of the delay elements 11 that output the reference delay data signal N0 by 1 (step S103). Thereby, the phase of the data signal (test data) input from the data signal line DATA0 can be delayed. Thereafter, the delay control unit 9 returns to step S102 and repeats the above-described operation. Note that the loop from the NO side of step S102 to step S103 is performed until the data signal capturing position in the capturing unit 8 reaches a value of “0” in order to search for the rising position of the signal waveform in the test data. This corresponds to the shift operation.

Next, in step S102, when the data signal Sd is “0” (YES side of S102), the delay control unit 9 is captured by the capture unit 8 at the rising edge of the clock signal, and the delay control unit 9 It is determined whether or not the data signal Sd input to “1” is “1” (step S104). When the data signal Sd is not “1” (NO side of S104), the delay control unit 9 increases the reference delay amount (the number of delay stages) by 1, and uses the reference delay amount as the reference delay switching signal A as a delay processing unit. 7 is output. Thereby, the delay control unit 9 increases the number of stages of the delay elements 11 to which the reference delay data signal N0 is output by 1 (step S105). Thereby, the phase of the data signal (test data) input from the data signal line DATA0 can be delayed. Thereafter, the delay control unit 9 returns to step S104 and repeats the above-described operation. Note that the loop from the NO side to step S105 in step S104 corresponds to an operation of shifting the data signal acquisition position in the acquisition unit 8 to the rising position of the signal waveform in the test data.

In step S104, when the data signal Sd is “1” (YES in S104), the delay control unit 9 temporarily stores the current reference delay amount in the storage unit 6 as “delay_start”. (Step S106). The reference delay amount “delay_start” stored in step S106 corresponds to the rising position of the signal waveform in the test data (see FIG. 5).

Further, the delay control unit 9 determines whether or not the data signal Sd captured by the capturing unit 8 and input to the delay control unit 9 at the rising edge of the clock signal is “0” (step S107). When the data signal Sd is not “0” (NO side of S107), the delay control unit 9 increases the reference delay amount (the number of delay stages) by 1, and uses the reference delay amount as the reference delay switching signal A as a delay processing unit. 7 is output. Thereby, the delay control unit 9 increases the number of stages of the delay elements 11 to which the reference delay data signal N0 is output by 1 (step S108). Thereby, the phase of the data signal (test data) input from the data signal line DATA0 can be delayed. After that, the delay control unit 9 returns to step S107 and repeats the above operation. Note that the loop from the NO side to step S108 in step S107 corresponds to an operation of shifting the data signal capturing position in the capturing unit 8 to the falling position of the signal waveform in the test data (see FIG. 5).

Then, in step S107, when the data signal Sd is “0” (YES side of S107), the delay control unit 9 temporarily stores the current reference delay amount as “delay_end” in the storage unit 6. (Step S109). The reference delay amount “delay_end” stored in step S109 corresponds to the falling position of the signal waveform in the test data (see FIG. 5).

Finally, the delay control unit 9 uses the reference delay amount “delay_start” acquired in step S106 and the reference delay amount “delay_end” acquired in step S109, and uses the reference delay of the delay processing unit 7 during data communication. An initial value of the amount (reference capture position of the data signal) is determined (step S110). Specifically, the delay control unit 9 calculates and determines the reference capture position of the data signal by the following equation (1).

Reference capture position = (delay_end−delay_start) / 2 + delay_start (1)
The reference capture position (initial value of the reference delay amount) obtained in step S110 is located between the rising position and the falling position of the signal waveform of the test data (see FIG. 5). For this reason, in the data communication performed after the initial setting, the data signal capture timing is stabilized by the reference delay amount given by the delay processing unit 7, so that a code error during data transfer is reduced. Further, the reference capture position (initial value of the reference delay amount) is determined based on the actual measurement value of the test data. For this reason, the above setting operation also absorbs errors due to variations in wiring length, elements, and environmental changes, so that the reliability of the data transfer unit 4 can be further improved. Furthermore, if the data transfer unit 4 is configured as described above, the initial value of the reference delay amount can be adjusted independently for each of the data signal line DATA0 and the data signal line DATA1. Therefore, the parallel data transfer unit 4 can avoid the isometric wiring design, and the degree of freedom of layout of elements and wirings is greatly improved at the time of designing.
(Reference delay correction)
However, it is assumed that the initial reference delay amount of the delay processing unit 7 is adjusted by the delay control unit 4 by the above processing, and the data signal capturing position in the capturing unit 8 is adjusted to a position where data can be stably captured. However, the following problems may occur. For example, when high-speed data transfer with a clock signal frequency of 1 GHz or more is performed, if a temperature change or a voltage change occurs in the data transfer unit 4, a delay (for example, one delay element 11 occurs in the data signal). Change in the delay time, delay time in the signal line, etc.) and accurate data cannot be obtained.

For example, when the temperature increases from the state of the reference delay data signal shown in FIG. 6A and the delay increases, and when the state of FIG. Compared with the case of a), it is inverted (becomes “0”), and an accurate value cannot be taken. Therefore, the data transfer unit 4 according to the present embodiment is configured such that an optimum value can be taken in by correcting the reference delay amount in the delay processing unit 7 in accordance with the state of the data signal. Hereinafter, a reference delay amount correction method will be described with reference to FIG.

As shown in steps S101 to S110 described above, the delay control unit 9 determines an initial reference delay amount using the test data (step S201). Thereafter, the delay control unit 9 sets the number of stages of the delay elements 11 by outputting the reference delay amount as the reference delay switching signal A to the delay processing unit 7. Further, the delay control unit 9 sets a reference delay amount and a delay compensation amount in the selector 10 by outputting a predetermined delay compensation amount as a delay compensation amount signal N to the delay processing unit 7 (step S202).

The delay controller 9 uses the delay plus signal Sp and the delay minus signal Sn output from the fetching unit 8 while fetching the data signal by the fetching unit 8 in such a state. The reference delay amount is corrected by the following operation.

Specifically, first, the delay control unit 9 determines whether or not the delay plus signal Sp is “1” (step S203). When the delay plus signal Sp is “1” (YES side of S203), the delay control unit 9 adds 1 to the current reference delay amount (number of stages) and uses the reference delay amount as the reference delay switching signal A. By outputting to the delay processing unit 7, the number of stages of the delay elements 11 is set (step S204).

The fact that the delay plus signal Sp is “1” means that the reference delay data signal N0 captured at the reference capture position and the small delay data signal N output from the delay element 11 of −N stages from the reference delay position. -Means that the value is different. That is, the delay amount of the data signal delayed by the current reference delay amount is shorter (the phase of the data signal is advanced) than when the data signal is initially set. Therefore, the delay control unit 9 in step S204 adds 1 to the current reference delay amount (number of stages) to increase the delay amount of the data signal to correct the phase (see FIG. 8B). . After the reference delay amount is increased by 1 in step S204, the process returns to step S203 and the same operation is repeated.

On the other hand, if the delay plus signal Sp is not “1” in step S203 (NO side of S203), the delay control unit 9 next determines whether or not the delay minus signal Sn is “1” (step S203). S205). When the delay minus signal Sn is “1” (YES side of S205), the delay control unit 9 subtracts 1 from the current reference delay amount (number of stages) and sets the reference delay amount to the reference delay switching signal. By outputting it to the delay processing unit 7 as A, the number of stages of the delay elements 11 is set (step S206).

The fact that the delay minus signal is “1” means that the value of the reference delay data signal N0 fetched at the reference delay position and the large delay data signal N + output from the delay element 11 of + N stages from the reference delay position. Means different. In other words, the delay amount of the data signal delayed by the current reference delay amount is longer (the phase of the data signal is delayed) than when it was initially set. Therefore, the delay control unit 9 in step S206 performs correction to reduce the delay amount of the data signal and advance the phase by subtracting 1 from the current reference delay amount (number of stages) (see FIG. 8C). ). After the reference delay amount (stage number) is decreased by 1 in step S206, the process returns to step S203 and the same operation is repeated.

If the delay minus signal Sn is not “1” in step S205 (NO side of S205), the process returns to step S203 as it is and repeats the same operation. Note that the adjustment amount of the reference delay amount (stage number) when the delay plus signal Sp or the delay minus signal Sn becomes “1” may be one or more. For example, when the delay compensation amount is three stages of delay elements, the adjustment amount of the reference delay amount (number of stages) may be two stages or three stages.

The data transfer apparatus according to the present embodiment can more appropriately correct in real time the delay amount of data that changes from time to time due to temperature change or voltage change, by the processing loop from S203 to S206.

For example, as shown in FIG. 6B, when the data signal fetched by the reference delay position due to an increase in temperature due to a temperature rise differs from the data signal delayed by + N stages from the reference delay position, As shown in FIG. 6C, by reducing the reference delay amount until the same value is reached (until the delay minus signal Sn becomes “0”), the data can be stably captured by the capturing unit 8. The data signal capture position can be corrected. Therefore, even when data transfer is performed using a clock signal of 1 GHz or higher, the data acquisition timing should always be kept stable in response to changes in transmission path characteristics and data output timing due to temperature and other factors. Can do.

In the initial setting of the reference delay amount of the delay processing unit 7 described above, processing for determining whether the data Sd captured by the capturing unit 8 is “0” or “1” (step S102, In S104 and S107), in consideration of fluctuations in the data signal due to jitter or the like, it is determined that it is “0” or “1” when it is “0” or “1” continuously acquired several times. You may comprise so that it may do. Further, in the above-described correction process of the reference delay amount, when the transmission characteristics of the system are greatly fluctuated, the delay stage number is set to n times these values by the delay plus signal Sp or the delay minus signal Sn. May be. The delay compensation amount N output from the delay control unit 9 to the delay processing unit 7 may be set to an optimal value depending on the number of stages of the delay elements 11 and the transfer speed (however, as described above, the data signal Range less than half of the data width).

From the above detailed description, the features and advantages of the embodiment will become apparent. It is intended that the scope of the claims extend to the features and advantages of the embodiments as described above without departing from the spirit and scope of the right. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to use appropriate improvements and equivalents within the scope disclosed in.

1 Digital Camera 4 Data Transfer Unit (Data Transfer Device)
7 Delay processing section 8 Capture section 9 Delay control section

Claims

A data transfer device for transferring a data signal in synchronization with a clock signal,
A reference delay data signal obtained by delaying the data signal by a reference delay amount, a small delay data signal delayed by a first delay compensation amount from the reference delay amount, and a second delay from the reference delay amount. A delay processing unit that outputs a large delay data signal that is greatly delayed by a delay compensation amount;
A capturing unit that captures and outputs data from the reference delay data signal based on the clock signal;
The reference delay amount in the delay processing unit is controlled based on at least one of matching between the reference delay data signal and the small delay data signal and matching between the reference delay data signal and the large delay data signal. A data transfer device comprising: a delay control unit;
When the reference delay data signal and the small delay data signal cannot be matched, the delay control unit increases the reference delay amount of the delay processing unit to increase the reference delay data signal and the large delay data. The data transfer apparatus according to claim 1, wherein when the signal cannot be matched, the reference delay amount of the delay processing unit is decreased.
The fetching unit compares the data fetched from the reference delay data signal with the data fetched from the small delay data signal based on the clock signal, and outputs a delay plus signal when matching is not achieved. The data fetched from the reference data signal and the data fetched from the large delay data signal are compared, and when a match is not achieved, a delay minus signal is output.
The delay control unit increases the reference delay amount of the delay processing unit when the delay plus signal is output from the capturing unit, and when the delay minus signal is output from the capturing unit. The data transfer device according to claim 1, wherein the reference delay amount of the delay processing unit is reduced.
The data transfer apparatus according to any one of claims 1 to 3, wherein the first delay compensation amount and the second delay compensation amount are set to be smaller than a half of a data width of the data signal.
The data transfer device according to any one of claims 1 to 4, wherein a frequency of the clock signal is 1 GHz or more.
A camera having the data transfer device according to any one of claims 1 to 5.