JP2010245664A - Image processor, method of adjusting sampling position, and a/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for appropriately setting a sampling position of data on a pixel unit in a control board, in a system with an A-D converter without incorporating a circuit for generating dummy data. <P>SOLUTION: This image processor includes: an A-D conversion part 230 for converting input analog pixel data to digital pixel data to be outputted; an offset part 210 for adapting a voltage range effective as a signal of analog pixel data supplied from an image sensor 100 to an input range of the A-D conversion part 230; and a digital data processing part 310 for adjusting the sampling position of the digital pixel data outputted from the A-D conversion part 230. The offset part 210 changes an offset value, and a digital data part 230 adjusts the sampling position of the digital pixel data outputted from the A-D conversion part 230 based on the amount of the change of the digital pixel data. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, a sampling position adjustment method, and an A / D conversion apparatus.

  In general, in an image reading apparatus such as a scanner apparatus, a read signal (analog data) obtained by an image sensor is converted into image data (digital data) by an A / D converter. The image data converted by the A / D converter is supplied to the image processing unit of the control board, and various image processing (for example, shading correction) is performed (for example, Patent Document 1).

  In the image reading apparatus, it is necessary to accurately process the digital data sent from the A / D converter in units of pixels. That is, the image processing unit must set the sampling position appropriately so that digital data from the A / D converter can be correctly received. For this reason, particularly when performing high-speed reading, a conventional image reading apparatus includes a circuit for generating dummy data in the A / D converter, and a part of the image data output from the A / D converter (for example, Some of the sampling positions are appropriately set by replacing the predetermined number of leading pixels) with dummy data of a predetermined value.

JP 2008-227823 A

  However, it is not common to provide a circuit for generating dummy data in the A / D converter, and the manufacturing cost of the image reading apparatus is increased.

  An object of the present invention is to provide a technique for appropriately setting a sampling position of data on a pixel basis on a control board in a system with an A / D converter that does not include a circuit for generating dummy data. And

  The present invention for solving the above-mentioned problems is an image processing apparatus, which converts A / D conversion means for converting input analog pixel data into digital pixel data and outputs the analog pixel data supplied from an image sensor. Offset adjusting means for adjusting a voltage range effective as a signal of the A / D converting means, sampling adjusting means for adjusting a sampling position of digital pixel data output from the A / D converting means, The offset adjustment means changes the offset value, and the sampling adjustment means adjusts the sampling position of the digital pixel data output from the A / D conversion means based on the change amount of the digital pixel data. .

1 is a schematic configuration diagram of an image processing apparatus according to an embodiment of the present invention. 6 is a timing chart for clock signal input / output and digital data input / output. It is a figure which shows the schematic data structure of 1 pixel data which an A / D conversion part outputs. It is a figure which shows the timing when digital data arrives at a digital data processing part, and the content of digital data. It is a flowchart for demonstrating the determination process of the sampling position performed with a control board. It is a figure which shows the example (example 1) when the arrival timing of dummy data delays and the arrival timing and the change point of an internal clock do not overlap. An example (example 2) in which the arrival timing of the dummy data is delayed and the change timing of the internal clock overlaps with the arrival timing is shown. It is a figure which shows the schematic data structure of the dummy data preserve | saved at a memory | storage device.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic configuration diagram of an image processing apparatus 50 to which an embodiment of the present invention is applied.

  The image processing device 50 is, for example, a scanner device, and includes an image sensor 100, an A / D converter 200, and a control board 300 as illustrated.

  The image sensor 100 outputs a reading signal of a document or the like (analog data indicating luminance values of RGB colors) to the A / D converter 200. Specifically, the image sensor 100 receives light reflected from a document or the like, reads out the electric charge accumulated according to the amount of received light as a voltage, and outputs the voltage to the A / D converter 200.

  The A / D converter 200 converts (quantizes) the analog data (read signal) output from the image sensor 100 into digital data, and outputs the digital data to the control board 300 via a transmission path such as a harness.

  For example, the A / D converter 200 includes an offset unit 210, an amplification unit 220, an A / D conversion unit 230, and an offset register 240 as illustrated.

  The offset unit 210 and the amplification unit 220 are provided in order to match the voltage range effective as a signal of the read signal supplied from the image sensor 100 with the input range of the A / D conversion unit 230. In general, the offset unit 210 is used to adjust the minimum value of the effective voltage range so as to match the minimum value of the input range of the A / D conversion unit 230. The amplifying unit 230 is used to adjust the maximum value of the effective voltage range so as to match the maximum value of the input range of the A / D conversion unit 230.

  Specifically, the offset unit 210 is composed of an operational amplifier or the like, and amplifies the difference value between the read signal supplied from the image sensor 100 and the offset value (offset signal) set in the offset register 240. To 220.

  Then, the amplification unit 220 amplifies the read signal (difference value) output from the offset unit 210 and outputs the amplified signal to the A / D conversion unit 230. For example, the amplification unit 220 includes an amplification circuit.

  The A / D converter 230 converts the analog signal (amplified read signal) output from the amplifier 220 into digital data. However, when the input value (the value of the analog signal output from the amplification unit 220) is negative, the A / D conversion unit 230 outputs “0” data. Then, the A / D conversion unit 230 outputs digital data to the control board 300 in synchronization with a clock signal (“input clock” shown in the figure) output from the clock output unit 320 of the control board 300.

  The offset register 240 receives the setting from the offset setting unit 330 of the control board 300 and stores the offset value. Then, the offset register 240 supplies a voltage (offset signal) corresponding to the stored offset value to the offset unit 210. Note that, as an initial value, a set value such that the offset adjustment amount is 0, for example, “0” is stored in the offset register 240.

  Further, the offset register 240 of the present embodiment can accept the setting from the offset setting unit 330 and change the stored offset value. For example, the value can be changed to a value “1” smaller than the initial value, a value “2” smaller than the initial value, and the value of the digital data is decreased.

  Hereinafter, digital data generated by A / D conversion based on an analog signal output by sequentially changing offset values set in the offset register 240 is referred to as “dummy data”. Using this, the sampling timing is adjusted.

  The control board 300 is configured by a chip (SoC) on which the main functions of the image processing apparatus 50 are mounted. As illustrated, a digital data processing unit 310, a clock output unit 320, and an offset setting unit 330 are provided on the control board 300.

  The clock output unit 320 generates a clock signal for timing the operation in the image processing apparatus 50. Then, the clock output unit 320 supplies the generated clock signal to the digital data processing unit 310 and the A / D conversion unit 230. Hereinafter, a clock signal output to the digital data processing unit 310 is referred to as an “internal clock”, and a clock signal output to the A / D conversion unit 230 is referred to as an “output clock”. The output clock is supplied to the A / D converter 230 via a transmission line such as a harness.

  The digital data processing unit 310 performs various correction processes on the image data output from the A / D converter 200 in synchronization with the internal clock output from the clock output unit 320. For example, the digital data processing unit 310 performs shading correction and gamma correction on the image data output from the A / D converter 200.

  Here, the digital data processing unit 310 performs various correction processes on the digital data (image data) output from the A / D converter 200 in units of pixels. Therefore, the digital data processing unit 310 must accurately specify pixel data for one pixel from the digital data continuously output from the A / D converter 200. However, since each pixel data constituting the image data does not include data for identifying a delimiter position of the pixel data (hereinafter referred to as “boundary position”), the boundary position of the pixel data from the data content Cannot be specified.

  Therefore, the digital data processing unit 310 uses the above-described dummy data to identify the boundary position of each pixel data that constitutes the image data. Specifically, the digital data processing unit 310 specifies the boundary position of the dummy data before specifying the boundary position of each pixel data constituting the image data. Then, the digital data processing unit 310 specifies the boundary position of each pixel data constituting the image data using the specified boundary position of the dummy data as a reference (for example, a sampling start position). Details of the processing (sampling position determination processing) performed by the digital data processing unit 310 will be described later.

  The offset setting unit 330 sets the offset value of the offset register 240. In this embodiment, when the A / D converter 200 generates dummy data, the offset setting unit 330 sets an offset value in the offset register 240 such that the output of the A / D converter 200 is not “0”. Then, the offset value is decreased stepwise (for example, by “1”) until the output of the A / D converter 200 becomes a negative value (“0” or less).

  The image processing apparatus 50 to which this embodiment is applied has the above configuration. However, the configuration of the image processing apparatus 50 is not limited to this. For example, the image processing apparatus 50 may have another configuration for functioning as a multifunction peripheral, a copier, or the like.

  And each component provided on the control board 300 is comprised by one ASIC (Application Specific Integrated Circuit). The main components provided on the control board 300 include a CPU as a main control device, a ROM storing a program, a RAM that temporarily stores data as a main memory, a host, and the like. It can also be achieved by a general computer having an interface for controlling input / output and a system bus serving as a communication path between each component.

  The A / D converter 200 can be configured by an analog front end IC (Integrated Circuit).

  Note that the offset unit 210, the offset register 240, the offset setting unit 330, and the like are not provided for the purpose of generating dummy data, and in order to perform offset adjustment for securing a dynamic range for an analog signal, It is generally provided in the image processing apparatus 50 such as a scanner apparatus.

  In addition, each of the above-described constituent elements is classified according to main processing contents in order to facilitate understanding of the configuration of the image processing apparatus 50. The present invention is not limited by the way of classification and names of the constituent elements. The configuration of the image processing device 50 can be classified into more components depending on the processing content. Moreover, it can also classify | categorize so that one component may perform more processes. Further, the processing of each component may be executed by one hardware or may be executed by a plurality of hardware.

  Next, the timing at which the clock output unit 320 of the present embodiment outputs a clock signal (internal clock, output clock) and the timing at which digital data (image data, dummy data) arrives at the digital data processing unit 310 are shown in FIG. Will be described in detail.

  FIG. 2 is a timing chart of the clock signal output from the clock output unit 320. The internal clock and the output clock output from the clock output unit 320 are general clock signals as illustrated. The digital data processing unit 310 can perform various correction processes in synchronization with the rise and fall of the internal clock supplied from the clock output unit 320.

  FIG. 2 also shows a timing chart of an input clock input to the A / D conversion unit 230, digital data output from the A / D conversion unit 230, and digital data reaching the digital data processing unit 310. . The A / D conversion unit 230 outputs digital data in synchronization with the rising and falling edges of the input clock output from the clock output unit 320 and input to the A / D conversion unit 230. In the illustrated example, the A / D converter 230 outputs digital data for one pixel data (for example, 16 bits) in two cycles of the input clock. This is an example in which the width of the transmission path (bus width N) for transmitting digital data from the A / D conversion unit 230 to the digital data processing unit 310 is 4 bits.

  FIG. 3 is a diagram illustrating a schematic data structure of one pixel data output from the A / D conversion unit 230. As shown in the figure, the A / D conversion unit 230 supplies one pixel data to the digital data processing unit 310 by outputting the digital data four times (AD0, AD1, AD2, AD3) every four bits.

  Returning to FIG. 2, the clock output unit 320 outputs the internal clock and the output clock in synchronization.

  Then, as described above, the output clock is supplied to the A / D conversion unit 230 via a transmission line such as a harness. Therefore, a difference (time difference) is likely to occur between the timing at which the output clock is output from the clock output unit 320 and the timing at which the output clock reaches the A / D conversion unit 230 as the input clock. In the illustrated example, the rising timing T2 of the input clock is delayed with respect to the rising timing T1 of the output clock ("T2-T1" time).

  Similarly, digital data (image data, dummy data) output from the A / D conversion unit 230 is also supplied to the digital data processing unit 310 via a transmission path such as a harness. Therefore, a difference (time difference) is likely to occur between the timing at which digital data is output from the A / D conversion unit 230 and the timing at which the digital data reaches the digital data processing unit 310.

  In examples 1 and 2 shown in the figure, timings T3 and T3 ′ at which digital data (first bit of pixel data) reaches the digital data processing unit 310 are timings T2 at which the digital data is output from the A / D conversion unit 230. ("T3-T2", "T3'-T2" time). Here, Example 1 is an example in which the arrival of digital data is delayed and the arrival timing T3 does not overlap the change point (rising edge, falling edge) of the internal clock. Example 2 is an example in which the arrival timing T3 'and the change point of the internal clock overlap due to the delay of arrival of the digital data.

  As described above, the arrival timings T3 and T3 ′ of the digital data may be greatly delayed from the timing T1 when the internal clock reaches the digital data processing unit 310 (“T3-T1”, “T3′-T1”). "time).

  When such a shift occurs, the bit received at the timing T1 in the digital data processing unit 310 is not a bit at the boundary position (for example, the head position) of the pixel data. Therefore, the digital data processing unit 310 cannot specify the boundary position of the pixel data.

  In the example shown in Example 1, the digital data processing unit 310 can correctly sample image data in synchronization with the internal clock. On the other hand, in the case of the example shown in Example 2, since the digital data processing unit 310 cannot correctly sample image data in synchronization with the internal clock, the internal clock and a predetermined adjustment amount (for example, 1/4 clock) Sampling is performed at a timing shifted by D.

  FIG. 4 is a diagram illustrating the timing at which digital data (bits at the boundary position) reaches the digital data processing unit 310 and the contents (luminance values) of the digital data.

  As shown in the drawing, when the bit received at timing T1 based on the internal clock is set as the boundary position (first bit) of the pixel data and divided by a predetermined bit width (16 bits), an attempt is made to recognize image data for one pixel data ( When a delay occurs in the transmission of image data, the erroneous range is recognized as one pixel data.

  However, in the present embodiment, the A / D converter 230 is caused to output a plurality of dummy data different by a predetermined value before outputting the image data. Therefore, the digital data processing unit 310 can correctly recognize the dummy data for one pixel data by identifying the variation amount of the dummy data.

  If the dummy data for one pixel can be correctly recognized, the digital data processing unit 310 can correctly recognize the pixel data for the image data output following the dummy data. As a result, the digital data processing unit 310 performs various correction processes on the image data even if the image data (bits at the boundary position) arrives with a shift (delayed) from the scheduled timing. Can be done in units.

<Sampling position determination process>
Next, a characteristic operation of the image processing apparatus 50 according to the present embodiment will be described. FIG. 5 is a flowchart for explaining the “sampling position determination process” performed by the digital data processing unit 310.

  For example, the digital data processing unit 310 receives an instruction from the user and starts a sampling position determination process.

  After starting the sampling position determination process, the digital data processing unit 310 first sets a default for the sampling timing of image data (including dummy data) (step S101). Specifically, the digital data processing unit 310 determines the sampling timing so as to sample the image data in synchronization with the change point (rise, fall) of the internal clock supplied from the clock output unit 320.

  Next, the offset setting unit 330 sets an initial offset value for adjusting the sampling timing (step S102). Specifically, the offset setting unit 330 sets a setting value such that the output digital data of the A / D converter 200 does not become “0” in the offset register 240 of the A / D converter 200 (however, in this embodiment) For example, when “0” is set in the offset register 240, the output when the light source is off is about 4.2).

  Then, the offset unit 210 outputs a differential signal between the read signal supplied from the image sensor 100 and the offset signal output from the offset register 240 to the amplification unit 220. Note that during the processing of this flow, the image sensor 100 supplies a read signal when the light source is off. That is, a read signal indicating a substantially constant luminance value (for example, “4.2”) is continuously supplied from the image sensor 100.

  The amplification unit 220 amplifies the difference signal (read signal) output from the offset unit 210 with a predetermined amplification factor, and outputs the amplified signal to the A / D conversion unit 230.

  Next, the A / D conversion unit 230 converts (quantizes) the read signal output from the amplification unit 220 into digital data to generate dummy data.

  Then, the A / D conversion unit 230 outputs the generated dummy data to the digital data processing unit 310 in synchronization with the clock signal (input clock) from the clock output unit 320 on the control board 300.

  Here, the digital data processing unit 310 reads dummy data (step S103). Specifically, the digital data processing unit 310 sets the dummy data output from the A / D conversion unit 230 to predetermined bits N (for example, 4 bits) in synchronization with the sampling timing determined in step S101 or step S109 described later. Accept (acquire) one by one and sequentially store it in a storage device such as a buffer (store dummy data for at least two pixels per offset value).

  However, as shown in FIG. 2 and the like, the arrival timings T3 and T3 'of the dummy data may be delayed with respect to the change point T1 of the internal clock.

  FIG. 6 shows an example (example 1) in which the arrival timing of dummy data is delayed and the arrival timing does not overlap the change point of the internal clock.

  As shown in Pattern 1 in the figure, the arrival timing T3 of the first bit (pixel data) may be delayed with respect to T1 by not less than (2k + 1/2) clocks and less than (2k + 1) clocks. In this case, if the bit (4 bits) sampled at the timing T1 is recognized as the first bit of the pixel data, the original position is shifted by (2N = 8) bits. However, k is an integer, and the same shall apply hereinafter.

  Further, as shown in pattern 2 in the figure, the arrival timing T4 of the first bit (pixel data) may be delayed with respect to T1 by (2k + 1) clocks or more and less than (2k + 3/2) clocks. In this case, if the bit (4 bits) sampled at the timing T1 is recognized as the first bit of the pixel data, the original position is shifted by (3N = 12) bits.

  Further, as shown in pattern 3 in the figure, the arrival timing T5 of the first bit (pixel data) may be delayed with respect to T1 by (2k + 3/2) clocks or more and less than (2k + 2) clocks. In this case, if the bit (4 bits) sampled at the timing T1 is recognized as the first bit of the pixel data, it matches the original position.

  Further, as shown in the pattern 4 in the figure, the arrival timing T6 of the first bit (pixel data) may be delayed with respect to T1 by not less than (2k) clocks and less than (2k + 1/2) clocks. In this case, if the bit (4 bits) sampled at timing T1 is recognized as the first bit of the pixel data, the original position is shifted by (N = 4) bits.

  FIG. 7 shows an example (example 2) in which the arrival timing of the dummy data is delayed and the arrival timing overlaps with the change point of the internal clock.

  In this case, as described above, the digital data processing unit 310 performs sampling at the timing T1 'shifted from the internal clock by a predetermined adjustment amount (for example, 1/4 clock) D.

  As shown in the pattern 5 in the figure, the arrival timing T5 of the first bit (pixel data) may be delayed by more than (2k + 1/2) clocks and less than (2k + 1) clocks with respect to T1 '. In this case, if the bit (4 bits) sampled at the timing T1 'is recognized as the first bit of the pixel data, the original position is shifted by (2N = 8) bits.

  Further, as shown in the pattern 6 in the figure, the arrival timing T4 of the first bit (pixel data) may be delayed with respect to T1 'by (2k + 1) clocks or more and less than (2k + 3/2) clocks. In this case, if the bit (4 bits) sampled at the timing T1 'is recognized as the first bit of the pixel data, the original position is shifted by (3N = 12) bits.

  In addition, as shown in the pattern 7 in the figure, the arrival timing T5 of the first bit (pixel data) may be delayed with respect to T1 'by (2k + 3/2) clocks or more and less than (2k + 2) clocks. In this case, if the bit (4 bits) sampled at the timing T1 'is recognized as the first bit of the pixel data, it matches the original position.

  Further, as shown in the pattern 8 shown in the figure, the arrival timing T6 of the first bit (pixel data) may be delayed by more than (2k) clocks and less than (2k + 1/2) clocks with respect to T1 '. In this case, if the bit (4 bits) sampled at the timing T1 'is recognized as the first bit of the pixel data, the original position is shifted by (N = 4) bits.

  Returning to FIG. 5, the digital data processing unit 310 determines whether or not it is possible to search for the boundary position (boundary) of the pixel data for the dummy data read in step S103 (step S104). Specifically, the digital data processing unit 310 reads dummy data (last record in FIG. 8 described later) stored last in the storage device in step S103, and determines whether or not all bits are “0”. When all the bits are “0”, the digital data processing unit 310 has already read all the dummy data necessary for searching for the boundary position of the pixel data, so that the boundary position of the pixel data can be searched. judge. On the other hand, when all the bits are not “0”, it is determined that the boundary position of the pixel data cannot be searched because the dummy data necessary for searching the boundary position of the pixel data is insufficient.

  If the digital data processing unit 310 determines that the boundary position of the pixel data can be searched (step S104; Yes), the process proceeds to step S105. On the other hand, when it is determined that the boundary position of the pixel data cannot be searched (step S104; No), the process proceeds to step S106.

  When the process proceeds to step S106, the offset setting unit 330 changes the offset value set in the offset register 240 (step S106). Specifically, the offset setting unit 330 notifies the offset register 240 of the A / D converter 200 of a request for changing the offset value. Then, when the request is notified, the offset register 240 stores an offset value that is smaller than the offset value stored (set) at that time by a predetermined value (for example, “1”). Then, the offset register 240 outputs a voltage (offset signal) corresponding to the changed offset value to the offset unit 210.

  Then, dummy data that has been offset adjusted with the changed offset value reaches the digital data processing unit 310.

  Then, the digital data processing unit 310 and the offset setting unit 330 repeat the processes of steps S103, S104, and S106 until the boundary position (boundary) of the pixel data can be searched.

  FIG. 8 is a diagram showing a schematic data structure of dummy data stored in the storage device in step S103. However, FIG. 8 is an example of dummy data stored in the case of the pattern 1 described above.

  As shown in the drawing, the read dummy data is stored in the storage device for each offset value. Then, each pixel data read continuously with the same offset value is stored in one record. The high order bits of each pixel data in the record have a substantially constant value. This is because the read signal supplied from the image sensor 100 to the offset unit 210 is approximately constant when the light source is off. The lower-order bits are random values due to the influence of noise and the like. For example, in the case where the offset value is “−2”, the upper 8 bits (integer part) are constant values “00000010” (indicated by hexadecimal numbers “0” and “2” in the figure), The lower 8 bits (decimal part) are random values (indicated by “####” in the figure). In accordance with the change of the offset value in step S106, pixel data for each offset value changed by a predetermined value (“1” in the illustrated example) is stored in each record. As shown in the figure, the value of the pixel data of each record changes according to the amount of change in the offset value. For example, the value of the first pixel data will be described. When the offset value is decreased by “1”, the value of the pixel data is also decreased by approximately “1”.

  Returning to FIG. 5, after the boundary position (boundary) of the pixel data can be searched, when the process proceeds to step S105, the digital data processing unit 310 searches for the boundary position of the pixel data (step S105).

  Specifically, the digital data processing unit 310 first reads dummy data as shown in FIG. 8 from the storage device. First, the bit (4 bits) sampled at timing T1 (or T1 ') is used as the first bit, and the dummy data is divided by a predetermined bit width (16 bits). That is, in the example shown in FIG. 8 (when dummy data is delayed as in pattern 1), the data in the arrow range (first delimiter) shown is specified as pixel data.

  Next, the digital data processing unit 310 compares the amount of change in the offset value with the amount of change in the pixel data for the specified pixel data.

  Here, if the pixel data changes according to the amount of change in the offset value, the digital data processing unit 310 converts the first specified pixel data (first delimiter) into the original pixel data (“1” shown in the figure). It is determined that the pixel data is the "th pixel data"). That is, the digital data processing unit 310 performs pixel data when the amount of change in the offset value and the amount of change in the pixel data satisfy a predetermined relationship (for example, when they are substantially coincident or in a substantially proportional relationship). It is determined that the boundary position of is correctly identified.

  On the other hand, if the pixel data does not change in accordance with the amount of change in the offset value, the digital data processing unit 310 uses the original pixel data (the “first” in the figure) as the first specified pixel data (first delimiter). It is determined that the pixel data is not “)”. In the example shown in FIG. 8, the offset value decreases by “1”, whereas the value of the first specified data (first delimiter) changes randomly. Therefore, in the example shown in FIG. 8, it is determined that the first specified data (first delimiter) is not the original pixel data.

  If the first specified pixel data (first division) is not the original pixel data (pixel unit), the digital data processing unit 310 samples the bit (4) sampled next to the timing T1 (or T1 ′). Bit) is the first bit, and dummy data is divided by a predetermined bit width (16 bits) in the same manner as described above. That is, in the example shown in FIG. 8, data in the illustrated arrow range (second segment) is specified as pixel data.

  Similarly to the above, the digital data processing unit 310 compares the change amount of the offset value with the change amount of the pixel data for the specified pixel data.

  The digital data processor 310 shifts the specified pixel data by a predetermined number of bits N (for example, 4 bits) and compares the change amount of the offset value with the change amount of the pixel data. Is repeated until both changes satisfy a predetermined relationship (for example, substantially coincide).

  Thereby, the digital data processing unit 310 can specify the correct boundary position of the pixel data regardless of the delay amount of the dummy data (in the case of pattern 1 to pattern 4). In the example illustrated in FIG. 8, when the data in the illustrated arrow range (third segment) is specified as pixel data, the change amount of the pixel data is substantially “1” with respect to the change amount “1” of the offset value. Therefore, the third segment data can be specified as the original pixel data.

  In the example shown in FIG. 8, when the second delimiter data is specified as the pixel data, the change amount of the pixel data is random with respect to the change amount “1” of the offset value. When the fourth segment data is specified as pixel data, the change amount of the pixel data is substantially “10” with respect to the change amount “1” of the offset value.

  When the digital data processing unit 310 can identify the correct boundary position of the pixel data (step S107; Yes), the digital data processing unit 310 ends this flow. On the other hand, if the correct boundary position of the pixel data cannot be specified even if the pixel data to be specified is shifted in step S105 (step S107; No), the arrival timing of the digital data (for example, T3 ′) Since there is a possibility that the change point of the clock overlaps (delay in example 2 shown in FIG. 2), the process proceeds to step S108.

  When the process proceeds to step S108, the digital data processing unit 310 determines whether or not the number of times the process has shifted to step S108 has reached a predetermined number (for example, twice) (step S108). If it is determined that the predetermined number of times has been reached (step S108; Yes), the digital data processing unit 310 regards it as an error and terminates abnormally. On the other hand, if it is determined that the predetermined number of times has not been reached (step S108; No), the process proceeds to step S109.

  When the process proceeds to step S109, the digital data processing unit 310 changes the sampling timing (step S109). Specifically, the digital data processing unit 310 changes the sampling timing so that sampling is performed at a timing delayed by a predetermined adjustment amount (for example, ¼ clock) D from the internal clock.

  After changing the sampling timing, the digital data processing unit 310 returns the process to step S102, and performs the processes from step S102 to S107 described above. As a result, the digital data processing unit 310 can detect the pixel regardless of the delay amount of the dummy data (in the case of the pattern 5 to the pattern 8) even when the arrival timing of the digital data and the change point of the internal clock overlap. Data boundary position can be specified correctly.

  The digital data processing unit 310 continues sampling after the dummy data by continuing sampling based on the boundary position (for example, sampling start position T3 in the case of pattern 1) of the dummy data specified (determined) in the above flow. Therefore, it is possible to correctly sample image data that arrives in pixel units.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation and application are possible.

  For example, in the embodiment described above, the bus width N for transmitting dummy data from the A / D conversion unit 230 to the digital data processing unit 310 is described as 4 bits. However, the present invention is not limited to this.

  For example, when the bus width N is 1 bit, the A / D conversion unit 230 supplies 1-pixel data to the digital data processing unit 310 by outputting the digital data 16 times bit by bit.

  In this case, the digital data processing unit 310 reads dummy data in 1-bit units in the above-described step S103. Then, in the above step S105, the process of comparing the pixel value to be specified in increments of 1 bit and comparing the amount of change of the offset value with the amount of change of the pixel data satisfies both the predetermined amounts of change (for example, , Almost match). Thereby, the digital data processing unit 310 can specify the boundary position of the pixel data regardless of the bus width N.

  DESCRIPTION OF SYMBOLS 50 ... Image processing apparatus, 100 ... Image sensor, 200 ... A / D converter, 210 ... Offset part, 220 ... Amplification part, 230 ... A / D conversion part, 240. .. Offset register, 300... Control board, 310... Digital data processing unit, 320... Clock output unit, 330.

Claims (5)

An image processing apparatus,
A / D conversion means for converting input analog pixel data into digital pixel data and outputting the digital pixel data;
Offset adjusting means for matching a voltage range effective as a signal of analog pixel data supplied from an image sensor with an input range of the A / D conversion means;
Sampling adjustment means for adjusting the sampling position of the digital pixel data output from the A / D conversion means,
The offset adjusting means includes
Change the offset value,
The sampling adjustment means includes
Adjusting the sampling position of the digital pixel data output from the A / D conversion means based on the amount of change of the digital pixel data;
An image processing apparatus. The image processing apparatus according to claim 1,
The sampling adjustment means includes
Adjusting the sampling position based on the relationship between the change amount of the offset value and the change amount of the digital pixel data;
An image processing apparatus. The image processing apparatus according to claim 1, wherein:
The sampling adjustment means includes
The digital pixel data output from the A / D conversion means is delimited by a predetermined bit width,
When there is a predetermined relationship between the amount of change in the offset value and the amount of change in the digital pixel data, the delimiter position of the data having the predetermined bit width is used as a sampling position serving as a sampling reference for the digital pixel data. Identify,
An image processing apparatus. A sampling position adjusting method for adjusting a sampling position of the digital pixel data output from an A / D converter that converts analog pixel data into digital pixel data,
A first step of adjusting the offset value to change the digital pixel data output from the A / D converter;
Performing a second step of adjusting a sampling position of the digital pixel data output from the A / D conversion device based on a change amount of the digital pixel data;
A sampling position adjustment method characterized by the above. An A / D converter,
A / D conversion means for converting input analog pixel data into digital pixel data and outputting the digital pixel data;
Offset adjusting means for matching a voltage range effective as a signal of analog pixel data supplied from an image sensor with an input range of the A / D conversion means,
The offset adjusting means includes
In the process of determining the sampling position of the digital pixel data, the offset value is adjusted to change the digital pixel data output from the A / D conversion means.
An A / D converter characterized by the above.

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