JP2005176187A - Scanning device control signal generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a scanning device control signal generating circuit capable of outputting, at an arbitrary pattern, a plurality of control signals for a scanning device and control signals of a sampling and A/D converting means connected with the scanning device, and further capable of controlling mounted devices with no distinction and furthermore capable of correcting timing deviance of scanned image data attributable to a physical layout of a device mounting since scanning device control signals except transfer clock signals of the scanning device can be arbitrarily delayed. <P>SOLUTION: The scanning device control circuit comprises a horizontal synchronizing means, an original clock frequency demultiplying means, a register means for storing arbitrary waveform patterns, a shift register for outputting arbitrary waveforms, a signal generating means for generating control signals that control the shift register synchronized with the horizontal synchronizing means and the original clock frequency demultiplying means, and a delay means for delaying an output from the shift register by a specified amount of the original clock frequency. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a reading device control signal generation circuit suitable for controlling a reading device used for facsimile and digital copying, which reads a document image and converts it into digital image data, and in particular, arbitrarily selects a reading device control signal pattern and timing. The present invention relates to a read device control signal generation circuit that can be generated.

  FIG. 3 is a block diagram showing a conventional image processing system. In this apparatus, a CCD (3-1) is used as an image sensor. The CCD is a reading device that irradiates a document with irradiation light from a lamp and converts reflected light of the document into an electric quantity.

3-2 is a driver circuit for supplying a drive signal for driving the CCD,
3-3 is a programmable amplifier circuit for amplifying the output of the CCD to an appropriate level, 3-4 is a sample and hold circuit for extracting only the output of the original image from the output signal output for each pixel from the CCD, and 3- Reference numeral 5 denotes an A / D converter that converts the analog video signal after the sample hold into a digital signal. 3-3, 3-4, and 3-5 are currently integrated and embodied as an analog front end ASIC (3-7).

  The output timing of the CCD and analog front end control signals is controlled by a 3-6 reading block control circuit. In the reading block control circuit, each control signal is generated by a certain synchronizing clock, and the image signal read from the document is A / D converted and synchronized with a certain synchronizing clock (image clock) as N-bit digital data. Each pixel is sequentially sent to subsequent image processing blocks. The output timing of the CCD and analog front end control signals is as follows.

  Control signals to be input to the CCD include a shift gate signal, a transfer clock signal (first), a transfer clock signal (second), a reset gate signal, a clamp gate signal, and the like.

  When the above signals (cc_ph1, cc_ph2 shown in the figure are transfer clock signals (first and second), cc_rs is a reset gate signal, and cc_clmp is a clamp gate signal) are input to the CCD at the timing shown in FIG. The CCD outputs the reference level and the data level of the read pixel in synchronization with the transfer clock (first and second) (shown in FIG. 4).

  Examples of control signals input to the analog front end include an AD convert clock signal, a sample hold signal, and a clamp signal.

  With respect to the reference level from the CCD and the data level of the read pixel, the reference level is extracted by asserting the clamp signal in synchronization with the output timing, and the signal level is obtained by asserting the sample hold signal. Extraction is performed, and the extracted signal level is converted from analog to digital by an AD conversion clock.

  The converted data is output from the analog front end in synchronization with the AD conversion clock and transferred to the subsequent processing block.

Conventionally, these CCD and analog front end control signal generation circuits 3-6 are designed and implemented according to the specifications of each CCD and analog front end.
Japanese Patent Application Laid-Open No. 11-177783

  In the conventional example described above, the output timing of the control signals of the CCD and the analog front end is controlled by the reading block control circuit as described above, and each control signal is generated by a certain synchronizing clock in the reading block control circuit and read from the original. The image signals thus obtained are A / D converted and synchronized with a certain synchronizing clock (image clock) as N-bit digital data, and sequentially sent out to the subsequent image processing blocks for each pixel.

  In recent years, various types of CCD devices and analog front-end devices have been developed with higher resolution and higher speed of image reading.

  In these devices, the basic control is the same, but the control timing is often different for each device in fine parts.

  When developing such a wide variety of CCD devices, digital copies, facsimiles, etc. equipped with analog front-end devices, it would be very efficient to design a control signal generation circuit according to each device specification. Is bad.

  In addition to the conventional simple reading device control as the resolution of the CCD increases, the pixel addition and decimation are performed analogly in the CCD device such as decimation reading and analog addition reading, and directly from the high resolution CCD device. A method for obtaining pixel values of resolution has been realized. This is very useful because it is not necessary to lower the resolution of the digitally converted pixel data at a later stage.

  To realize this, it is necessary to be able to control the transfer clock signal, reset gate signal, clamp gate signal, etc. of the CCD in a complex manner.

  For example, in order to obtain a 300 dpi resolution by performing pixel addition and pixel thinning out from a CCD device having a resolution of 1200 dpi, as shown in the timing diagram of FIG. 5, the transfer clock (cc_ph1, 2) and the final transfer stage By controlling the clock (cc_phL1, 2), reset gate signal (cc_rs), and clamp gate signal (cc_clmp), the odd-numbered pixels (or even-numbered pixels) are thinned out, and the pixels after the thinned-out processing are added every two pixels. By doing so, a 300 dpi pixel analog output (video_out) can be obtained directly from the CCD device.

  Of course, when controlling these thinning and addition readings, the control signal of the analog front end must also be synchronized with this CCD output.

  Also, when developing these CCD devices, digital copies, facsimiles, etc. with analog front-end devices, the timing of the control signals supplied to the devices may be shifted due to the physical layout of the devices, etc. May cause deterioration.

  For example, the scanner unit on which the CCD device is mounted and the main control unit on which the analog front-end device is mounted are physically separated, and the CCD control signal output from the main control unit is connected by a cable or the like. If there is a load capacity such as a cable, a delay of the control signal and a read data output are caused, and the image quality is deteriorated due to a timing shift with the analog front-end device.

  These delay factors were completely unpredictable by design, and developers had to make timing in the product development process.

  The present invention has been made to eliminate the above-mentioned conventional drawbacks, and can output a plurality of control signals for a reading device, samples connected thereto, and control signals for A / D conversion means in arbitrary patterns. It is possible to control regardless of the mounted device, and it is possible to control analog pixel decimation, pixel addition, etc. Reading device control signals other than the reading device control clock signal are set in the register for the reading device control clock. It is an object to construct a reading device control signal generation circuit that corrects a timing shift caused by a physical layout of a device mounting by arbitrarily delaying by several original clocks.

  In the present invention, an SH signal generating means for generating a horizontal synchronizing signal (line reset signal) to be supplied to the reading device, a clock dividing means for dividing the original clock and obtaining a 1 / N divided output clock , Synchronized with the divided reference clock output from the clock dividing means, and synchronized with the horizontal synchronizing signal generated by the SH signal generating means, and within a control signal output cycle set in the register, Having a plurality of pattern signal output means for outputting an arbitrary output pattern set in the register, a plurality of control signals for the reading device and samples connected thereto, and a control signal for the A / D conversion means for an arbitrary pattern Can be output regardless of the mounted device, and analog pixel thinning, pixel addition, etc. can be controlled. To.

  In addition, delay means for delaying the output signals of the plurality of pattern signal output means by the number of original clocks set in the register is provided, and reading device control signals other than the reading device control clock signal are used as the reading device control clock. On the other hand, it is possible to arbitrarily delay by the number of source clocks corresponding to the number of register settings, and to correct timing deviation caused by the physical layout of the device mounting.

  In addition, the arbitrary output pattern length is defined by the bit length of the register to be set, but in order to control the CCD at a later timing, the reading output within the control signal output cycle set in the register The device control clock can select a mode that outputs an arbitrary output pattern set in the register and a mode that toggles in the signal output cycle of a specific bit set in the register. It can be supported.

  In the present invention, an SH signal generating means for generating a horizontal synchronizing signal (line reset signal) to be supplied to the reading device, a clock dividing means for dividing the original clock and obtaining a 1 / N divided output clock , Synchronized with the divided reference clock output from the clock dividing means, and synchronized with the horizontal synchronizing signal generated by the SH signal generating means, and within a control signal output cycle set in the register, Having a plurality of pattern signal output means for outputting an arbitrary output pattern set in the register, a plurality of control signals for the reading device and samples connected thereto, and a control signal for the A / D conversion means for an arbitrary pattern Can be output regardless of the mounted device, and analog pixel thinning, pixel addition, etc. can be controlled. It made.

  In addition, delay means for delaying the output signals of the plurality of pattern signal output means by the number of original clocks set in the register is provided, and reading device control signals other than the reading device control clock signal are used as the reading device control clock. On the other hand, it is possible to arbitrarily delay by the number of source clocks corresponding to the number of register settings, and to correct timing deviation caused by the physical layout of the device mounting.

  An arbitrary output pattern length is defined by the bit length of the register to be set, but a reading device that is output within the control signal output cycle set in the register in order to control the CCD at a later timing The control clock can select a mode that outputs an arbitrary output pattern set in the register and a mode that toggles the signal output cycle of a specific bit set in the register. It becomes possible.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an example of a reading device control signal generation circuit according to the present invention. Reference numeral 001 denotes an SH generator that generates a horizontal synchronization signal. The SH generator 001 generates a horizontal synchronization signal (internal_SH) that defines the timing of horizontal synchronization. A timing generator 002 generates a load signal for loading a register value into a plurality of shift register groups 4 to be described later and a shift clock (ps_lclk) for shifting the shift register.

  As shown in the timing diagram of FIG. 2-1, the shift clock (ps_lclk) is generated by a frequency divider with a built-in timing generator that divides the original oscillation (lclk2x), and the division ratio is determined by the register pre_scale_lclk2x. The

  As shown in FIG. 2A, when pre_scale_lclk2x is set to divide by 4, ps_lclk becomes 48 MHz with respect to the original oscillation of 192 MHz, and the shift register operates in synchronization with ps_lclk.

  003 is a register group for arbitrarily generating each waveform.

  Each register group holds an output pattern of each output control signal.

  In this embodiment, the register group has a bit length of 32 bits, and patterns for 32 periods of ps_lclk can be generated.

  On the other hand, the operation of loading data from each register (* _cnt) of the register group to the shift register is set by the register vclk_interval in the timing generator, and when the value of the counter counted by ps_lclk becomes vclk_interval, the load signal to each shift register Is asserted.

  As a result, the output signal repeats output of the value of the register loaded in the cycle of vclk_interval in synchronization with ps_lclk.

  004 is a shift register group that is loaded with a cycle of vclk_interval from the register group 003 and outputs a shift in synchronization with ps_lclk.

An example of data output from the shift register group is shown in FIG.
Below each output waveform is the value of each register. In this figure, since vclk_interval = 24, the output of the register value is repeated at a cycle of 24 × ps_lclk.

  The timing generator 002 receives a horizontal synchronization signal (internal_SH) and performs phase alignment of the outputs of the shift registers in synchronization with the horizontal synchronization signal.

  For example, when a horizontal synchronization signal (internal_SH) is input from the SH generator 001, the timing generator 002 starts operation in synchronization with this and the load signal to each shift register is asserted.

  The load signal is output at a cycle of vclk_interval, and predetermined stored data from each register group is periodically loaded into the shift register group.

  On the other hand, ps_lclk is input to the shift register group as a shift clock, and the loaded data is shifted out in synchronization with this clock.

  Looking at the output of the cc_ph1 and cc_phL1 signals, the value of the register is “111111111111000000000”. By loading this into the shift register and outputting it in synchronization with ps_lclk, ps_lclk × 12 as shown in FIG. A waveform that is repeated with a period of “1” ps_lclk × 12 periods of “0” is output.

  The pattern data set for other output signals is as follows.

  Each output signal repeatedly outputs a pattern of ps_lclk × 24 periods.

  005 is a delay logic for delaying the output from the shift register by the designated number of clocks of the original oscillation.

  The operation of the delay logic 005 will be described with reference to FIG.

  2-4 shows the delay setting operation of the cc_rs signal. In this embodiment, 2 is set in the delay logic register ccrs_delay, and the delay is set for two clocks of lclk2x, and the signal output from the shift register is Thus, a signal delayed by 2 × lclk2x is output.

  For example, the scanner unit on which the CCD device is mounted and the main control unit on which the analog front-end device is mounted are physically separated, and the CCD control signal output from the main control unit is connected by a cable or the like. If there is a load capacity such as a cable, a delay of the control signal and a read data output delay occur, and the data from the CCD is delayed from the assumed output timing.

  Therefore, if the analog front end control signal is asserted at a normal timing, the CCD output is sampled at a timing shifted by the delay, and an accurate CCD output cannot be obtained.

  Therefore, in such a case, the delay logic controls the sampling signal (af_vclpmp, af_vsmp) input to the analog front end so as to sample the CCD output at a predetermined timing and control so as to obtain an accurate CCD output.

  For the transfer clock input to the CCD, the ccph_mode register is provided in the timing generator, and the transfer clock (cc_ph1, cc_ph2, cc_phL1, cc_phL2) output within the control signal output cycle (vclk_interval) as described above is stored in the register. It is possible to select a mode for outputting an arbitrary output pattern set to 1 (hereinafter referred to as a pattern mode) and a mode for causing a value set in a register to perform a toggle operation in a control signal output cycle (hereinafter referred to as a toggle mode).

  In the operation in the pattern mode, the transfer clock pattern control can only be controlled to be less than or equal to the bit length of the shift register as described above, and transfer clock control with a longer cycle is impossible.

  Therefore, when the transfer clock is controlled with a longer period, ccph_mode is set to toggle mode, and control is performed so that ‘0’ and ‘1’ toggle in the control signal output period (vclk_interval).

  The operation is shown in FIG.

  When ccph_mode is set in the toggle mode, when the horizontal synchronization signal (internal_SH) is input from the SH generator 001, the timing generator 002 starts the operation in synchronization with this, and the timing generator 002 shifts the shift register ( The value of the 0th bit set in the register is loaded into all the shift register bits, not the value of the register (003-1, 003-2) with respect to (004-1, 004-2).

  Therefore, in the first control signal output cycle (vclk_interval), the value set in the 0 bit of each register is continuously output (waveforms cc_ph1, cc_phL1 in FIG. 2-3).

  In the next control signal output cycle (vclk_interval), the shift register (004-1, 004-2) related to the transfer clock is set to the register instead of the value of the register (003-1, 003-2). Negative logic data of the 0th bit value is loaded to all shift register bits.

  Therefore, in the next control signal output cycle (vclk_interval), the negative logic value set in the 0 bit of each register is continuously output.

  By controlling in this way, it is possible to extend the cycle of the transfer clock to the cycle of vclk_interval × 2 in the toggle mode, and it is possible to control a slower reading device.

The figure which shows 1st Example of this invention The figure which shows the internal operation | movement waveform of 1st Example of this invention. The figure which shows the internal operation | movement waveform of 1st Example of this invention. The figure which shows the internal operation | movement waveform of 1st Example of this invention. The figure which shows the internal operation | movement waveform of 1st Example of this invention. Diagram showing conventional reading device control The figure which shows the control waveform in the conventional reading device control The figure which shows the control waveform of thinning addition reading with CCD

Explanation of symbols

001 SH generator 002 Timing generator 003 Register group 004 Shift register group 005 Delay logic

Claims (3)

  SH signal generating means for generating a horizontal synchronizing signal (line reset signal) to be supplied to the reading device, clock dividing means for dividing the original clock and obtaining a 1 / N divided output clock, and the clock dividing Is synchronized with the frequency-divided reference clock output from the means and synchronized with the horizontal synchronizing signal generated by the SH signal generating means, and is set in a plurality of registers within the control signal output period set in the register. A plurality of pattern signal output means for outputting an arbitrary output pattern, and a plurality of control signals for the reading device and analog sampling connected thereto, and control signals for the A / D conversion means can be output in an arbitrary pattern. Read device control signal generation circuit.   The output signal of the plurality of pattern signal output means has a delay means for delaying by the number of original clocks set in the register, and reading device control signals other than the transfer clock signal and A / D conversion clock signal of the reading device are 2. The read device control signal generation circuit according to claim 1, wherein the read device control signal generation circuit can be arbitrarily delayed by the number of source clocks set in the register.   The transfer clock signal of the reading device that is output within the control signal output period set in the register controls the mode in which an arbitrary output pattern set in the register is output, and the value of a specific bit set in the register The reading device control signal generation circuit according to claim 1, wherein a mode for performing a toggle operation in a signal output cycle can be selected.

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