JP5163162B2 - Data transfer device and electronic camera - Google Patents

Description

The present invention relates to a data transfer device, and an electronic camera.

  In recent years, with an increase in the number of pixels of an image sensor, there has been a demand for speeding up digital data transfer. In the design of conventional electronic equipment for the purpose of high-speed transfer, impedance control of a transmission path, selection of materials such as equal-length wiring or a printed circuit board, etc. are performed, and then a signal waveform is simulated.

However, when the transfer rate is in the order of gigahertz, there are limits to measures such as equal-length wiring alone, and stable high-speed transmission is difficult due to the influence of jitter (fluctuations in delay time of data signals). Thus, for example, cited document 1 and cited document 2 disclose a data transfer device that adjusts variation due to delay of each data signal caused by transfer by using a clock signal as a reference signal in parallel data transfer. ing.
JP 2004-171254 A Japanese Patent Laid-Open No. 11-112383

  However, in the cited document 1 as the prior art, since the test data signal for adjustment continues to be output until the adjustment of the delay amount is completed, the data transfer cannot be performed during that time and it has to wait.

  Further, in the cited document 2, there is a problem that the circuit to be mounted becomes complicated and large in order to calculate the optimum delay amount by comparing the test data before and after the transfer in adjusting the delay amount. there were.

  SUMMARY OF THE INVENTION In view of the above-described problems of the prior art, an object of the present invention is to provide a technique capable of adjusting a delay of a data signal with respect to a clock signal in a short time.

The data transfer apparatus according to claim 1, wherein a clock signal is input and a data signal is input, and the value of the data signal is captured in synchronization with either the rising or falling timing of the clock signal. A delay control unit having a storage unit that stores a predetermined initial delay amount as a delay amount for delaying the phase of the data signal input to the acquisition unit, and the initial delay amount A delay unit that delays the phase of the data signal input to the acquisition unit based on a final delay amount, and the delay control unit calculates a value of the data signal acquired by the acquisition unit. A determination unit for determining, and an increase unit for increasing the final delay amount based on a determination result by the determination unit, and the data signal is input to the capturing unit following the test data signal. If the test data signal is input to the capture unit, the first process, the second process, the third process, and the fourth process are controlled in order, and the first process is performed as the first process. When the determination unit determines that the value of the test data signal captured by the capture unit is not 0, the increase unit determines the value of the test data signal captured by the capture unit. When the determination unit determines that the value of the test data signal acquired by the acquisition unit is 0, the final delay amount is increased until the determination unit determines that 0 is 0. When the determination unit determines that the value of the test data signal acquired by the acquisition unit is not 1 as the second processing, the increase unit The test taken by the take-in part The final delay amount is increased until the determination unit determines that the value of the data signal is 1, and the determination unit determines that the value of the test data signal acquired by the acquisition unit is 1. When the determination is made, the final delay amount is stored as a first delay amount and the second process is terminated. As the third process, the value of the test data signal taken in by the take-in unit is 0. Otherwise, the increase unit determines the final delay amount until the determination unit determines that the value of the test data signal captured by the capture unit is 0. When the determination unit determines that the value of the test data signal acquired by the acquisition unit is 0, the final delay amount is stored as a second delay amount and the third process is performed. To exit As a fourth process, based on the first delay amount and the second delay amount, a third delay amount for delaying the phase of the main data signal that is input to the capturing unit following the test data signal is determined. And when the delay unit is able to calculate the third delay amount within a predetermined time, based on the third delay amount, delays the phase of the main data signal captured by the capture unit, When the third delay amount cannot be calculated within the predetermined time, the phase of the main data signal taken into the take-in unit is delayed based on the initial delay amount.

The data transfer device according to claim 2 is the data transfer device according to claim 1, wherein the third delay amount is expressed by the following equation (the second delay amount−the first delay amount) / 2 + the first delay. It is calculated by quantity.

An imaging apparatus according to a third aspect includes the data transfer apparatus according to the first or second aspect, and an imaging unit that captures an image of a subject and outputs an image data signal as the main data signal. Outputs the test data signal having a data amount output during the predetermined time, and outputs the image data signal following the test data signal.

According to a fourth aspect of the present invention, in the electronic camera according to the third aspect, the data amount of the test data signal is determined according to the resolution of the image.

According to a fifth aspect of the present invention, in the electronic camera according to the third aspect, the data amount of the test data signal is determined according to a photographing condition.

  According to the present invention, the delay adjustment of the data signal with respect to the clock signal can be performed in a short time.

<< First Embodiment >>
FIG. 1 is a schematic diagram illustrating a configuration example of a data transfer apparatus 100 according to the first embodiment of the present invention. FIG. 1 shows a configuration example when the imaging unit 10 of the electronic camera is a transmission unit and the signal processing circuit 13 of the electronic camera is a reception unit.

  The imaging unit 10 of the first embodiment includes an imaging element 11 having a light receiving surface in which a plurality of light receiving elements are two-dimensionally arranged, and an A / D conversion circuit (not shown), and an imaging optical system (not shown). The image signal of the subject image formed on the light receiving surface is output as digital image data. The imaging unit 10 further includes a test data adding unit 12 that adds test data for adjusting the delay amount of each delay unit 14 to the head of the imaged image data.

  Here, the imaging unit 10 of the first embodiment includes one end of n data signal lines DATA0 to DATAn (n = 0, 1, 2,...) For outputting image signals in parallel and a reference signal. One end of a clock signal line CLK that outputs a clock signal is connected. The other end of each signal line is connected to the signal processing circuit 13, and in the data transfer between the imaging unit 10 and the signal processing circuit 13, the image data is transferred by n channels in a parallel manner.

  The signal processing circuit 13 is a preprocess circuit that performs various types of image processing on the digital image signal input from the imaging unit 10. The signal processing circuit 13 includes a set of delay unit 14, capture unit 15, and delay control unit 16 for each of the data signal lines DATA 0 to DATAn, and further includes an image processing unit 17 and a storage unit 18. The delay unit 14 and the capture unit 15 are each connected to the delay control unit 16. Each capturing unit 15 is connected to an image processing unit 17, and each delay control unit 16 is connected to a storage unit 18. The image processing unit 17 has a circuit configuration that performs various types of image processing (defective pixel correction, color interpolation, gradation correction, white balance adjustment, edge enhancement, etc.) on a digital image signal.

  The delay unit 14 is a circuit that controls the delay amount of the data signals of the data signal lines DATA0 to DATAn. FIG. 2 is a schematic diagram illustrating a configuration example of the delay unit 14. The delay unit 14 includes a plurality of delay elements 30 (inverters and the like) connected in series in a plurality of stages, and a plurality of paths 31 and paths 31 connected to the output of each delay element 30 in accordance with an instruction from the delay control unit 16. It consists of a selector 32 to select. The data signal lines DATA0 to DATAn are output to the capturing unit 15 with the delay amount of the data signal output from each delay circuit being controlled according to the path 31 selected by the selector 32. The number of delay stages of the delay unit 14 is designed to correspond to several times the data transfer period.

  The capturing unit 15 is connected to the clock signal line CLK, and captures the value indicated by the data signal in synchronization with the rising or falling timing of the clock signal. Then, the capture unit 15 outputs the value indicated by the data signal to the delay control unit 16 and the image processing unit 17. Note that the capturing unit 15 in the operation example described later captures the value of the data signal at the rising timing of the clock signal.

  The delay control unit 16 is a processor that controls the pair of delay units 14 and the capture unit 15. FIG. 3 is a schematic diagram illustrating a configuration example of the delay control unit 16 in the first embodiment. The delay control unit 16 determines whether or not the delay amounts of the data signal line DATA0 and the clock signal line CLK match based on the output pattern of the capturing unit 15 based on the test data transferred before the image data. 35, a delay count-up circuit 36 that increases the delay amount in the delay unit 14 based on the determination of the determination unit 35, a holding unit 37 that reads and holds the initial value of the delay amount held in the storage unit 18, and any one of them The selector 38 selects the delay amount. Thereby, the delay control unit 16 determines the delay amount of the delay unit 14 based on the output of the capturing unit 15. The holding unit 37 may be a memory provided in the delay control unit 16 or a memory such as an external RAM.

  The storage unit 18 is configured by a storage medium such as a register. In the storage unit 18, data of the delay amount (the number of delay stages of the delay element 30) of the delay unit 14 read by the holding unit 37 of the delay control unit 16 obtained in advance in a manufacturing process or the like is recorded.

  Next, a delay adjustment work procedure in the data transfer apparatus 100 according to the first embodiment will be described. Note that the configurations of the delay unit 14, the capture unit 15, and the delay control unit 16 of the data signal lines DATA0 to DATAn are the same. Therefore, in the following example, only the case of the data signal line DATA0 will be described for the sake of simplicity. However, the same processing is actually performed in parallel on the other data signal lines DATA1 to DATAn. This process is executed at a timing when image data captured by the imaging unit 10 is transferred. In the first embodiment, before the data transfer, the test data adding unit 12 adjusts the delay of the delay unit 14 in each of the data signal lines DATA0 to DATAn at the head of the image data captured by the image sensor 11. Test data is added (see FIG. 5). Note that the test data in the first embodiment includes a binary data string in which “0” and “1” are repeated in the same cycle as the clock signal. The data amount of the test data can be arbitrarily determined. In the first embodiment, the data signal lines DATA0 to DATAn are transferred for 1 second.

In the following, the case where the delay adjustment operation is completed within the test data transfer time and the case where it is not completed will be described separately.
(When delay adjustment is completed within the test data transfer time)
This will be described with reference to the flowchart of FIG.

  Step S <b> 101: The delay control unit 16 initializes the delay amount of the delay unit 14, and reads the initial value of the delay amount of the delay unit 14 from the storage unit 18 and holds it in the holding unit 37. The delay control unit 16 instructs the output start of the image data to which the test data is added in the imaging unit 10 described above. Thereby, test data is output from the imaging unit 10 to the data signal lines DATA0 to DATAn in synchronization with the clock signal. Then, the test data of the data signal line DATA0 is input to the capturing unit 15 via the delay unit 14.

  Step S102: The delay control unit 16 causes the determination unit 35 to determine whether or not the value input from the capture unit 15 at the rising timing of the clock signal is “0”. If it is “0”, the process proceeds to step S104 (YES side). On the other hand, if it is not “0”, the process proceeds to step S103 (NO side).

  Step S103: The delay control unit 16 issues a command to increase the delay amount of the delay unit 14 (the number of delay stages of the delay circuit) by “1” to the delay count-up circuit 36 based on the determination unit 35 to delay the phase. Thereafter, the delay control unit 16 returns to Step S102. The loop from the NO side to step S103 in step S102 corresponds to the operation of temporarily shifting the data signal capture position to the value “0” in order to search for the rising position of the signal waveform in the test data. .

  Step S104: The delay control unit 16 causes the determination unit 35 to determine whether or not the value input from the capture unit 15 at the rising timing of the clock signal is “1”. If “1”, the process proceeds to step S106 (YES side). On the other hand, if it is not “1”, the process proceeds to step S105 (NO side).

  Step S105: The delay control unit 16 instructs the delay count-up circuit 36 to increase the delay amount of the delay unit 14 by “1” and delay the phase. Thereafter, the delay control unit 16 returns to Step S104. Note that the loop from the NO side to step S105 in step S104 corresponds to the operation of shifting the data signal capture position to the falling position of the signal waveform in the test data.

  Step S106: The delay control unit 16 temporarily holds the current delay amount of the delay unit 14 in the holding unit 37 as “delay_start”. Note that the delay amount “delay_start” held in step S106 corresponds to the falling position of the signal waveform in the test data (see FIG. 6).

  Step S107: The delay control unit 16 causes the determination unit 35 to determine whether or not the value input from the capture unit 15 at the rising timing of the clock signal is “0”. If it is “0”, the process proceeds to step S109 (YES side). On the other hand, if it is not “0”, the process proceeds to step S108 (NO side).

  Step S108: The delay control unit 16 instructs the delay count-up circuit 36 to increase the delay amount of the delay unit 14 by “1” and delay the phase. Thereafter, the delay control unit 16 returns to Step S107. Note that the loop from the NO side to step S108 in step S107 corresponds to an operation of shifting the data signal capturing position to the rising position of the signal waveform in the test data.

  Step S109: The delay control unit 16 temporarily holds the current delay amount of the delay unit 14 in the holding unit 37 as “delay_end”. The delay amount “delay_end” recorded in step S109 corresponds to the rising position of the signal waveform in the test data (see FIG. 6). The delay control unit 16 causes the determination unit 35 to output a flag signal that informs the AND circuit 19 that the adjustment of the delay amount has been completed.

Step S110: The delay control unit 16 uses the delay amount “delay_start” acquired in step S106 and the delay amount “delay_end” acquired in step S109, to determine the delay amount (data signal) of the delay unit 14 during data communication. Determine the reference capture position). Specifically, the delay control unit 16 calculates the reference capture position of the data signal by the following equation (1).
Reference capture position = (delay_end−delay_start) / 2 + delay_start (1)
Step S111: The delay control unit 16 causes the delay count-up circuit 36 to output the number of delay stages of the delay element 30 corresponding to the reference capture position obtained in step S110, and transmits it to the delay unit 14 through the selector 38. At the same time, the delay control unit 16 updates the initial value data of the storage unit 18 and the initial value of the holding unit 37 by using the newly obtained delay stage number of the delay element 30 as a new initial value of the delay unit 14 to adjust the delay. Finish the work.

The operations from step S101 to step S111 are also performed in parallel for the delay adjustment of the delay units 14 of the other data signal lines DATA1 to DATAn. When the delay adjustment of all the delay units 14 is completed and the AND circuit 19 receives a flag signal indicating completion of delay adjustment from the determination unit 35 of the delay control unit 16, the AND circuit 19 outputs a delay adjustment completion signal. The delay adjustment completion signal is input to the selector 38 of each delay control unit 16, and the delay amount of each delay unit 14 is fixed while the image data is being transferred. Thereafter, the image data transferred to the data signal lines DATA0 to DATAn in synchronization with the clock signal is acquired by the capturing unit 15 via the delay unit 14 adjusted to an appropriate delay amount and sent to the image processing unit 17. Is output.
(When delay adjustment is not completed within the test data transfer time)
Next, a procedure when the delay adjustment is not completed within the test data transfer time will be described.

  Also in this case, while the test data is transferred to the data signal lines DATA0 to DATAn, the operations from Step S101 to Step S111 in FIG. 4 are performed in parallel. However, when the transfer of test data is completed before any of the operations up to step S111 is completed on any of the data signal lines DATA0 to DATAn, the determination unit 35 of the data signal line whose delay adjustment has not ended is performed. Then, a flag signal indicating the end of the test data is output. The delay control unit 16 causes the selector 38 to output the initial value of the number of delay stages of the delay element 30 held in the holding unit 37 as the delay amount of the delay unit 14, and at the same time, causes the determination unit 35 to the AND circuit 19. A flag signal for which delay adjustment has been completed is output.

  When the AND circuit 19 receives a flag signal indicating that the delay adjustment is completed from all the delay control units 16, the AND circuit 19 sends a delay adjustment completion signal in the same manner as when the delay adjustment is completed within the test data transfer time. Output. The delay adjustment completion signal is input to the selector 38 of each delay control unit 16, and the delay amount of the delay unit 14 is fixed while the image data is being transferred. Thereafter, the image data transferred to the data signal lines DATA0 to DATAn in synchronization with the clock signal is acquired by the capturing unit 15 via the delay unit 14 adjusted to an appropriate delay amount and sent to the image processing unit 17. Is output.

  As described above, in the first embodiment, the delay adjustment of each delay unit 14 is performed in parallel within the test data transfer time, so that the adjustment is completed in a short time, and the release time is limited. Data transfer is possible without losing image data.

  Further, by performing the delay adjustment of the delay unit 14 in parallel for each of the data signal lines DATA0 to DATAn, the parallel data transfer apparatus 100 can avoid the isometric wiring design, and at the time of designing, the elements and wirings can be avoided. Layout flexibility is greatly improved.

  Furthermore, in the first embodiment, when the delay adjustment is completed within the test data transfer time, the reference capture position obtained in step S110 is determined by the actually measured value of the test data. Errors due to changes are also absorbed, and the reliability of the data transfer apparatus 100 can be improved.

Further, when the delay adjustment is not completed within the test data transfer time, the initial value of the delay amount stored in advance in the storage unit 18 is used, so that an appropriate delay amount can be used without using an inaccurate delay amount during the adjustment. The delay unit 14 can be adjusted for delay.
<< Second Embodiment >>
FIG. 7 is a configuration diagram of a data transfer apparatus 200 according to the second embodiment of the present invention.

  The data transfer apparatus 200 has three data signal lines (DATA0 to DATA2), and the image data, the vertical synchronization signal, and the horizontal synchronization signal of the image captured by the image sensor 11 are parallelized through the three channels. Forward by. Note that the components of the data transfer apparatus 200 according to the second embodiment are the same as those of the data transfer apparatus 100 according to the first embodiment of FIG. The detailed description is omitted.

  Therefore, the data transfer apparatus 200 according to the second embodiment will be described with reference to the flowchart of FIG. However, the procedure of delay adjustment in the data transfer apparatus 200 is the same as that in the first embodiment, and will be described only for the data signal line DATA0. However, the same processing is actually applied to the other data signal lines DATA1 and DATA2. Are performed in parallel. This process is executed at a timing when image data captured by the imaging unit 10 is transferred. Before the data transfer, the test data adding unit 12 adds test data for adjusting the delay of the delay unit 14 in each of the data signal lines DATA0 to DATA2 to the head of the image data picked up by the image pickup device 11. Also in the second embodiment, the test data is a binary data string in which “0” and “1” are repeated in the same cycle as the clock signal, and the amount of test data to be added is as follows. The data signal lines DATA0 to DATA2 are assumed to be transferred for 1 second.

As in the first embodiment, the case where the delay adjustment operation is completed within the test data transfer time and the case where the operation is not completed will be described separately.
(When delay adjustment is completed within the test data transfer time)
Step S <b> 101: The delay control unit 16 initializes the delay amount of the delay unit 14, and reads the initial value of the delay amount of the delay unit 14 from the storage unit 18 and holds it in the holding unit 37. The delay control unit 16 instructs the output start of the image data to which the test data is added in the imaging unit 10 described above. Accordingly, test data is output from the imaging unit 10 to the data signal lines DATA0 to DATA2 in synchronization with the clock signal. Then, the test data of the data signal line DATA0 is input to the capturing unit 15 via the delay unit 14.

  Step S102: The delay control unit 16 causes the determination unit 35 to determine whether or not the value input from the capture unit 15 at the rising timing of the clock signal is “0”. If it is “0”, the process proceeds to step S104 (YES side). On the other hand, if it is not “0”, the process proceeds to step S103 (NO side).

  Step S103: The delay control unit 16 issues a command to increase the delay amount of the delay unit 14 (the number of delay stages of the delay circuit) by “1” to the delay count-up circuit 36 based on the determination unit 35 to delay the phase. Thereafter, the delay control unit 16 returns to Step S102.

  Step S104: The delay control unit 16 causes the determination unit 35 to determine whether or not the value input from the capture unit 15 at the rising timing of the clock signal is “1”. If “1”, the process proceeds to step S106 (YES side). On the other hand, if it is not “1”, the process proceeds to step S105 (NO side).

  Step S105: The delay control unit 16 instructs the delay count-up circuit 36 to increase the delay amount of the delay unit 14 by “1” and delay the phase. Thereafter, the delay control unit 16 returns to Step S104.

  Step S106: The delay control unit 16 temporarily holds the current delay amount of the delay unit 14 in the holding unit 37 as “delay_start”.

  Step S107: The delay control unit 16 causes the determination unit 35 to determine whether or not the value input from the capture unit 15 at the rising timing of the clock signal is “0”. If it is “0”, the process proceeds to step S109 (YES side). On the other hand, if it is not “0”, the process proceeds to step S108 (NO side).

  Step S108: The delay control unit 16 instructs the delay count-up circuit 36 to increase the delay amount of the delay unit 14 by “1” and delay the phase. Thereafter, the delay control unit 16 returns to Step S107.

  Step S109: The delay control unit 16 temporarily holds the current delay amount of the delay unit 14 in the holding unit 37 as “delay_end”. The delay control unit 16 causes the determination unit 35 to output a flag signal that informs the AND circuit 19 that the adjustment of the delay amount has been completed.

  Step S110: The delay control unit 16 uses the delay amount “delay_start” acquired in step S106 and the delay amount “delay_end” acquired in step S109 and the equation (1) to delay the delay unit 14 during data communication. Determine the amount (reference capture position of the data signal).

  Step S111: The delay control unit 16 causes the delay count-up circuit 36 to output the number of delay stages of the delay element 30 corresponding to the reference capture position obtained in step S110, and transmits it to the delay unit 14 through the selector 38. At the same time, the delay control unit 16 updates the initial value data of the storage unit 18 and the initial value of the holding unit 37 by using the newly obtained delay stage number of the delay element 30 as a new initial value of the delay unit 14 to adjust the delay. Finish the work.

The operations from step S101 to step S111 are also performed in parallel for the delay adjustment of the delay units 14 of the other data signal lines DATA1 and DATA2. When the delay adjustment of all the delay units 14 is completed and the AND circuit 19 receives a flag signal indicating completion of delay adjustment from the determination unit 35 of the delay control unit 16, the AND circuit 19 outputs a delay adjustment completion signal. The delay adjustment completion signal is input to the selector 38 of each delay control unit 16, and the delay amount of each delay unit 14 is fixed while the image data is being transferred. Thereafter, the image data, the vertical synchronization signal, and the horizontal synchronization signal transferred to each of the data signal lines DATA0 to DATA2 in synchronization with the clock signal are taken in via the delay unit 14 adjusted to an appropriate delay amount. Obtained by the unit 15 and output to the image processing unit 17.
(When delay adjustment is not completed within the test data transfer time)
Next, a procedure when the delay adjustment is not completed within the test data transfer time will be described.

  Also in this case, while the test data is transferred to the data signal lines DATA0 to DATA2, the operations from step S101 to step S111 in FIG. 4 are performed in parallel. However, if the transfer of the test data is completed before any of the operations up to step S111 is completed on any of the data signal lines DATA0 to DATA2, the determination unit 35 of the data signal line whose delay adjustment has not been completed is performed. Then, a flag signal indicating the end of the test data is output. The delay control unit 16 causes the selector 38 to output the initial value of the number of delay stages of the delay element 30 held in the holding unit 37 as the delay amount of the delay unit 14. At the same time, the delay control unit 16 causes the determination unit 35 to output a flag signal whose delay adjustment has been completed to the AND circuit 19.

  When the AND circuit 19 receives a flag signal indicating that the delay adjustment is completed from all the delay control units 16, the AND circuit 19 sends a delay adjustment completion signal in the same manner as when the delay adjustment is completed within the test data transfer time. Output. The delay adjustment completion signal is input to the selector 38 of each delay control unit 16, and the delay amount of the delay unit 14 is fixed while the image data is being transferred. Thereafter, the image data, the vertical synchronization signal, and the horizontal synchronization signal transferred to each of the data signal lines DATA0 to DATA2 in synchronization with the clock signal are taken in via the delay unit 14 adjusted to an appropriate delay amount. Obtained by the unit 15 and output to the image processing unit 17.

  As described above, in the second embodiment, the test data is added before the image data is transferred, and the delay adjustment of the delay unit 14 of each of the data signal lines DATA0 to DATA2 is performed. Image data can be transferred at high speed without embedding codes of a vertical synchronization signal and a horizontal synchronization signal in data that has been used in data transfer.

  Furthermore, in the second embodiment, the delay adjustment of each delay unit 14 is performed in parallel within the test data transfer time, so that the adjustment is completed in a short time, and even under the condition that there is a restriction on the release time or the like. Data can be transferred without losing data.

  Further, by adjusting the delay of the delay unit 14 for each of the data signal lines DATA0 to DATA2, the parallel data transfer apparatus 200 can avoid the isometric wiring design, and the layout of elements and wiring can be freely set at the time of designing. The degree is greatly improved.

  Further, in the second embodiment, when the delay adjustment is completed within the test data transfer time, the reference capture position obtained in step S110 is determined by the actually measured value of the test data. Errors due to changes are also absorbed, and the reliability of the data transfer apparatus 200 can be further improved.

Further, when the delay adjustment is not completed within the test data transfer time, the initial value of the delay amount stored in advance in the storage unit 18 is used, so that an appropriate delay amount can be used without using an inaccurate delay amount during the adjustment. The delay unit 14 can be adjusted for delay.
<< Third Embodiment >>
FIG. 8 is a configuration diagram of a data transfer apparatus 300 according to the third embodiment of the present invention.

  The data transfer device 300 has four data signal lines (DATA0 to DATA3) and is connected to the pair of data signal lines DATA0 and DATA1 or the data signal lines DATA2 and DATA3, respectively, and the capture unit 15 is connected to one delay control unit 16a. The components of the data transfer device 300 according to the third embodiment are the same as those of the data transfer device 100 according to the first embodiment of FIG. The detailed description is omitted. However, the configuration of the delay control unit 16a is the same as the configuration in the first embodiment (FIG. 3) as shown in FIG. 9, but the output of the determination unit 35a to the AND circuit 19 is lost, and the selector 38a The output is made to the two delay units 14 connected. The AND circuit 19a outputs a signal to the delay control unit 16a based on the outputs from the two capturing units 15.

  A data transfer apparatus according to the third embodiment will be described with reference to the flowchart of FIG. However, the delay adjustment procedure in the data transfer apparatus according to the third embodiment is the same as that in the first embodiment, and will be described only for the pair of data signal lines DATA0 and DATA1. The same processing is performed in parallel for the pair of data signal lines DATA2 and DATA3. This process is executed at a timing when image data captured by the imaging unit 10 is transferred. Before the data transfer, the test data adding unit 12 adds test data for adjusting the delay of the delay unit 14 in each of the data signal lines DATA0 to DATA3 to the head of the image data captured by the image sensor 11. In the third embodiment, the test data is a binary data string in which “0” and “1” are repeated in the same cycle as the clock signal. However, the amount of test data to be added is the amount of data signal lines DATA0 to DATA3 transferred for 2 seconds.

As in the first embodiment, the case where the delay adjustment operation is completed within the test data transfer time and the case where the operation is not completed will be described separately.
(When delay adjustment is completed within the test data transfer time)
Step S201: The delay control unit 16a initializes the delay amounts of the two delay units 14, and reads and holds the initial values of the delay amounts of the delay units 14 from the storage unit 18 in the holding unit 37, respectively. The delay control unit 16a instructs the output start of the image data to which the test data is added in the imaging unit 10 described above. Test data is output from the imaging unit 10 to the data signal lines DATA0 to DATA3 in synchronization with the clock signal. The delay control unit 16a sets the delay unit 14 so that the output from the capturing unit 15 connected to the delay unit 14 of the data signal line DATA1 is fixed to “1”. As a result, the delay adjustment of the delay unit 14 of DATA0 is first performed using the test data and the clock signal input to the capturing unit 15 via the delay unit 14 of the data signal line DATA0.

  Step S202: The delay control unit 16a causes the determination unit 35a to determine whether or not the value input from the AND circuit 19a is “0” at the rising timing of the clock signal. If it is “0”, the process proceeds to step S204 (YES side). On the other hand, if it is not “0”, the process proceeds to step S203 (NO side).

  Step S203: The delay control unit 16a issues a command to delay the phase by increasing the delay amount of the delay unit 14 (the number of delay stages of the delay circuit) by “1” to the delay count-up circuit 36 based on the determination unit 35a. Thereafter, the delay control unit 16a returns to Step S202.

  Step S204: The delay control unit 16a causes the determination unit 35a to determine whether or not the value input from the AND circuit 19a is “1” at the rising timing of the clock signal. If “1”, the process proceeds to step S206 (YES side). On the other hand, if it is not “1”, the process proceeds to step S205 (NO side).

  Step S205: The delay control unit 16a instructs the delay count-up circuit 36 to increase the delay amount of the delay unit 14 by “1” and delay the phase. Thereafter, the delay control unit 16a returns to Step S204.

  Step S206: The delay control unit 16a temporarily holds the current delay amount of the delay unit 14 in the holding unit 37 as “delay_start”. Note that the delay amount “delay_start” held in step S206 corresponds to the rising position of the signal waveform in the test data (see FIG. 6).

  Step S207: The delay control unit 16a causes the determination unit 35a to determine whether or not the value input from the AND circuit 19a is “0” at the rising timing of the clock signal. If it is “0”, the process proceeds to step S209 (YES side). On the other hand, if it is not “0”, the process proceeds to step S208 (NO side).

  Step S208: The delay control unit 16a instructs the delay count-up circuit 36 to increase the delay amount of the delay unit 14 by “1” and delay the phase. Thereafter, the delay control unit 16a returns to Step S207.

  Step S209: The delay control unit 16a temporarily holds the current delay amount of the delay unit 14 in the holding unit 37 as “delay_end”. The delay amount “delay_end” recorded in step S209 corresponds to the falling position of the signal waveform in the test data (see FIG. 6).

  Step S210: The delay control unit 16a uses the delay amount “delay_start” acquired in step S206, the delay amount “delay_end” acquired in step S209, and Expression (1) to delay the delay unit 14 during data communication. Determine the amount (reference capture position of the data signal).

  Step S211: The delay control unit 16a retains the initial value data in the storage unit 18 as the new initial value of the delay unit 14 of the data signal line DATA0 with the number of delay stages of the delay element 30 corresponding to the reference capture position obtained in Step S210. The initial value of the unit 37 is updated.

  Step S212: The delay control unit 16a determines whether or not the delay adjustment of all the delay units 14 connected by the determination unit 35a has been completed. If completed, the process proceeds to step S213 (YES side). On the other hand, if not completed, the process proceeds to step S202 (NO side). It should be noted that when the process proceeds to step S202, the delay control unit 16a sets the output of the delay unit 14 so that the output from the capture unit 15 connected to the delay unit 14 of the data signal line DATA0 is fixed to “1”. Set up. The delay control unit 16a performs the operations from step S202 to step S212 on the delay unit 14 of the data signal line DATA1 to adjust the delay.

  Step S213: The delay control unit 16a outputs the number of delay stages of the delay element 30 of the delay unit 14 of the pair of data signal lines DATA0 and DATA1 obtained in a series of operations to each delay unit 14, and ends the operation.

For the delay adjustment of the delay unit 14 of the other pair of data signal lines DATA2 and DATA3, the operations from step S201 to step S213 are performed in parallel. Thereafter, the image data transferred to the data signal lines DATA0 to DATA3 in synchronization with the clock signal is acquired by the capturing unit 15 via the delay unit 14 adjusted to an appropriate delay amount and sent to the image processing unit 17. Is output.
(When delay adjustment is not completed within the test data transfer time)
Next, a procedure when the delay adjustment is not completed within the test data transfer time will be described.

  Also in this case, while the test data is being transferred to the data signal lines DATA0 to DATA3, each delay control unit 16a performs the operations from step S201 to step S213 in FIG. 10 in parallel. However, when the transfer of test data is completed before the delay adjustment to step S213 for the delay units 14 of all the data signal lines DATA0 to DATA3 is completed, the determination unit 35a displays a flag signal indicating the end of the test data. Is output. The delay control unit 16 a outputs and sets the initial value of the number of delay stages of the delay element 30 held in the holding unit 37 to the selector 38 a as the delay amount of each delay unit 14. Thereafter, the image data transferred in synchronization with the clock signal to the data signal lines DATA0 to DATA3 is acquired by the capturing unit 15 via the delay units 14 adjusted to an appropriate delay amount, and the image processing unit 17 Is output.

  As described above, in the third embodiment, a part of the delay control unit 16a that adjusts the delay of the delay unit 14 of the data signal lines DATA1 to DATA3 is shared, and the delay unit 14 of each of the data signal lines DATA0 to DATA3 is shared. By performing the delay adjustment, the circuit scale can be reduced while maintaining the accuracy of data transfer.

  Furthermore, in the third embodiment, when the delay adjustment is completed within the test data transfer time, the reference capture position obtained in step S210 is determined by the actual measurement value of the test data. Errors due to changes are also absorbed, and the reliability of the data transfer apparatus 300 can be further improved.

  Further, by adjusting the delay of the delay unit 14 for each of the data signal lines DATA0 to DATA3, the parallel data transfer apparatus 300 can avoid the isometric wiring design, and the layout of elements and wiring can be freely set at the time of designing. The degree is greatly improved.

Further, when the delay adjustment is not completed within the test data transfer time, the initial value of the delay amount stored in advance in the storage unit 18 is used, so that an appropriate delay amount can be used without using an inaccurate delay amount during the adjustment. The delay unit 14 can be adjusted for delay.
<Supplementary items of the embodiment>
In the first to third embodiments, the example of data transfer between the imaging unit 10 and the signal processing circuit 13 in the camera has been described. However, the data transfer apparatus according to the present invention is connected between other elements in the camera. It can also be applied to data transfer. For example, instead of the imaging unit 10, an analog front end (AFE) that receives image data from the imaging element 11 having the test data adding unit 12 may be used. The data transfer apparatus according to the present invention can also be applied to a digital processing circuit incorporated in another electronic device. Furthermore, the data transfer apparatus of the present invention can also be applied to wired data transfer between mutually independent electronic devices.

  In the first to third embodiments, the test data adding unit 12 directly adds test data to the head of image data, but the present invention is not limited to this. For example, the test data adding unit 12 may add data indicating an end code of the test data, a start code of the image data, or empty data between the test data and the image data.

  In the first to third embodiments, the image data transfer method is the parallel method. However, the data transfer device according to the present invention is also applicable to the serial method.

  In the first to third embodiments, the capturing unit 15 captures the value of the data signal at the rising timing of the clock signal. However, even if the capturing unit 15 captures the value of the data signal at the falling timing of the clock signal. good.

  In the first embodiment to the third embodiment, the number of delay elements 30 of the delay unit 14 is six, but the present invention is not limited to this. The number of delay elements 30 can be determined by the amount of delay of one delay element 30 and the size of the range in which the phase of test data with respect to the clock signal is delayed. For example, the size of the range for delaying the phase is preferably about 1.5 cycles of the clock signal.

  In the first to third embodiments, the delay control unit 16 (16 a) reads the initial value of the delay unit 14 that performs delay adjustment from the storage unit 18 and holds it in the holding unit 37, thereby creating a new delay. When the amount is obtained, the delay amount of the storage unit 18 is updated, but the present invention is not limited to this. For example, the delay amount of the delay unit 14 that adjusts the delay may be stored in the holding unit 37, and when a new delay amount is obtained, the delay amount of the holding unit 37 may only be updated. Thereby, the circuit scale can be further reduced.

  In the first embodiment to the third embodiment, the initial value of the delay amount for each delay unit 14 is stored in the storage unit 18 one by one, but the present invention is not limited to this. For example, the delay control unit 16 (16a) includes a temperature sensor, and the storage unit 18 stores a data table including a plurality of values for each temperature as an initial value of the delay amount for each delay unit 14, thereby the delay control unit. 16 (16a) may read or update the initial value of the delay amount of each delay unit 14 corresponding to the temperature such as the photographing situation measured by the temperature sensor from the data table of the storage unit 18.

  In the first embodiment or the second embodiment, the data amount of the test data added to the image data is the amount that each data signal line is transferred for one second. However, the present invention is not limited to this. . For example, it may be determined by the resolution of the image, shooting conditions, processing capability of the data transfer device, or the like.

  In the third embodiment, an example of a data transfer apparatus that performs parallel transfer using four channels has been described. However, the number of channels of the data transfer apparatus according to the present invention is not limited to this, and can naturally be applied to a data transfer apparatus that performs parallel transfer using a plurality of channels exceeding two channels or four channels.

  In the third embodiment, the delay unit 14 corresponding to two data signal lines is shared and controlled by one delay control unit 16a. However, the present invention is not limited to this. Three or more or all data signal lines may be shared and controlled by one delay control unit 16a. However, as the number of delay units 14 controlled by one delay control unit 16a increases, it takes time to complete the delay adjustment of all the delay units 14, and the amount of test data added to the image data also increases. It will increase. Therefore, it is preferable to determine the number of delay units 14 controlled by one delay control unit 16a according to the resolution of the image, shooting conditions, processing capability of the data transfer apparatus, and the like.

  In the third embodiment, the data amount of the test data added to the image data is the amount that each data signal line is transferred for 2 seconds. However, the present invention is not limited to this. For example, it is preferably determined by the resolution of the image, shooting conditions, the processing capability of the data transfer apparatus, the number of delay units 14 controlled by one delay control unit 16a, and the like.

  In the third embodiment, the delay adjustment of each delay unit 14 is performed using the AND circuit 19a, but the present invention is not limited to this. For example, the delay adjustment of each delay unit 14 may be performed using an OR circuit. However, in this case, the delay control unit 16a needs to set the delay unit 14 so that the output is fixed to “0” from the capturing unit 15 connected to the delay unit 14 that does not perform delay adjustment. There is.

  It should be noted that the present invention can be implemented in various other forms without departing from the spirit or main features thereof. Therefore, the above-described embodiment is merely an example in all respects and should not be interpreted in a limited manner. The present invention is defined by the claims, and the present invention is not limited to the text of the specification. Further, all modifications and changes belonging to the equivalent scope of the claims are within the scope of the present invention.

1 is a schematic diagram showing a configuration example of a data transfer apparatus 100 according to a first embodiment of the present invention. The schematic diagram which shows the structural example of the delay part 14 which concerns on the 1st Embodiment of this invention. Schematic diagram showing a configuration example of the delay control unit 16 according to the first embodiment of the present invention. The flowchart which shows the procedure of the delay adjustment of the delay part 14 which concerns on the 1st Embodiment of this invention. The figure which illustrates the state where the test data was added to the head of the image data by the test data adding unit 12 Timing chart showing a procedure of delay adjustment of the delay unit 14 according to the first embodiment of the present invention. Schematic diagram showing a configuration example of a data transfer apparatus 200 according to the second embodiment of the present invention Schematic diagram showing a configuration example of a data transfer apparatus 300 according to the third embodiment of the present invention. The schematic diagram which shows the structural example of the delay control part 16a which concerns on the 3rd Embodiment of this invention. The flowchart which shows the procedure of the delay adjustment of the delay part 14 which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

CLK clock signal line, DATA0 to DATAn data signal line, 10 imaging unit, 11 imaging element, 12 test data adding unit, 13 signal processing circuit, 14 delay unit, 15 capture unit, 16 delay control unit, 17 image processing unit, 18 storage unit, 19 AND circuit, 30 delay element, 31 path, 32, 38 selector, 35 determination unit, 36 delay count-up circuit, 37 holding unit, 100 data transfer device

Claims (5)

A data signal is input together with a clock signal, and a capturing unit that captures the value of the data signal in synchronization with either the rising edge or the falling edge of the clock signal;
A delay control unit having a storage unit that stores a predetermined initial delay amount as a delay amount for delaying the phase of the data signal input to the capture unit;
A delay unit that delays the phase of the data signal input to the capture unit based on a final delay amount including the initial delay amount;
The delay control unit
A determination unit for determining a value of the data signal captured by the capture unit;
Based on the determination result by the determination unit, further includes an increase unit that increases the final delay amount,
When this data signal is input to the capture unit following the test data signal, and the test data signal is input to the capture unit, the first process, the second process, the third process, 4 processes are executed in order,
As the first process,
When the determination unit determines that the value of the test data signal captured by the capture unit is not 0, the increase unit determines that the value of the test data signal captured by the capture unit is Increasing the final delay amount until it is determined by the determination unit to be 0,
When the determination unit determines that the value of the test data signal acquired by the acquisition unit is 0, the first process ends.
As the second process,
When the determination unit determines that the value of the test data signal captured by the capture unit is not 1, the increase unit determines that the value of the test data signal captured by the capture unit is Increasing the final delay amount until it is determined by the determination unit to be 1,
When the determination unit determines that the value of the test data signal acquired by the acquisition unit is 1, the final delay amount is stored as a first delay amount and the second process is terminated. ,
As the third process,
When the determination unit determines that the value of the test data signal captured by the capture unit is not 0, the increase unit determines that the value of the test data signal captured by the capture unit is Increasing the final delay amount until it is determined by the determination unit to be 0,
When the determination unit determines that the value of the test data signal acquired by the acquisition unit is 0, the final delay amount is stored as a second delay amount and the third process is terminated. ,
As the fourth process,
Based on the first delay amount and the second delay amount, calculate a third delay amount for delaying the phase of the main data signal input to the acquisition unit following the test data signal,
If the delay unit can calculate the third delay amount within a predetermined time, the delay unit delays the phase of the main data signal captured by the capture unit based on the third delay amount, and the predetermined time If the third delay amount cannot be calculated, the phase of the main data signal taken into the fetch unit is delayed based on the initial delay amount.
A data transfer device. The data transfer device according to claim 1, wherein
The third delay amount is given by
(Second delay amount−first delay amount) / 2 + first delay amount
Calculated by
A data transfer device. The data transfer device according to claim 1 or 2,
An imaging unit that images a subject and outputs an image data signal as the main data signal;
The imaging unit outputs the test data signal having a data amount output during the predetermined time, and outputs the image data signal following the test data signal.
An electronic camera characterized by The electronic camera according to claim 3.
The data amount of the test data signal is determined according to the resolution of the image.
An electronic camera characterized by The electronic camera according to claim 3.
The data amount of the test data signal should be determined according to the shooting conditions.
An electronic camera characterized by

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